CN111522181A - Array substrate, display panel and preparation method thereof - Google Patents
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- CN111522181A CN111522181A CN202010344750.6A CN202010344750A CN111522181A CN 111522181 A CN111522181 A CN 111522181A CN 202010344750 A CN202010344750 A CN 202010344750A CN 111522181 A CN111522181 A CN 111522181A
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- 239000000758 substrate Substances 0.000 title claims abstract description 52
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000010409 thin film Substances 0.000 claims abstract description 30
- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- 238000010030 laminating Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Crystallography & Structural Chemistry (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
The application discloses an array substrate, a display panel and a preparation method of the display panel, wherein the array substrate comprises a transparent substrate and a pixel structure arranged on the transparent substrate; the pixel structure includes: scan lines and data lines crossing each other; a pixel region defined by the scan lines and the data lines crossing each other; a thin film transistor region formed at an intersection of the scan line and the data line; in the pixel region, a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode are sequentially stacked on one side of the transparent substrate; and a light transmission part is arranged below the active layer and corresponds to the active layer, and light is transmitted and irradiated to the active layer through the light transmission part. Compared with the pixel structure in the prior art in which the active layer is completely shielded, the pixel structure has the advantages that the pixel aperture opening ratio is improved by 3-8%, and the problem of capacitance structure change caused by the change of the pixel structure is solved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a display panel and a preparation method of the array substrate.
Background
The viewing angle and transmittance are key parameters of a Liquid Crystal Display (LCD) panel. For a Vertically Aligned (VA) display mode LCD panel, increasing the number of pixel domains (domains) from 4 to 8 can significantly increase the viewing angle. But simultaneously, the voltage difference between two sides of the liquid crystal of the Sub-Pixel in the 8-domain Pixel is small, the area occupation ratio of the Sub-Pixel is large, and the penetration rate of the Sub-Pixel (Sub Pixel) is obviously lower than that of the main Sub-Pixel (main Pixel). In addition, since the driving circuit of the pixel is changed from one TFT (thin film transistor) to three TFTs from 4-domain pixels to 8-domain pixels, the occupied area is larger, the light transmission area of the pixel is reduced, and the transmittance of the pixel is further reduced. Thus, improving pixel transmittance has been the direction of research and development efforts for LCD panels.
An active layer in a pixel region in an 8-domain 3T (8-domain 3 transistor) pixel structure prepared in the prior art usually uses an a-Si material, and the material is converted from a semiconductor to a conductor under the irradiation of a backlight source, so that capacitance between a pixel electrode and a share electrode (common electrode) is changed, on one hand, the capacitance structure of the pixel deviates from a designed value, and on the other hand, under the irradiation of a scanning backlight source, the capacitance is switched between two states, so that the brightness of the pixel varies, and the abnormality is caused. The metal layer is usually provided to completely shield the active layer from the backlight, but this widens the opaque region of the pixel region and further reduces the pixel aperture ratio.
Disclosure of Invention
In order to solve the problems in the prior art, an object of the present application is to provide an array substrate, a display panel and a manufacturing method thereof, which can improve the pixel transmittance.
The application provides an array substrate, which comprises a transparent substrate and a pixel structure arranged on the transparent substrate; the pixel structure includes:
scan lines and data lines crossing each other;
a pixel region defined by the scan lines and the data lines crossing each other;
a thin film transistor region formed at an intersection of the scan line and the data line;
in the pixel region, a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode are sequentially stacked on one side of the transparent substrate;
and a light transmission part is arranged below the active layer and corresponds to the active layer, and light is transmitted and irradiated to the active layer through the light transmission part.
In some embodiments, the first metal layer includes a common electrode, and a through hole is opened in the first metal layer in the light transmitting portion, and corresponds to an orthographic projection of the active layer on the first metal layer.
In some embodiments, the light-transmitting portion extends from one end to the other end of the pixel region.
In some embodiments, the width of the light-transmitting portion is greater than or equal to the width of the active layer.
In some embodiments, the width of the pixel electrode is less than or equal to the width of the active layer.
In some embodiments, the active layer has light stability.
In some embodiments, the active layer has a forbidden band width greater than 3 eV.
In some embodiments, the thin film transistor region is provided with a main region thin film transistor, a sub region thin film transistor and a shared thin film transistor, the second metal layer includes a source or a drain of the shared thin film transistor, and the light-transmitting portion is provided corresponding to the source and/or the drain.
The application also provides a display panel, which comprises the array substrate.
The application also provides a preparation method of the array substrate, which comprises the following steps:
providing a transparent substrate; forming a scanning line and a data line on the transparent substrate, wherein the scanning line and the data line are crossed with each other to define a pixel area;
sequentially laminating a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode on the transparent substrate, and forming a thin film transistor region at the intersection of the scanning line and the data line;
and a light-transmitting part is formed below the active layer and corresponding to the active layer, and light is transmitted and irradiated to the active layer through the light-transmitting part.
Compared with the pixel structure in the prior art in which the active layer is completely shielded, the pixel structure has the advantages that the pixel aperture opening ratio is improved by 3-8%, and the problem of capacitance structure change caused by the change of the pixel structure is solved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a plan view illustrating an array substrate of the present application.
Fig. 2 is a schematic cross-sectional view illustrating the array substrate of fig. 1 taken along line a-a'.
Fig. 3 is a schematic structural diagram of a display panel according to the present application.
Fig. 4 is a schematic flow chart illustrating a method for manufacturing an array substrate according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Specifically, please refer to fig. 1, which is a schematic top view of the array substrate provided in the present application. The embodiment of the application provides an array substrate, which comprises a transparent substrate 10 and a pixel structure arranged on the transparent substrate 10; the pixel structure includes: scanning lines 21 and data lines 22 crossing each other; a pixel region 23 defined by the scan line 21 and the data line 22 crossing each other; a thin film transistor region 24 formed at the intersection of the scan line 21 and the data line 22; the thin film transistor region 24 includes a main region thin film transistor, a sub region thin film transistor, and a shared thin film transistor 241. An opaque region 230 is provided in the pixel region 23, and the opaque region 230 extends from one end of the pixel region 23 to the other end.
Fig. 2 is a schematic cross-sectional view illustrating a non-light-transmitting region a-a' in the pixel region of fig. 1, and referring to fig. 1 and 2, a first metal layer, a first insulating layer 231, an active layer 232, a second metal layer 233, a second insulating layer 234, and a pixel electrode 235 are sequentially stacked on one side of a transparent substrate 10; the first metal layer includes a common electrode and a gate electrode of the tft area 24, the first insulating layer 231 is a gate insulating layer for insulating and separating the active layer 232 and the first metal layer, the second metal layer 233 includes a source/drain electrode of the tft area 24, a common electrode (share electrode) sharing the source or drain of the tft 241, and the second insulating layer 234 covers the active layer 232 and planarizes the pixel area 23. A light-transmitting portion 236 is disposed below the active layer 232 corresponding to the active layer 232, and the light-transmitting portion 236 allows light to transmit and irradiate the active layer 232.
A through hole is opened in the first metal layer in the light-transmitting portion 236, and the through hole corresponds to an orthographic projection of the active layer 232 on the first metal layer.
The light-transmitting portion 236 extends from one end to the other end of the pixel region 23.
The width of the light-transmitting portion 236 is greater than or equal to the width of the active layer 232.
The width of the pixel electrode 235 is less than or equal to the width of the active layer 232.
In the prior art, the first metal layer generally includes a light shielding portion disposed below the active layer 232 and corresponding to the active layer 232, in order to completely shield the active layer 232, a width of the light shielding portion is greater than a width of the active layer 232, and a width of the opaque region 230 is defined by the width of the light shielding portion, where the light shielding portion of the first metal layer is removed to form a transparent portion, so that a width of the opaque region 230 is defined by a width d1 of the pixel electrode 235, the width of the opaque region 230 is reduced, and an aperture ratio is improved.
To ensure that the capacitance between the pixel electrode 235 and the common electrode (share electrode) does not change, the active layer has light stability. The photo-stability refers to the property that the physical properties of the active layer 232 are not changed and are not sensitive to light under the irradiation of light. In some embodiments, the active layer 232 is made of a semiconductor material with a forbidden band width greater than 3eV, which does not change from a semiconductor to a conductor under light irradiation. In some embodiments, the material of the active layer 232 may be an oxide semiconductor InGaZnO, a silicon-based nanomaterial, zinc oxide, or the like.
The present application further provides a display panel 200, which is a schematic structural diagram of the display panel 200 with reference to fig. 3. The display panel 200 includes an array substrate 100 and a color filter substrate that are oppositely disposed; the array substrate 200 and the color filter substrate are respectively provided with electrodes oppositely, alignment films are attached to the electrodes oppositely, and liquid crystal molecules are filled between the array substrate 200 and the color filter substrate.
Another exemplary embodiment of the present application provides a method for manufacturing the array substrate, which is schematically illustrated in fig. 4, and includes the following steps: providing a transparent substrate 10, depositing a first metal layer on the transparent substrate 10, performing photolithography to form a common electrode, the gates of the main thin film transistor, the sub-thin film transistor and the shared thin film transistor 241, and the scan line 21; a through hole is further formed in the first metal layer, and the through hole corresponds to an orthographic projection of the active layer 232 on the first metal layer. Depositing a first insulating layer 231 on the patterned first metal layer, wherein the first insulating layer 231 covers the through hole, and the first insulating layer 231 is used for forming a gate insulating layer; forming an active layer 232 on the gate insulating layer at a position corresponding to the via hole; depositing a second metal layer 233 on the active layer, and performing photolithography on the second metal layer 233 by using a 4Mask process Half Tone technology to form a common electrode (share electrode) sharing a source electrode or a drain electrode of the thin film transistor 241, the source electrode, the drain electrode and the data line 22; depositing a second insulating layer 234 on the active layer 232 and covering the second metal layer 233 on the active layer, wherein the second insulating layer 234 is used for covering the active layer 232 and flattening the pixel region 23; a pixel electrode 235 is deposited on the second insulating layer 234, and in some embodiments, the material of the pixel electrode 235 is indium tin oxide.
Through the above steps, the thin film transistor region 24 is formed at the intersection of the scan line 21 and the data line 22, and the main region thin film transistor, the sub region thin film transistor, and the sharing thin film transistor 241 are formed in the thin film transistor region 24.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing describes in detail an electronic device provided in an embodiment of the present application, and a specific example is applied to illustrate the principle and the implementation of the present application, and the description of the foregoing embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. The array substrate is characterized by comprising a transparent substrate and a pixel structure arranged on the transparent substrate; the pixel structure includes:
scan lines and data lines crossing each other;
a pixel region defined by the scan lines and the data lines crossing each other;
a thin film transistor region formed at an intersection of the scan line and the data line;
in the pixel region, a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode are sequentially stacked on one side of the transparent substrate;
and a light transmission part is arranged below the active layer and corresponds to the active layer, and light is transmitted and irradiated to the active layer through the light transmission part.
2. The array substrate of claim 1, wherein the first metal layer comprises a common electrode, and a via hole is formed in the first metal layer in the light-transmitting portion, the via hole corresponding to an orthographic projection of the active layer on the first metal layer.
3. The array substrate of claim 1, wherein the light-transmissive portion extends from one end of the pixel region to the other end.
4. The array substrate of claim 1, wherein the width of the light-transmitting portion is greater than or equal to the width of the active layer.
5. The array substrate of claim 1, wherein the width of the pixel electrode is less than or equal to the width of the active layer.
6. The array substrate of claim 1, wherein the active layer has light stability.
7. The array substrate of claim 6, wherein the active layer has a forbidden bandwidth greater than 3 eV.
8. The array substrate of claim 1, wherein the thin film transistor region is provided with a main region thin film transistor, a sub region thin film transistor and a shared thin film transistor, the second metal layer includes a source or a drain of the shared thin film transistor, and the light-transmitting portion is provided corresponding to the source and/or the drain.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. The preparation method of the array substrate is characterized by comprising the following steps:
providing a transparent substrate; forming a scanning line and a data line on the transparent substrate, wherein the scanning line and the data line are crossed with each other to define a pixel area;
sequentially laminating a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode on the transparent substrate, and forming a thin film transistor region at the intersection of the scanning line and the data line;
and a light-transmitting part is formed below the active layer and corresponding to the active layer, and light is transmitted and irradiated to the active layer through the light-transmitting part.
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| CN202010344750.6A CN111522181B (en) | 2020-04-27 | 2020-04-27 | Array substrate, display panel and preparation method of display panel |
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| CN202010344750.6A CN111522181B (en) | 2020-04-27 | 2020-04-27 | Array substrate, display panel and preparation method of display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113741108A (en) * | 2021-08-31 | 2021-12-03 | 惠科股份有限公司 | Array substrate, display panel and display device |
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| CN107768386A (en) * | 2017-11-16 | 2018-03-06 | 深圳市华星光电半导体显示技术有限公司 | Tft array substrate and preparation method thereof and liquid crystal display panel |
| US20180190679A1 (en) * | 2015-09-11 | 2018-07-05 | Mitsubishi Electric Corporation | Thin film transistor substrate and method for manufacturing same |
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| CN113741108A (en) * | 2021-08-31 | 2021-12-03 | 惠科股份有限公司 | Array substrate, display panel and display device |
| CN113741108B (en) * | 2021-08-31 | 2022-07-22 | 惠科股份有限公司 | Array substrate, display panel and display device |
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| Publication number | Publication date |
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| CN111522181B (en) | 2023-05-05 |
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