CN103474432A - Array substrate and preparation method and display device of array substrate - Google Patents
Array substrate and preparation method and display device of array substrate Download PDFInfo
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- CN103474432A CN103474432A CN2013103830207A CN201310383020A CN103474432A CN 103474432 A CN103474432 A CN 103474432A CN 2013103830207 A CN2013103830207 A CN 2013103830207A CN 201310383020 A CN201310383020 A CN 201310383020A CN 103474432 A CN103474432 A CN 103474432A
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- black matrix
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- 229910045601 alloy Inorganic materials 0.000 description 5
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- 229910052804 chromium Inorganic materials 0.000 description 5
- 229910003437 indium oxide Inorganic materials 0.000 description 5
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate and a preparation method and display device of the array substrate, which are used for reducing the voltage difference of common electrode layers among different pixel units, and increasing the pixel aperture ratio. The array substrate comprises a substrate, grid lines arranged on the substrate in an intersecting way, data lines, and pixel units which are formed by the division of the grid lines and the data lines and are in matrix arrangement, wherein thin film transistors, pixel electrodes and common electrode layers are arranged in the pixel units, and the thin film transistors comprise grid electrodes, first insulating layers, source electrodes, drain electrodes and active layers. The array substrate also comprises black matrixes with conductivity, which are arranged in non-display areas of the pixel units and electrically connected with the common electrode layers, and second insulating layers which are used for insulating the black matrixes and the common electrode layers from the thin film transistors, wherein the coverage areas of the second insulating layers are overlapped with the coverage areas of the black matrixes and the common electrode layers.
Description
Technical field
The present invention relates to technical field of liquid crystal display, relate in particular to a kind of array base palte and preparation method thereof and display unit.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) there are the characteristics such as volume is little, low in energy consumption, radiationless, obtained in recent years developing by leaps and bounds, in current flat panel display market, occupied leading position.TFT-LCD is widely used on various big-and-middle undersized products, the main electronic product of almost having contained current information-intensive society, as LCD TV, high definition digital television, computer, mobile phone, car-mounted display, Projection Display, video camera, digital camera, electronic watch, calculator, electronic instrument and meter, public demonstration and illusory demonstration etc.
TFT-LCD is comprised of display panels, drive circuit and backlight module, and display panels is the pith of TFT-LCD.Display panels is that surrounding seals by sealed plastic box by between array base palte and color membrane substrates, injecting liquid crystal, then on array base palte and color membrane substrates, sticks respectively that the process such as the orthogonal polarizer in polarization direction forms.Be formed with thin-film transistor, pixel electrode and peripheral circuit that matrix form is arranged on wherein said array base palte.Color membrane substrates (Color Filter, CF) by red (R), green (G), blue (B) three primary colors resin, form pixel, and be formed with transparent public electrode.
In order to block the light of transmission region, the liquid crystal panel of prior art all is provided with black matrix on color membrane substrates.In design, the width that the width of black matrix is the light leak zone with to box trueness error sum, but due to larger to the box trueness error, cause the width d1 of the black matrix be arranged on color membrane substrates generally larger, cause TFT-LCD to exist aperture opening ratio to hang down and the defects such as display brightness is low.
Simultaneously, in order to reduce the voltage differences of public electrode between pixel, for multi-dimensional electric field type TFT-LCD, there is at present design to be illustrated in fig. 1 shown below, Fig. 1 is in prior art, to be the sectional structure chart that reduces the display floater of common electrode layer resistance, make the common electrode layer 20 of electrically conducting transparent directly be placed in the metal level 11 of grid 10 with layer on, like this owing to grid 10, with layer metal level 11 material therefor arranged, being generally chromium (Cr), tungsten (W), titanium (Ti), (Ta), (Mo), (Al), (Cu) metal and the alloy thereof such as, common electrode layer 20 is generally tin indium oxide, indium zinc oxide, aluminum zinc oxide etc., the former resistivity is little more a lot of than the latter's resistivity, thereby the all-in resistance after both parallel connections is more much smaller than the resistance of common electrode layer, can effectively reduce the resistance value of common electrode layer, thereby the voltage differences of public electrode between the minimizing pixel.But, because the metal level 11 with described grid 10 same layers is non-transparent metals, therefore can cause to the aperture opening ratio of pixel very large loss.
Referring to Fig. 1 and Fig. 2, the planar structure schematic diagram that wherein Fig. 2 is the display floater shown in Fig. 1.In conjunction with Fig. 1 and Fig. 2, can find out that described display floater comprises: tft array substrate, color membrane substrates, and be arranged on the liquid crystal layer (not shown) between described array base palte and described color membrane substrates, wherein said array base palte comprises: grid 10, with described grid 10, with layer, arrange and with metal level 11 and the grid line 12 of material, the common electrode layer 20 of electrically conducting transparent, and described common electrode layer 20 covers described metal level 11; The first insulating barrier 30, active layer 40, data line layer 50(specifically comprises: data wire 501, source electrode 502 and drain electrode 503), and pixel electrode layer 60; Wherein, described grid 10, the first insulating barrier 30, active layer 40, data line layer 50 has formed a thin-film transistor, and grid line 12 is for to thin-film transistor, providing start signal, and data wire 501 is for providing data-signal to pixel electrode 60; Wherein pixel electrode 60 is also a transparency conducting layer, arranges with layer with data line layer 50, and is electrically connected to described drain electrode 503.In order to make the electric field energy between common electrode layer 20 and pixel electrode 60 be applied on the liquid crystal between array base palte and color membrane substrates, pixel electrode 60 generally is designed to the plane hollow structure, as shown in Figure 3.Can first after forming data line layer 50, composition technique form again pixel electrode layer 60 in addition on technique, also can first after forming pixel electrode layer 60, composition technique form again data line layer 50, here said composition technique mainly comprises film forming, the processes such as exposure and etching.
Described array base palte also comprises the protective layer 70 that is arranged on described thin-film transistor and pixel electrode 60 tops, and described protective layer 70 is not corroded for the protection of thin-film transistor.Described display floater also comprises the black matrix 80 be arranged on described color membrane substrates 200, and described black matrix 80 is for blocking the light leak zone.The zone that dotted line AA ' and dotted line BB ' define is that TFT regions (or is called the non-display area of pixel cell, referred to as non-display area), the viewing area (referred to as viewing area) that dotted line BB ' and dotted line CC ' institute delimited area are pixel cell.
In prior art, because described metal level 11 arranges and adopt identical making material with grid 10 with layer, material therefor is generally Cr, W, Ti, Ta, Mo, Al, metal and the alloys thereof such as Cu, can reduce to a certain extent the resistance of common electrode layer 20 after making metal level 11 and common electrode layer 20 being in parallel, but the restriction due to the width d1 of the black matrix 80 on color membrane substrates, and in order to prevent that metal level 11 and grid 10 are short-circuited, interval between described metal level 11 and grid 10 is about 5 microns (um), so the width d2 of described metal level 11 is very limited, thereby not very obvious to the resistance effect that reduces common electrode layer 20, but, the mode that reduces the resistance of common electrode layer 20 by increasing d2 length can cause d2 to enter into BB '-CC ' inside, cause pixel aperture ratio to reduce.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof and display floater, in order to reduce the voltage differences of common electrode layer between the different pixels unit, increases the aperture opening ratio of pixel simultaneously.
The array base palte that the embodiment of the present invention provides comprises: underlay substrate, on described underlay substrate arranged crosswise grid line, data wire and by described grid line and data wire, marked off be the pixel cell that matrix is arranged, be provided with thin-film transistor, pixel electrode and common electrode layer in described pixel cell, described thin-film transistor comprises grid, the first insulating barrier, active layer, source electrode and drain electrode, and described array base palte also comprises:
Be arranged on the black matrix with electric conductivity of the non-display area of pixel cell, described black matrix is electrically connected to described common electrode layer; And,
Be used for the second insulating barrier of described black matrix and common electrode layer and described film crystal pipe insulation, the covering area overlapping of the overlay area of described the second insulating barrier and described black matrix and described common electrode layer.
In described array base palte, be provided with the black matrix of conduction, described black matrix and common electrode layer are electrically connected to, the resistance of the black matrix of electrical connections is in parallel with the resistance of common electrode layer, make all-in resistance after parallel connection be less than the resistance of described common electrode layer, effectively reduce the resistance value of common electrode layer, thereby reduce the voltage differences of common electrode layer between the different pixels unit; Simultaneously, due to described black arranged in matrix on array base palte, do not need to consider the box trueness error, and, be provided with the second insulation layer by layer in this array base palte, for by described grid and described black matrix and public electrode insulation, so larger spacing distance need to be set between public electrode and grid, therefore the width of the black matrix in described array base palte diminishes than the width of black matrix in prior art, is conducive to improve the aperture opening ratio of pixel cell.
Preferably, described black arranged in matrix is between thin-film transistor and underlay substrate, and described the second insulating barrier is arranged between thin-film transistor and black matrix, can effectively stop that the illumination of backlight is mapped to active layer, has been conducive to reduce the dark current in the thin-film transistor.In addition, described black matrix can also be arranged on the top of thin-film transistor, and described the second insulating barrier is arranged between described black matrix and described thin-film transistor.
Preferably, the material of described black matrix is the non-transparent metals material; The black matrix that described non-transparent metals material is made can have conducting function and shade function simultaneously, and the resistance of metal material is much smaller than the resistance of the transparent conductive material for making common electrode layer, after the two parallel connection, make parallel resistance after the parallel connection resistance much smaller than described common electrode layer, can effectively reduce by the caused voltage differences of the resistance value of common electrode layer.
Preferably, described black matrix is positioned at the top of described common electrode layer, or described black matrix is positioned at the below of described common electrode layer, makes described black matrix and described common electrode layer be electrically connected to.
Preferably, the overlay area of the electrical connections of described black matrix and described common electrode layer and the overlay area of described grid are not overlapping, for preventing, between described common electrode layer and grid, form coupling capacitance, in order to avoid the performance of thin-film transistor is impacted.
Preferably, described array base palte also comprises passivation layer, and described passivation layer is arranged on the top of described thin-film transistor place layer, covers the upper area of described thin-film transistor and pixel electrode, and described passivation layer is not corroded mainly for the protection of thin-film transistor.
Preferably, be formed with successively described grid, described the first insulating barrier, described active layer, described source electrode and drain electrode and described pixel electrode on described the second insulating barrier;
Perhaps, be formed with successively described source electrode and drain electrode and described pixel electrode, described layer, described the first insulating barrier, the described grid of having chance with on described the second insulating barrier;
With layer, source electrode, drain electrode and pixel electrode are set in described array base palte, make described drain electrode and pixel electrode directly be electrically connected to, be conducive to reduce manufacture craft.
The embodiment of the present invention provides a kind of display unit, and described display unit comprises above-mentioned array base palte.
The embodiment of the present invention provides a kind of preparation method of array base palte, and described preparation method comprises:
Form the figure that comprises common electrode layer and have the black matrix of electric conductivity on underlay substrate, described black matrix is electrically connected to described common electrode layer, and described black arranged in matrix is at the non-display area of pixel cell;
Form the second insulating barrier on underlay substrate, the covering area overlapping of the overlay area of described the second insulating barrier and described black matrix and described common electrode layer, for by described black matrix and common electrode layer and described film crystal pipe insulation;
Form the figure that comprises thin-film transistor and pixel electrode on underlay substrate.
In the array base palte that utilizes described method to prepare, comprise the black matrix with electric conductivity that is arranged on the underlay substrate top, described black matrix is electrically connected to described common electrode layer, the resistance of the black matrix of electrical connections is in parallel with the resistance of common electrode layer, make all-in resistance after parallel connection be less than the resistance of described common electrode layer, effectively reduce the resistance value of common electrode layer, thereby reduce the voltage differences of common electrode layer between the different pixels unit; Simultaneously, due to described black arranged in matrix on array base palte, do not need to consider the box trueness error, and, be provided with the second insulating barrier in this array base palte, for by described grid and described black matrix and public electrode insulation, so larger spacing distance need to be set between public electrode and grid, therefore the width of described black matrix diminishes than the width of black matrix in prior art, is conducive to improve the aperture opening ratio of pixel cell.
Preferably, described black arranged in matrix is between thin-film transistor and underlay substrate, and described the second insulating barrier is arranged between thin-film transistor and black matrix, and the described figure that comprises black matrix and common electrode layer that forms on underlay substrate specifically comprises:
Form the figure that comprises black matrix on described underlay substrate; Form the figure that comprises common electrode layer above the described figure that comprises black matrix;
Perhaps, form the figure that comprises common electrode layer on described underlay substrate; Form the figure that comprises black matrix above the described figure that comprises common electrode layer;
Wherein, the non-display area of described black each pixel cell of Matrix cover.
Comprise in the process of the figure of deceiving matrix and common electrode layer in formation, both can first form black matrix, also can first form common electrode layer, as long as guarantee that black matrix and common electrode layer are electrically connected to; Wherein, the non-display area of described black each pixel cell of Matrix cover, for preventing seeing through of light in non-display area, be conducive to reduce the dark current in thin-film transistor.
Preferably, form the figure that comprises thin-film transistor and pixel electrode on underlay substrate, specifically comprise:
The top of described the second insulating barrier forms the figure that comprises grid and grid line;
Form the first insulating barrier above the described figure that comprises grid and grid line;
Form the figure that comprises active layer above described the first insulating barrier;
Form the figure that comprises source electrode, drain electrode and pixel electrode above the described figure that comprises active layer.
Perhaps, form the figure that comprises thin-film transistor and pixel electrode above described the second insulating barrier, specifically comprise:
The top of described the second insulating barrier forms the figure that comprises source electrode, drain electrode and pixel electrode;
Form the figure that comprises active layer above the described figure that comprises source electrode, drain electrode and pixel electrode;
Form the first insulating barrier above the described figure that comprises active layer;
Form the figure that comprises grid and grid line above described the first insulating barrier.
In the process that forms described thin-film transistor and pixel electrode, form the figure that comprises source electrode, drain electrode and pixel electrode with layer, make described drain electrode and pixel electrode directly be electrically connected to, be conducive to reduce manufacture craft.
Preferably, described method also comprises: form passivation layer above the described figure that comprises thin-film transistor and pixel electrode, described passivation layer covers the upper area of described thin-film transistor and pixel electrode, for preventing thin-film transistor, is corroded.
The accompanying drawing explanation
The cross-sectional view that Fig. 1 is a kind of display floater of the prior art;
The planar structure schematic diagram that Fig. 2 is display floater shown in Fig. 1;
The plane structure chart that Fig. 3 is pixel electrode;
The cross-sectional view of a kind of array base palte that Fig. 4 provides for the embodiment of the present invention one;
The planar structure schematic diagram that Fig. 5 is the array base palte shown in Fig. 4;
The cross-sectional view of a kind of array base palte that Fig. 6 provides for the embodiment of the present invention two;
The cross-sectional view of a kind of array base palte that Fig. 7 provides for the embodiment of the present invention three;
The cross-sectional view of a kind of array base palte that Fig. 8 provides for the embodiment of the present invention four;
The cross-sectional view of the array base palte that Fig. 9 has been black matrix and common electrode layer making;
The cross-sectional view of the array base palte that Figure 10 has been the second insulating barrier making;
The cross-sectional view of the array base palte that Figure 11 has been the thin-film transistor making;
The cross-sectional view of the array base palte that Figure 12 has been the pixel electrode making;
In the process that Figure 13 is the array base palte that provides in Preparation Example two, complete the cross-sectional view of the array base palte after black matrix and common electrode layer are made.
Embodiment
The embodiment of the present invention provides a kind of array base palte and preparation method thereof and display floater, in order to reduce the voltage differences of common electrode layer between the different pixels unit, increases the aperture opening ratio of pixel simultaneously.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.
The embodiment of the present invention one provides a kind of array base palte, referring to Fig. 4 and Fig. 5, and the cross-sectional view of the array base palte that wherein Fig. 4 provides for the embodiment of the present invention one, the planar structure schematic diagram that Fig. 5 is array base palte shown in Fig. 4.In conjunction with Fig. 4 and Fig. 5, can find out that described array base palte comprises: underlay substrate 1001, black matrix 80, common electrode layer 20, the second insulating barrier 90, grid 10, grid line 12, the first insulating barrier 30, active layer 40, data line layer 50(specifically comprise: data wire 501, source electrode 502, drain 503) and pixel electrode 60;
Concrete, described black matrix 80 is positioned at the top of described underlay substrate 1001, the material of described black matrix is the non-transparent metals material, the black matrix that described employing non-transparent metals material is made can have conducting function and shade function simultaneously, and the resistance of metal material is much smaller than for utilizing the resistance of other nontransparent electric conducting material.
The width of described black matrix 80 is d3, and it covers the non-display area of each pixel cell, for preventing seeing through of light in non-display area; Because described black matrix 80 is arranged on array base palte, therefore, when the black matrix 80 of design, do not need to consider the box trueness error, be conducive to reduce the size of black matrix, improve the aperture opening ratio of pixel;
In addition, described black matrix 80 can also cover the channel region of active layer 40, makes the light that shines active layer 40 all be covered, and then reduces the leakage current of active layer.
Described common electrode layer 20 is positioned at the top of described black matrix 80 place layers, and is electrically connected to described black matrix 80, and the material of described common electrode layer 20 is generally the transparent oxides such as tin indium oxide, indium zinc oxide or aluminum zinc oxide.
Described black matrix 80 is d4 with the width of the electrical connections of described common electrode layer 20, the overlay area of the overlay area of described electrical connections and described grid 10 is not overlapping, for preventing from forming coupling capacitance between described common electrode layer 20 and grid 10, in order to avoid affect the performance of thin-film transistor.The overlay area of indication refers to the view field of dependency structure (for example electrical connections or the grid of described black matrix and described common electrode layer) on underlay substrate herein.
Electrical connections at described black matrix 80 with described common electrode layer 20, the resistance of the black matrix of electrical connections is in parallel with the resistance of described common electrode layer 20, due to the resistance value of the described electrical connections resistance much smaller than described common electrode layer 20, therefore, the resistance of the all-in resistance after parallel connection is much smaller than the resistance of described common electrode layer 20, and then makes by the caused voltage differences of the resistance of common electrode layer 20 and reduce.
Described the second insulating barrier 90, be arranged between described common electrode layer 20 place layers and described grid 10 and grid line 12 place layers, the covering area overlapping of the overlay area of described the second insulating barrier and described black matrix and described common electrode layer, be the upper area that described the second insulating barrier covers described black matrix 80 and described common electrode layer 20, for the grid 10 by described thin-film transistor and described black matrix 80 and 20 insulation of described common electrode layer.Therefore, in this array base palte, do not need to consider the spacing distance between common electrode layer 20 and grid line 10.Be conducive to further reduce the size of black matrix, improve the aperture opening ratio of pixel.
Described grid 10 arranges with layer with grid line 12, all between described the first insulating barrier 30 and the second insulating barrier 90, and described grid 10 adopts identical making material with described grid line 12, and making material used is generally non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu.
Described the first insulating barrier 30 is positioned at the top of described grid 10 and grid line 12, covers the upper area of described grid 10 and grid line 12; In the present embodiment, the making material of described the first insulating barrier 30 is photoresist, and its thickness is about 20000 Ethylmercurichlorendimides, and simultaneously, described the first insulating barrier 30 can also be with other insulating layer material, and thickness should be determined according to actual needs.
Described active layer 40 is positioned at the top of described the first insulating barrier 30;
Described data wire 501, source electrode 502 and the 503 same layers that drain arrange, and are positioned at the top of described active layer 40 place layers, and adopt identical material to make;
Described data wire 501 is electrically connected to described source electrode 502, and arranged in a crossed manner with grid line 12;
The relative both sides that described source electrode 502 is positioned at described active layer 40 tops with drain electrode 503.
Described pixel electrode 60 arranges with described data wire 501, source electrode 502, the 503 same layers that drain, and described pixel electrode 60 is electrically connected to described drain electrode 503, described pixel electrode generally adopts the transparent oxide materials such as tin indium oxide, indium zinc oxide or aluminum zinc oxide to make, and described pixel electrode is slit-shaped.
Described array base palte also comprises the passivation layer 70 that is positioned at described data wire 501, source electrode 502 and 503 tops that drain, and described passivation layer 70 is not corroded for the protection of thin-film transistor; Described passivation layer 70 adopts the transparent insulation materials such as silicon nitride or silica to form.
In order better to explain the impact of present design on aperture opening ratio and grid line and the data wire of thin-film transistor pixel, now take pixel cell in the display floater shown in Fig. 2 and the pixel cell in the array base palte shown in Fig. 5 and describe as example:
Fig. 2 is the pixel cell structure schematic diagram in the display floater designed in prior art, and specifically the material of each layer film and thickness data refer to table 1;
The material of each layer film and thickness data in table 1 prior art
Pixel cell planar structure schematic diagram in the array base palte that Fig. 5 provides for the embodiment of the present invention one, specifically the material of each layer film and thickness data refer to table 2;
The material of each layer film and thickness data in the array base palte that table 2 embodiment of the present invention one provides
And Fig. 2 and Fig. 5 are the dot structure figure of 5.2 inches that resolution is 480 * 272, pixel cell size is 80 * 240um, and grid line 12 live widths are 6um, and data wire 501 live widths are 4um.
As calculated, the grid line resistance of each pixel cell of above-mentioned two kinds of designs and the resistance of data wire 501 can not change, in structure pixel cell as shown in Figure 2, and the grid line capacitor C
gate=5.91 * 10
-14f, data line capacitance C
data=9.56 * 10
-14f, suppose that its picture scanning frequency is 60Hz, and when the pixel charge rate is 99.99%, in described pixel cell, the width of thin-film transistor and length need to be designed to respectively 16um and 5um;
The Anawgy accuracy of supposing array base palte and color membrane substrates is 7.5um, in structure in pixel cell as described in Figure 5, and the grid line capacitor C
gate=3.72 * 10
-13f, data line capacitance C
data=2.19 * 10
-13f, be 60Hz in the picture scanning frequency, and when the pixel charge rate is 99.99%, the width of the thin-film transistor in this pixel cell and length need to be designed to respectively 17um and 5um.
In sum, in the described pixel cell of Fig. 5, due to the introducing of black matrix, the grid line electric capacity that can cause each pixel cell is by original 5.91 * 10
-14f increases to 3.72 * 10
-13f, the data line capacitance of each pixel cell is by original 9.56 * 10
-14f increases to 2.19 * 10
-13f, and the increase of electric capacity can cause the delay of grid line and data wire to increase, and then cause the charging interval of each pixel cell to reduce, need to increase charging current for this reason, therefore, in the array base palte provided at embodiment mono-, the width of thin-film transistor, length need to need to be designed to respectively to 17um, 5um for increasing charging current, to guarantee the normal demonstration of pixel cell.Although the introducing of described black matrix can increase the electric capacity of grid line and data wire, and then cause the width of thin-film transistor to increase (can cause aperture opening ratio to reduce), but because black matrix in parallel with common electrode layer in this pixel cell and grid line layer are non-with layer design, need between black matrix and grid line layer, larger interval be set, and do not need to consider the box trueness error, therefore the aperture opening ratio of pixel cell increases as a complete unit, and the aperture opening ratio of whole pixel increases to 75.5% by original 72%.
The embodiment of the present invention two also provides a kind of array base palte, its cross-section structure as shown in Figure 6, as can be seen from Figure 6, the structure of the array base palte shown in this array base palte and Fig. 4 is basic identical, both difference parts are: in the array base palte shown in Fig. 4, black matrix 80 is between underlay substrate 1001 and described common electrode layer 20; And, in the array base palte shown in Fig. 6, black matrix 80 is between the second insulating barrier 90 and described common electrode layer 20.
The embodiment of the present invention three also provides a kind of array base palte, its cross-section structure as shown in Figure 7, from 7, can find out, the structure of the array base palte shown in this array base palte and Fig. 4 is basic identical, both difference parts are: the array base palte that the array base palte shown in Fig. 4 is bottom grating structure, and the array base palte that the array base palte shown in Fig. 7 is top gate structure, concrete, in array base palte shown in Fig. 7, described data wire 501, the top that is positioned at described the second insulating barrier 90 of source electrode 502 and drain electrode 503, described active layer 40 is positioned at the described data wire 501 that comprises, the top of the figure of source electrode 502 and drain electrode 503, described the first insulating barrier 30 is positioned at the top of described active layer 40, described grid 10 and grid line 12 are positioned at the top of described the first insulating barrier 30.And due to described pixel electrode 60 and described data wire 501, source electrode 502 with drain and 503 arrange with layer, therefore in the array base palte shown in Fig. 7, described pixel electrode 60 is arranged between described the first insulating barrier 30 and the second insulating barrier 90.
The embodiment of the present invention four also provides a kind of array base palte, its cross-section structure as shown in Figure 8, as can be seen from Figure 8, the structure of the array base palte shown in described array base palte and Fig. 7 is basic identical, both differences are: in the array base palte shown in Fig. 7, black matrix 80 is between underlay substrate 1001 and described common electrode layer 20; And, in the array base palte shown in Fig. 8, black matrix 80 is between the second insulating barrier 90 and described common electrode layer 20.
In the array base palte that above-described embodiment one, embodiment bis-, embodiment tri-and embodiment tetra-provide, include the black matrix with conductivity that is arranged on the underlay substrate top, described black matrix and common electrode layer are electrically connected to, the resistance of the black matrix of electrical connections is in parallel with the resistance of common electrode layer, make the all-in resistance of the electrical connections after parallel connection be less than the resistance of the common electrode layer of this electrical connections, effectively reduce the resistance value of common electrode layer, thereby reduced the voltage differences of common electrode layer between the different pixels unit; Simultaneously, due to described black arranged in matrix, on array base palte, do not need to consider the box trueness error, be conducive to reduce the width dimensions of black matrix, improve the aperture opening ratio of pixel; Simultaneously, also be provided with the second insulation layer by layer in this array base palte, be used for described grid and described black matrix and public electrode insulation, so larger spacing distance need to be set between common electrode layer and grid for preventing grid and common electrode layer short circuit, be conducive to further reduce the size of black matrix, improve the aperture opening ratio of pixel.
Be pointed out that, described black matrix can also be arranged on the top of thin-film transistor, concrete, described the second insulating barrier is arranged on the top of film crystal, described black arranged in matrix is above the second insulating barrier, described common electrode layer is arranged on the top/below of described black matrix and is electrically connected to black matrix, described passivation layer is arranged on the top of described common electrode layer and black matrix, described pixel electrode is arranged on the top of described passivation layer, wherein, described pixel electrode is slit-shaped, and described public electrode is tabular or slit-shaped;
Perhaps, described the second insulating barrier is arranged on the top of thin-film transistor, described pixel electrode is arranged on the below of the second insulating barrier, described common electrode layer is arranged on the top of thin-film transistor, described black arranged in matrix above the second insulating barrier, common electrode layer above or below, and with described common electrode layer, be electrically connected to, described passivation layer is arranged on the top of described black matrix and common electrode layer; Wherein, described public electrode is slit-shaped, and described pixel electrode is tabular or slit-shaped.
The preparation method of a kind of array base palte that the embodiment of the present invention five provides, described method comprises:
Form the figure that comprises common electrode layer and have the black matrix of electric conductivity on underlay substrate, described black matrix is electrically connected to described common electrode layer, and described black arranged in matrix is at the non-display area of pixel cell;
Form the second insulating barrier on underlay substrate, the covering area overlapping of the overlay area of described the second insulating barrier and described black matrix and described common electrode layer, for by described black matrix and common electrode layer and film crystal pipe insulation;
Form the figure that comprises thin-film transistor and pixel electrode on underlay substrate.
In the array base palte that utilizes described method to prepare, comprise the black matrix with electric conductivity that is arranged on the underlay substrate top, described black matrix is electrically connected to described common electrode layer, the resistance of the black matrix of electrical connections is in parallel with the resistance of common electrode layer, make all-in resistance after parallel connection be less than the resistance of described common electrode layer, effectively reduce the resistance value of common electrode layer, thereby reduce the voltage differences of common electrode layer between the different pixels unit; Simultaneously, due to described black arranged in matrix on array base palte, do not need to consider the box trueness error, and, be provided with the second insulation layer by layer in this array base palte, for by described grid and described black matrix and public electrode insulation, so larger spacing distance need to be set between public electrode and grid, therefore the width of described black matrix diminishes than the width of black matrix in prior art, is conducive to improve the aperture opening ratio of pixel cell.
The array base palte that the embodiment of the present invention one of below take provides is example, introduces in detail in actual preparation technology, and the preparation method of described array base palte, the method specifically comprises:
The first step referring to Fig. 9, forms the figure that comprises black matrix 80 and common electrode layer 20 on underlay substrate 1001; Concrete, this step comprises:
The nontransparent metallic film of deposition one deck on underlay substrate 1001, then by the composition PROCESS FOR TREATMENT, form the figure that comprises black matrix 80, and described black matrix 80 covers the non-display area of each pixel cell; Wherein, in the present embodiment, described composition technique comprises: at first, form nontransparent metallic film that (as sputter or coating etc.) one deck is used to form black matrix on underlay substrate 1001; Then, apply one deck photoresist on metallic film; Then, with the mask plate that is provided with the figure that comprises black matrix, photoresist is exposed; Finally by forming the figure that comprises black matrix 80 after development, etching.In the preparation method of the present embodiment array base palte, the preparation technology who relates to the rete formed by composition technique is identical therewith, after this no longer is described in detail.
Above the described figure that comprises black matrix 80, use magnetron sputtering method deposition indium oxide layer tin transparent conductive film, and, by composition technique, form the figure that comprises common electrode layer 20; Described common electrode layer 20 is electrically connected to described black matrix, the width of its electrical connections is d4, owing to not needing to consider the interval between common electrode layer and grid, so the width d4 of this electrical connections is greater than the width d2 of the electrical connections of metal level and public electrode wire in prior art.
Second step, referring to Figure 10, deposited silicon nitride (SiN above the described figure that comprises black matrix 80 and common electrode layer 20
x) or silica (SiO
x) layer, forming the second insulating barrier 90, described second gate insulating barrier 90 is for covering the upper area of described black matrix 80 and common electrode layer 20, for will described black matrix 80 and common electrode layer 20 and film crystal pipe insulation.
The 3rd step referring to Figure 11, forms the figure that comprises thin-film transistor above described the second insulating barrier 90, and this step specifically comprises:
One, deposition layer of metal film on deposition above described the second insulating barrier 90, then by the composition PROCESS FOR TREATMENT, formation comprises that grid 10 and grid line 12(are shown in Fig. 5) figure, the described material that is used to form metallic film is non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu;
Two, deposited silicon nitride (SiN above the described figure that comprises grid 10 and grid line 12
x) or silica (SiO
x) layer, forming the first insulating barrier 30, described first grid insulating barrier 30 is for covering the upper area of described grid line and grid, for grid line and grid are insulated with other layer;
Three, deposited amorphous silicon semiconductor material above described the first insulating barrier 30, then form by composition technique the figure that comprises active layer 40;
Four, above the described figure that comprises active layer 40, metallic film is leaked in the formation source, then by composition technique, forms and comprises data wire 501, source electrode 502 and 503 the figure of draining.
The 4th step, referring to Figure 12, use magnetron sputtering method deposition indium oxide layer tin transparent conductive film above described the first insulating barrier 30, and by composition technique, formation comprises the figure of pixel electrode 60, described pixel electrode 60 arranges with described data wire 501, source electrode 502, the 503 same layers that drain, and described pixel electrode 60 is electrically connected to described drain electrode 503.
The 5th step, referring to Fig. 4, deposited silicon nitride or silicon oxide layer above the described figure that comprises pixel electrode, form passivation layer 70, for the protection of thin-film transistor, is not corroded.
Through above-mentioned steps, form that the embodiment of the present invention one is that provide, structure array base palte as shown in Figure 4.
Should be noted, in the above-mentioned process for preparing array base palte, form again pixel electrode after can first forming thin-film transistor, form again thin-film transistor after also can first forming pixel electrode.
The array base palte provided for the embodiment of the present invention two, its preparation method is similar with the method for the array base palte that the preparation embodiment of the present invention one provides, difference is, referring to Figure 13, in the process of the array base palte provided in the making embodiment of the present invention two, the described figure that comprises black matrix and common electrode layer that forms on underlay substrate specifically comprises:
1), use magnetron sputtering method deposition indium oxide layer tin transparent conductive film on underlay substrate 1001, and, by composition technique, form the figure that comprises common electrode layer 20;
2), the nontransparent metallic film of deposition one deck above the described figure that comprises common electrode layer 20, then by the composition PROCESS FOR TREATMENT, form the figure that comprises black matrix 80, and described black matrix 80 covers the non-display area of each pixel cell;
Wherein, described common electrode layer 20 is electrically connected to described black matrix, the width of its electrical connections is d4, owing to not needing to consider the interval between common electrode layer and grid, so the width d4 of this electrical connections is greater than the width d2 of the electrical connections of metal level and public electrode wire in prior art; .
The array base palte provided for the embodiment of the present invention three, its preparation method is similar with the method for the array base palte that the preparation embodiment of the present invention one provides, difference is, referring to Fig. 7, in the process of the array base palte provided in the making embodiment of the present invention three, described formation comprises the figure of thin-film transistor and pixel electrode, specifically comprises:
A), metallic film is leaked in the formation source, top of described the second insulating barrier 90, then by composition technique, forms and comprises data wire 501, source electrode 502 and 503 the figure of draining;
B), use magnetron sputtering method deposition indium oxide layer tin transparent conductive film above described the second insulating barrier 90, and by composition technique, formation comprises the figure of pixel electrode 60, described pixel electrode 60 arranges with described data wire 501, source electrode 502, the 503 same layers that drain, and described pixel electrode 60 is electrically connected to described drain electrode 503;
C), described comprise data wire 501, source electrode 502 and 503 the figure of draining above deposited semiconductor material, then by composition technique, form the figure that comprises active layer 40;
D), deposited silicon nitride or silicon oxide layer above the described figure that comprises active layer 40, form the first insulating barrier 30, and described first grid insulating barrier 30 is for covering the upper area of described active layer 40, for by described active layer 40 and other layer insulation;
E), deposition layer of metal film above described the first insulating barrier 30, then by the composition PROCESS FOR TREATMENT, form and comprise that grid 10 and grid line 12(are shown in Fig. 4) figure, the described material that is used to form metallic film is non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu.
The array base palte provided for the embodiment of the present invention four, its preparation method is similar with the method for the array base palte that the preparation embodiment of the present invention three provides, difference is, referring to Fig. 8, in the process of the array base palte provided in the preparation embodiment of the present invention four, the described figure that comprises black matrix and common electrode layer that forms on underlay substrate specifically comprises:
1), use magnetron sputtering method deposition indium oxide layer tin transparent conductive film on underlay substrate 1001, and, by composition technique, form the figure that comprises common electrode layer 20;
2), the nontransparent metallic film of deposition one deck above the described figure that comprises common electrode layer 20, then by the composition PROCESS FOR TREATMENT, form the figure that comprises black matrix 80, and described black matrix 80 covers the non-display area of each pixel cell;
Wherein, described common electrode layer 20 is electrically connected to described black matrix, the width of its electrical connections is d4, owing to not needing to consider the interval between common electrode layer and grid, so the width d4 of this electrical connections is greater than the width d2 of the electrical connections of metal level and public electrode wire in prior art.
Be pointed out that, in the present invention, described composition technique, can only include photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refer to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.The corresponding composition technique of formed structure choice in can be according to the present invention.
In addition, all be arranged on the array base palte of thin-film transistor top for black matrix, common electrode layer and the second insulating barrier, its manufacture method comprises:
Form the figure that comprises thin-film transistor on underlay substrate, form successively the second insulating barrier and comprise the figure of common electrode layer and black matrix above the described figure that comprises thin-film transistor, form passivation layer above the described figure that comprises common electrode layer and black matrix, form the figure that comprises pixel electrode above described passivation layer, wherein, pixel electrode is slit-shaped, and described common electrode layer is tabular or slit-shaped;
Perhaps, form the figure that comprises thin-film transistor on underlay substrate, form successively figure and the second insulating barrier that comprises pixel electrode above the described figure that comprises thin-film transistor, form the figure that comprises common electrode layer and black matrix above described the second insulating barrier, form passivation layer above the described figure that comprises common electrode layer and black matrix, wherein, wherein, pixel electrode is slit-shaped or tabular, and described common electrode layer is slit-shaped.
To sum up, in the array base palte that the embodiment of the present invention provides, comprise the black matrix with conductivity that is arranged on the underlay substrate top, described black matrix and common electrode layer are electrically connected to, the resistance of the black matrix of electrical connections is in parallel with the resistance of common electrode layer, make the all-in resistance of the electrical connections after parallel connection be less than the resistance of the common electrode layer of this electrical connections, effectively reduce the resistance value of common electrode layer, thereby reduced the voltage differences of common electrode layer between the different pixels unit; Simultaneously, due to described black arranged in matrix, on array base palte, do not need to consider the box trueness error, be conducive to reduce the width dimensions of black matrix, improve the aperture opening ratio of pixel; Simultaneously, also be provided with the second insulation layer by layer in this array base palte, be used for described grid and described black matrix and public electrode insulation, so larger spacing distance need to be set between common electrode layer and grid for preventing grid and common electrode layer short circuit, be conducive to further reduce the size of black matrix, improve the aperture opening ratio of pixel.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (15)
1. an array base palte, described array base palte comprises underlay substrate, on described underlay substrate arranged crosswise grid line, data wire and by described grid line and data wire, marked off be the pixel cell that matrix is arranged, be provided with thin-film transistor, pixel electrode and common electrode layer in described pixel cell, described thin-film transistor comprises grid, the first insulating barrier, active layer, source electrode and drain electrode, it is characterized in that, described array base palte also comprises:
Be arranged on the black matrix with electric conductivity of the non-display area of pixel cell, described black matrix is electrically connected to described common electrode layer; And,
Be used for the second insulating barrier of described black matrix and common electrode layer and described film crystal pipe insulation, the covering area overlapping of the overlay area of described the second insulating barrier and described black matrix and described common electrode layer.
2. array base palte as claimed in claim 1, is characterized in that, described black arranged in matrix is between described thin-film transistor and described underlay substrate, and described the second insulating barrier is arranged between described thin-film transistor and described black matrix.
3. array base palte as claimed in claim 1, is characterized in that, described black arranged in matrix is above described thin-film transistor, and described the second insulating barrier is arranged between described black matrix and described thin-film transistor.
4. array base palte as claimed in claim 2, is characterized in that, the material of described black matrix is the non-transparent metals material.
5. array base palte as claimed in claim 2, is characterized in that, described black matrix is positioned at the top of described common electrode layer, or described black matrix is positioned at the below of described common electrode layer.
6. array base palte as claimed in claim 2, is characterized in that, the overlay area of the electrical connections of described black matrix and described common electrode layer and the overlay area of described grid are not overlapping.
7. array base palte as claimed in claim 1, is characterized in that, described array base palte also comprises passivation layer, and described passivation layer is arranged on the top of described thin-film transistor place layer, covers the upper area of described thin-film transistor and pixel electrode.
8. array base palte as claimed in claim 7, is characterized in that, is formed with successively described grid, described the first insulating barrier, described active layer, described source electrode and drain electrode and described pixel electrode on described the second insulating barrier.
9. array base palte as claimed in claim 7, is characterized in that, is formed with successively described source electrode and drain electrode and described pixel electrode, described layer, described the first insulating barrier, the described grid of having chance with on described the second insulating barrier.
10. a display unit, is characterized in that, described display unit comprises the arbitrary described array base palte of claim 1～9.
11. the preparation method of an array base palte, is characterized in that, described preparation method comprises:
Form the figure that comprises common electrode layer and have the black matrix of electric conductivity on underlay substrate, described black matrix is electrically connected to described common electrode layer, and described black arranged in matrix is at the non-display area of pixel cell;
Form the second insulating barrier on underlay substrate, the covering area overlapping of the overlay area of described the second insulating barrier and described black matrix and described common electrode layer, for by described black matrix and common electrode layer and described film crystal pipe insulation;
Form the figure that comprises thin-film transistor and pixel electrode on underlay substrate.
12. preparation method as claimed in claim 11, it is characterized in that, described black arranged in matrix is between described thin-film transistor and described underlay substrate, described the second insulating barrier is arranged between described thin-film transistor and described black matrix, the described figure that comprises black matrix and common electrode layer that forms on underlay substrate specifically comprises:
Form the figure that comprises black matrix on described underlay substrate; Form the figure that comprises common electrode layer above the described figure that comprises black matrix;
Perhaps, form the figure that comprises common electrode layer on described underlay substrate; Form the figure that comprises black matrix above the described figure that comprises common electrode layer;
Wherein, the non-display area of described black each pixel cell of Matrix cover.
13. preparation method as claimed in claim 12, is characterized in that, forms the figure that comprises thin-film transistor and pixel electrode on underlay substrate, specifically comprises:
The top of described the second insulating barrier forms the figure that comprises grid and grid line;
Form the first insulating barrier above the described figure that comprises grid and grid line;
Form the figure that comprises active layer above described the first insulating barrier;
Form the figure that comprises source electrode, drain electrode and pixel electrode above the described figure that comprises active layer.
14. preparation method as claimed in claim 12, is characterized in that, forms the figure that comprises thin-film transistor and pixel electrode on underlay substrate, specifically comprises:
The top of described the second insulating barrier forms the figure that comprises source electrode, drain electrode and pixel electrode;
Form the figure that comprises active layer above the described figure that comprises source electrode, drain electrode and pixel electrode;
Form the first insulating barrier above the described figure that comprises active layer;
Form the figure that comprises grid and grid line above described the first insulating barrier.
15. preparation method as claimed in claim 12, is characterized in that, described method also comprises:
Form passivation layer above the described figure that comprises thin-film transistor and pixel electrode, described passivation layer covers the upper area of described thin-film transistor and pixel electrode.
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| PCT/CN2013/088834 WO2015027609A1 (en) | 2013-08-28 | 2013-12-09 | Array substrate and manufacturing method therefor, and display device |
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|---|---|
| CN103474432B (en) | 2016-01-06 |
| WO2015027609A1 (en) | 2015-03-05 |
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