CN111129155A - 一种低栅漏电容碳化硅di-mosfet制备方法 - Google Patents
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Abstract
本发明提出了一种低栅漏电容SiC DI‑MOSFET的制备方法来解决栅漏电容大导致的器件工作频率低，动态损耗大的问题，具体步骤包括：选取形成有碳化硅（SiC）外延层的半导体衬底；通过光刻掩膜对其进行区域离子注入，并高温退火激活注入杂质；对未注入掺杂的外延层通过光刻掩膜进行局部Si离子注入；在600℃‑2000℃下热生长氧化层；淀积多晶硅并刻蚀掉不需要的部分形成栅极；淀积介质层将栅极包覆并刻蚀形成源级接触孔；在介质层上方淀积覆盖源区和介质层的源级金属，在衬底下方沉积漏极金属，并退火制备欧姆接触。由于采用上述技术方案，栅氧化层厚度增加，栅漏电容减小、器件的开关速度提升、工作频率提高、器件的开关损耗减小。
Description
技术领域
本发明涉及半导体领域，尤其涉及一种低栅漏电容碳化硅DI-MOSFET制备方法。
背景技术
半导体技术一直是推动电力电子行业发展的决定性力量。功率硅器件(Silicon，Si)的应用已经相当成熟，但随着日益增长的行业需求，硅器件由于其本身物理特性的限制，已经开始不适用于一些高压、高温、高效率及高功率密度的应用场合。碳化硅(SiliconCarbide，SiC)材料因其优越的物理特性，开始受到人们的关注和研究，碳化硅技术得到了迅速发展。碳化硅是宽禁带半导体材料的一种，也是第三代半导材料的重要组成部分，具有高临界击穿电场强度、高饱和电子迁移率、高热导率、耐腐蚀、硬度大等优点。在众多碳化硅半导体器件中，碳化硅DI- MOSFET(Double Implanted Metal Oxide SemiconductorField Effect Transistor)是最具优势特性的开关器件，具有易驱动、开关速度快、低功耗等优点。这种器件主要通过两次离子注入，首先形成n型掺杂区和包围n型掺杂区的p型掺杂区，其次在SiC表面通过热氧化形成栅氧层，并在其上淀积多晶硅形成一个MOS结构，然后淀积介质层将栅极隔离，最后淀积源级金属和漏极金属并退火制备源、漏电极。
然而，在开关电源中，MOS管本身内部结构、开关过程和损耗复杂，大批MOS管由于短时过功率烧毁失效，因为对大的MOS管进行开关操作时，需要对寄生电容充放电，这样会引起驱动损耗，开关损耗，降低开关速度。
发明内容
本发明提出了一种低栅漏电容SiC DI-MOSFET的制备方法，通过增厚栅极与未注入掺杂的外延层之间的氧化层厚度从而降低器件的栅漏电容，从而提高器件工作频率，减小器件的动态损耗。
为实现本发明的目的，本发明提供如下技术方案：
一种低栅漏电容SiC DI-MOSFET制备方法，其具体步骤包括：
步骤S1：选取SiC衬底的上表面同质生长有SiC外延层的外延片；
步骤S2：对SiC外延层上表面局部区域进行p型掺杂，形成p型掺杂区，在p型掺杂区上表面通过离子注入形成n型离子注入区形成n型掺杂区，并高温退火激活注入杂质，P型掺杂区上表面与n型掺杂区的上表面重合，p型掺杂区和n型掺杂区共同构成源区，并且使p型掺杂区包围n型掺杂区；
步骤S3：在SiC外延层上表面未注入掺杂的区域通过光刻掩膜进行局部Si离子注入，使SiC非晶化；
步骤S4：进行热氧化处理，使得非晶化的离子注入区以及p型掺杂区、n型掺杂区和SiC外延层上表面裸露的部分被氧化，从而形成氧化介质层；
步骤S5：在氧化后的介质层表面淀积栅极导电材料并刻蚀掉两侧的小部分，使得形成栅极导电材料在垂直方向上能够覆盖到部分p型掺杂区和n型掺杂区；
步骤S6：沉积或生长一层介质层将所述栅极导电材料完全包覆，刻蚀介质层形成源极接触孔
步骤S7：在SiC外延层上方淀积覆盖源区和所述介质层的源级金属，以及在所述SiC衬底下方沉积漏极金属，并退火制备欧姆接触。
本发明的原理为： MOS管内部寄生电容主要有栅源电容（Cgs）、栅漏电容（Cgd），它们是由MOS结构的绝缘层形成的；漏源电容（Cds），由PN结构成。栅漏电容（Cgd）电容业界称为米勒电容，它不是恒定的，而是随栅极和漏级间电压变化而迅速变化。米勒电容会引发的米勒效应，即在MOS管开通过程中，GS电压上升到某一电压值后GS电压有一段稳定值，过后GS电压又开始上升直至完全导通。因为，在MOS开通前，D极电压大于G极电压，MOS寄生电容Cgd储存的电量需要在其导通时注入G极与其中的电荷中和，MOS完全导通后G极电压大于D极电压。米勒效应会使得MOS管不能很快得进入开关状态，严重增加MOS的开通损耗。由半导体中的计算公式可知：氧化层压降Vox = - Qs/Cox，Cox=εox/tox，εox =εr×εo（Cox为氧化层单位面积电容，εo真空介电常数，εr表示其他材料的介电常数，εox为栅氧化层介电常量，tox为氧化层厚度 ）。因此Cgd和Cox成正比，Cox与tox成反比。
采用本发明的技术方案，对栅极下方未注入掺杂的部分SiC外延层进行Si离子注入，离子注入使SiC非晶化，提高其氧化速度，实现局部厚氧化层的制备，从而降低栅极与漏极之间的电容值，提高器件工作频率，减小器件动态损耗。
附图说明
图1为步骤1的一种结构示意图。
图2为步骤2的一种结构示意图。
图3为步骤3的一种结构示意图。
图4为步骤4的一种结构示意图。
图5为步骤5的一种结构示意图。
图6为步骤6的一种结构示意图。
图7为整个器件的一种结构示意图。
1．源级金属；2．介质层；3．栅极；4．n型掺杂区；5．p型掺杂区；6．SiC外延层：7．SiC衬底；8．漏极金属；9．Si离子注入区。
具体实施方式
下面通过具体的实施例对本发明进行说明，但对本发明不局限于此，下述实施例中所述实验方法，如无特殊说明，均为常规方法；
实施例1
步骤S1：选取4H—SiC外延片，由N+SiC衬底7和N-型外延层6组成，外延层6通过物理气相沉积（PVD）制备而成，厚度为10um；
步骤S2：对SiC外延层6上表面两侧进行p型掺杂，形成p型掺杂区5,在p型掺杂区5上表面通过离子注入形成n型离子注入区形成n型掺杂区4，并在1700℃高温下退火激活注入杂质，p型掺杂区5上表面与n型掺杂区4的上表面重合，p型掺杂区5和n型掺杂区4共同构成源区，并且使p型掺杂区5包围n型掺杂区4，其中p型区的掺杂浓度为1×1013cm-3，n型区的掺杂浓度为1×1016cm-3；
步骤S3：在SiC外延层6上表面未掺杂的区域通过光刻掩膜进行局部Si离子9注入，使SiC非晶化，Si离子注入深度为60nm，浓度为1×1020cm-3；
步骤S4：在1200℃下进行热氧化处理，使得非晶化的离子注入区9以及p型掺杂区5、n型掺杂区4和SiC外延层6上表面裸露的部分被氧化，从而形成氧化介质层2，氧化气体为干氧、湿氧、NO、N2O、NO2和氧气中的一种或者多种，或者为含氮气体的混合气体，含氮气体优选NO、N2O、NO2；
步骤S5：在氧化后的介质层2表面淀积栅极导电材料3并刻蚀掉两侧的小部分，使得形成栅极导电材料3在垂直方向上能够覆盖到部分p型掺杂区5和n型掺杂区4；
步骤S6：刻蚀形成源级接触孔，并生成一层介质层2将所述栅极导电材料3完全包覆，形成介质层2方法为物理气相沉积（PVD）、化学气相沉积（CVD）或是由一层多晶硅或者非晶硅或者单晶硅经过热氧化形成；
步骤S7：在SiC外延层6上方淀积覆盖源区和所述介质层2的源级金属1，以及在所述SiC衬底7下方沉积漏极金属8，并在1000℃高温下退火制备欧姆接触。
实施例2
步骤S1：选取4H—SiC外延片，由N+SiC衬底7和N-型外延层6组成，外延层6通过物理气相沉积（PVD）制备而成，厚度为20um；
步骤S2：对SiC外延层6上表面两侧进行p型掺杂，形成p型掺杂区5,在p型掺杂区5上表面通过离子注入形成n型离子注入区形成n型掺杂区4，并在1700℃高温下退火激活注入杂质，p型掺杂区5上表面与n型掺杂区4的上表面重合，p型掺杂区5和n型掺杂区4共同构成源区，并且使p型掺杂区5包围n型掺杂区4，其中p型区的掺杂浓度为1×1015cm-3，n型区的掺杂浓度为1×1017cm-3；
步骤S3：在SiC外延层6上表面未掺杂的区域通过光刻掩膜进行局部Si离子9注入，使SiC非晶化，Si离子注入深度为300nm，浓度为1×1021cm-3；
步骤S4：在950℃下进行热氧化处理，使得非晶化的离子注入区9以及p型掺杂区5、n型掺杂区4和SiC外延层6上表面裸露的部分被氧化，从而形成氧化介质层2，氧化气体为干氧、湿氧、NO、N2O、NO2和氧气中的一种或者多种，或者为含氮气体的混合气体，含氮气体优选NO、N2O、NO2；
步骤S5：在氧化后的介质层2表面淀积栅极导电材料3并刻蚀掉两侧的小部分，使得形成栅极导电材料3在垂直方向上能够覆盖到部分p型掺杂区5和n型掺杂区4；
步骤S6：刻蚀形成源级接触孔，并生成一层介质层2将所述栅极导电材料3完全包覆，形成介质层2方法为物理气相沉积（PVD）、化学气相沉积（CVD）或是由一层多晶硅或者非晶硅或者单晶硅经过热氧化形成；
步骤S7：在SiC外延层6上方淀积覆盖源区和所述介质层2的源级金属1，以及在所述SiC衬底7下方沉积漏极金属8，并在1000℃高温下退火制备欧姆接触。
对栅极下方未注入掺杂的部分SiC外延层进行Si离子注入，离子注入使SiC非晶化，可提高其氧化速度，实现局部厚氧化层的制备，从而降低了栅极与漏极之间的电容值，提高了器件工作频率，减小了器件动态损耗。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步的详细说明，所应理解的是，以上所述仅为本发明的具体实施方法而已，并不用于限制本发明，凡是在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
Claims (8)
1.一种低栅漏电容SiC DI-MOSFET制备方法，其具体步骤包括：
步骤S1：选取SiC衬底（7）的上表面同质生长有SiC外延层（6）的外延片；
步骤S2：对SiC外延层（6）上表面局部区域进行p型掺杂，形成p型掺杂区（5），在p型掺杂区（5）上表面通过离子注入形成n型离子注入区形成n型掺杂区（4），并高温退火激活注入杂质，p型掺杂区（5）上表面与n型掺杂区（4）的上表面重合，p型掺杂区（5）和n型掺杂区（4）共同构成源区，并且使p型掺杂区（5）包围n型掺杂区（4）；
步骤S3：在SiC外延层（6）上表面未注入掺杂的区域通过光刻掩膜进行局部Si离子（9）注入，使SiC非晶化；
步骤S4：进行热氧化处理，使得非晶化的离子注入区（9）以及p型掺杂区（5）、n型掺杂区（4）和SiC外延层（6）上表面裸露的部分被氧化，从而形成氧化介质层（2）；
步骤S5：在氧化后的介质层（2）表面淀积栅极导电材料（3）并刻蚀掉两侧的小部分，使得形成栅极导电材料（3）在垂直方向上能够覆盖到部分p型掺杂区（5）和n型掺杂区（4）；
步骤S6：沉积或生长一层介质层（2）将所述栅极导电材料（3）完全包覆，刻蚀介质层2形成源极接触孔；
步骤S7：在SiC外延层（6）上方淀积覆盖源区和所述介质层（2）的源级金属（1），以及在所述SiC衬底（7）下方沉积漏极金属（8），并退火制备欧姆接触。
2.根据权利要求1所述的低栅漏电容SiC DI-MOSFET制备方法，其特征在于：步骤S2中高温退火激活注入杂质的温度为1200-2000℃。
3.根据权利要求1所述的低栅漏电容SiC DI-MOSFET制备方法，其特征在于：所述栅极导电材料（3）为金属、多晶硅或金属与Si的合金，或者是金属、多晶硅和Si中2种或2种以上的叠层结构。
4.根据权利要求1所述的低栅漏电容SiC DI-MOSFET制备方法，其特征在于：n型掺杂区（4）的掺杂浓度为1x1016cm-3-1x1020cm-3；p型掺杂区（5）的掺杂浓度为1x1013cm-3-1x1019cm-3。
5.根据权利要求1所述的低栅漏电容SiC DI-MOSFET制备方法，其特征在于：SiC外延片由N+SiC衬底和N-型外延层组成，SiC外延层（6）和SiC衬底（7）的晶型为4H或6H，SiC外延层（6）厚度为0um-500um。
6.根据权利要求1所述的低栅漏电容SiC DI-MOSFET制备方法，其特征在于：步骤S3中局部Si离子注入区（9）注入深度为30nm-1000nm，浓度为1x1018cm-3-1x1022cm-3。
7.根据权利要求1所述的低栅漏电容SiC DI-MOSFET制备方法，其特征在于：步骤S4中所述介质层（2）为SiO2氧化层，生成SiO2氧化层热氧化处理的温度为600℃-2000℃，氧化气体为干氧、湿氧、NO、N2O、NO2和氧气中的一种或者多种，或者为含氮的混合气体。
8.根据权利要求1所述的低栅漏电容SiC DI-MOSFET制备方法，其特征在于：步骤S6中所述介质层（2）为SiO2氧化层，形成方法为物理气相沉积（PVD）、化学气相沉积（CVD），或是由一层多晶硅或者非晶硅或者单晶硅经过热氧化形成。
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