CN110828373B - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN110828373B CN110828373B CN201911131109.8A CN201911131109A CN110828373B CN 110828373 B CN110828373 B CN 110828373B CN 201911131109 A CN201911131109 A CN 201911131109A CN 110828373 B CN110828373 B CN 110828373B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
A method of forming a semiconductor structure, comprising: providing a substrate comprising a first area and a second area; forming a dielectric layer on the surface of the substrate, wherein a first through hole is formed in the first area dielectric layer, a second through hole is formed in the second area dielectric layer, and the opening of the first through hole is larger than that of the second through hole; forming a first oxide layer in the first through hole and forming a second oxide layer in the second through hole; etching to remove the first oxide layer at the bottom of the first through hole and the second oxide layer with partial thickness at the bottom of the second through hole, and forming a groove in the substrate below the first through hole; forming a first side wall on the side wall of the first through hole and the side wall of the groove, and forming a second side wall on the side wall of the second through hole; forming a first word line layer in the first through hole and the groove; forming a second word line layer in the second through hole; removing the dielectric layer, the second oxide layer, the second side wall and the second word line layer in the second area; and removing part of the thickness substrate of the second area. The invention is beneficial to completely etching and removing the second side wall and improving the yield of products.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
A silicon single crystal (silicon chip) is composed of many compact, hexagonal cells (cells). The number of the cells is related to the size of the silicon single crystal. For example: a 120 mil square (mil sqt) silicon single crystal contains about 5000 units and a 240 mil square silicon single crystal contains about 25000 units.
Adjacent cells are separated by a peripheral region (periphery) with a cell transition region (cell ring) between the cells and the peripheral region. The cell transition region surrounds the cell and can function as a protection cell.
The existing methods for forming semiconductor structures still need to be improved.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which is beneficial to etching and removing a second side wall, reducing the material residue of the second side wall and improving the yield of products.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first area and a second area; forming a dielectric layer on the surface of the substrate, wherein a first through hole is formed in the dielectric layer of the first region, a second through hole is formed in the dielectric layer of the second region, and the opening of the first through hole is larger than that of the second through hole; in the same process step, forming a first oxide layer on the side wall and the bottom of the first through hole, and forming a second oxide layer on the side wall and the bottom of the second through hole; in the same process step, etching to remove a first oxide layer at the bottom of the first through hole and a second oxide layer with partial thickness at the bottom of the second through hole, etching to remove the substrate with partial thickness below the first through hole, and forming a groove in the substrate; in the same process step, forming a first side wall on the side wall of the first through hole and the side wall of the groove, and forming a second side wall on the side wall of the second through hole; forming a first word line layer in the first through hole and the groove; forming a second word line layer in the second through hole; removing the dielectric layer, the second oxide layer, the second side wall and the second word line layer in the second region; and removing part of the thickness of the substrate of the second region.
Optionally, the ratio of the opening width of the first through hole to the opening width of the second through hole is 1.5-2.
Optionally, the opening width of the first through hole is 0.32 μm, and the opening width of the second through hole is 0.16 μm to 0.19 μm.
Optionally, in the step of forming the first oxide layer and the second oxide layer, a ratio of a thickness of the first oxide layer covering the bottom of the first through hole to a thickness of the second oxide layer covering the bottom of the second through hole is 0.4 to 0.6.
Optionally, the groove is formed by an anisotropic dry etching process.
Optionally, in the process of providing the substrate, the substrate includes: a substrate; a first isolation layer on the substrate; a floating gate layer on the first isolation layer; a first bonding layer on the floating gate layer; a second release layer on the first adhesive layer; a second adhesive layer on the second barrier layer; a control gate layer on the second adhesion layer.
Optionally, in the process of forming the groove, the bottom of the groove is exposed out of the surface of the substrate.
Optionally, the first side wall includes: the first sub-side wall covers the side wall of the first oxide layer, the side wall of the control gate layer, the side wall of the second bonding layer, the side wall of the second isolation layer and the side wall of the first bonding layer; the second sub-side wall covers the side wall of the first sub-side wall; the third sub-side wall covers the side wall of the second sub-side wall; and the fourth sub-side wall covers the side walls of the third sub-side wall, the side walls of the floating gate layer, the side walls of the first isolation layer and the surface of the substrate exposed at the bottom of the groove.
Optionally, the second side wall includes: the fifth sub-side wall covers the side wall of the second oxidation layer; the sixth sub-side wall covers the side wall of the fifth sub-side wall; the seventh sub-side wall covers the side wall of the sixth sub-side wall; and the eighth sub-side wall covers the seventh sub-side wall and the second oxidation layer positioned at the bottom of the second through hole.
Optionally, in the process of removing a portion of the thickness of the substrate in the second region, the control gate layer in the second region is removed.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the process of forming the dielectric layer, the opening of the first through hole is larger than the opening of the second through hole, so that when the first oxide layer and the second oxide layer are formed in the same process step, the thickness of the first oxide layer at the bottom of the first through hole is smaller than that of the first oxide layer at the bottom of the second through hole. Because the thickness of the first oxidation layer at the bottom of the first through hole is smaller than that of the first oxidation layer at the bottom of the second through hole, in the process of forming the groove, when the first oxidation layer at the bottom of the first through hole is completely etched and removed and part of the thickness of the substrate below the first through hole is etched and removed, only part of the thickness of the second oxidation layer at the bottom of the second through hole is etched and removed, and the rest of the second oxidation layer still covers the bottom of the second through hole. Because the rest of the second oxide layer still covers the bottom of the second through hole, in the process of forming the first side wall and the second side wall, the first side wall covers the side wall of the first through hole and the side wall of the groove, and the second side wall covers the side wall of the second through hole. Because the second side wall covers the side wall of the second through hole and the bottom of the second through hole is still covered by the second oxidation layer, the bottom of the second side wall is higher than the top surface of the substrate, the second side wall is etched and removed cleanly in the process of removing the dielectric layer, the second oxidation layer, the second side wall and the second word line layer in the second area, the material residue of the second side wall is reduced, the substrate and the material residue of the second side wall are prevented from being continuously remained due to larger etching selection ratio in the process of removing the substrate with partial thickness in the second area, and the product yield is prevented from being influenced by the material residue of the second side wall.
Drawings
Fig. 1 to 16 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known in the art, the performance of the conventional semiconductor structure is still to be improved.
Now, analysis is performed in combination with a method for forming a semiconductor structure, and the process steps for forming the semiconductor structure mainly include: providing a substrate, wherein the substrate comprises a first area and a second area; forming a dielectric layer on the surface of the substrate, wherein a first through hole is formed in the dielectric layer of the first region, a second through hole is formed in the dielectric layer of the second region, and the opening of the first through hole is the same as the opening of the second through hole; in the same process step, forming a first oxide layer on the side wall and the bottom of the first through hole, and forming a second oxide layer on the side wall and the bottom of the second through hole; in the same process step, etching to remove a first oxide layer at the bottom of the first through hole and a second oxide layer at the bottom of the second through hole, etching to remove a part of the thickness of the substrate below the first through hole and the second through hole, forming a first groove in the substrate below the first through hole, and forming a second groove in the substrate below the second through hole; in the same process step, forming a first side wall on the side wall of the first through hole and the side wall of the first groove, and forming a second side wall on the side wall of the second through hole and the side wall of the second groove; forming a first word line layer in the first through hole and the first groove; forming a second word line layer in the second through hole and the second groove; removing the dielectric layer, the second oxide layer, the second side wall and the second word line layer which are higher than the top of the substrate in the second area; and removing part of the thickness of the substrate of the second region.
And after the dielectric layer, the second oxide layer, the second side wall and the second word line layer which are higher than the top of the substrate are removed from the second region, the second side wall is remained to cover the side wall of the second groove. In the process of removing the substrate with partial thickness of the second region, the second sidewall is difficult to be removed by etching and remains because the substrate has a larger etching selectivity ratio to the second sidewall material. The second side wall is easy to peel off in the subsequent process, and the product yield is affected.
The inventor researches the forming method of the semiconductor structure, and after creative work, the inventor notices that in the process of forming the dielectric layer, the opening of the first through hole is larger than the opening of the second through hole, which is beneficial to reducing the residue of the second side wall material and improving the yield of products.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 16 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 1 to 6, a substrate 100 is provided, wherein the substrate 100 includes a first region i and a second region ii.
In this embodiment, the substrate 100 further includes a third region (not shown), and the second region ii is located between the first region i and the third region.
In this embodiment, the substrate 100 includes: a substrate 110; a first isolation layer 120 on the substrate 110; a floating gate layer 130 on the first isolation layer 120; a first adhesion layer 140 on the floating gate layer 130; a second release layer 150 on the first adhesive layer 140; a second adhesive layer 160 on the second barrier layer 150; a control gate layer 170 on the second adhesive layer 160.
The process steps for forming the substrate 100 are described in detail below with reference to fig. 1-6.
Referring to fig. 1, a substrate 110 is provided, the substrate 110 including a first region i and a second region ii.
In this embodiment, the substrate 110 further includes a third region, and the second region ii is located between the first region i and the third region.
In this embodiment, the first area i is a cell (cell), the second area ii is a cell ring, and the third area is a peripheral area (periphery).
In this embodiment, a gap (not shown) is formed between the second region ii and the first region i. In other embodiments, the second region ii may be adjacent to the first region i.
The substrate 110 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 110 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In this embodiment, the substrate 110 is a silicon substrate.
Referring to fig. 2, a first isolation layer 120 is formed on the surface of the substrate 110.
In this embodiment, the material of the first isolation layer 120 is silicon oxide. In other embodiments, the material of the first isolation layer 120 is silicon nitride or silicon oxynitride.
A floating gate layer is subsequently formed on the first isolation layer 120, and the first isolation layer 120 can serve to isolate the floating gate layer from the substrate 110.
Referring to fig. 3, a floating gate layer 130 is formed on the surface of the first isolation layer 120.
In this embodiment, the material of the floating gate layer 130 is polysilicon.
The floating gate layer 130 is used for storing electrons to support an erasing process of a Flash Memory (Flash Memory).
Referring to fig. 4, a first adhesive layer 140 is formed on the surface of the floating gate layer 130.
In this embodiment, before forming the first adhesive layer 140, the method further includes: etching the floating gate layer 130, the first isolation layer 120 and the substrate 110 in the second region ii, and forming a first isolation groove in the second region ii; forming a first isolation structure 181 filling the first isolation trench; and carrying out planarization treatment on the first isolation structure 181, wherein the top of the first isolation structure 181 is flush with the top of the floating gate layer 130 of the first area I.
In this embodiment, before forming the first adhesive layer 140, the method further includes: etching the floating gate layer, the first isolation layer and the substrate 110 in the third region to form a second isolation groove in the third region; forming a second isolation structure (not shown) filling the second isolation trench.
In this embodiment, the first adhesive layer 140 covers the surface of the floating gate layer 130 in the first region i, the surface of the floating gate layer 130 in the second region ii, the surface of the first isolation structure 181, the surface of the second isolation structure, and the surface of the floating gate layer in the third region.
In this embodiment, the material of the first bonding layer 140 is silicon oxide.
A second spacer layer is subsequently formed on the first bonding layer 140, and the first bonding layer 140 can improve adhesion between the second spacer layer and the surface of the floating gate layer 130.
Referring to fig. 5, a second isolation layer 150 is formed on the surface of the first adhesive layer 140.
A control gate layer is subsequently formed on the second isolation layer 150, and the second isolation layer 150 can further isolate the control gate layer from the floating gate layer 130, so as to prevent the control gate layer from being electrically connected to the floating gate layer 130.
In this embodiment, the second isolation layer 150 is made of silicon nitride. In other embodiments, the material of the second isolation layer 150 is silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Referring to fig. 6, a control gate layer 170 is formed on the second isolation layer 150.
In this embodiment, before forming the control gate layer 170, the method further includes: a second adhesive layer 160 is formed on the surface of the second isolation layer 150, and the control gate layer 170 covers the surface of the second adhesive layer 160.
The second adhesive layer 160 can improve the bonding performance between the control gate layer 170 and the surface of the second isolation layer 150, and reduce the risk of voids between the control gate layer 170 and the second isolation layer 150.
In this embodiment, the material of the second bonding layer 160 is silicon oxide.
In this embodiment, the material of the control gate layer 170 is polysilicon.
Referring to fig. 7, a dielectric layer 200 is formed on a surface of a substrate 100, the dielectric layer 200 in the first area i has a first through hole 210 therein, the dielectric layer 200 in the second area ii has a second through hole 220 therein, and an opening of the first through hole 210 is larger than an opening of the second through hole 220.
In this embodiment, the dielectric layer 200 covers the surface of the control gate layer 170.
The step of forming the dielectric layer 200 includes: forming a dielectric film (not shown) covering the entire surface of the control gate layer 170; forming a first patterned photoresist layer (not shown in the figure) on the surface of the dielectric film, wherein the first patterned photoresist layer covers all the dielectric surface of the third region, part of the dielectric surface of the first region I and part of the dielectric surface of the second region II; etching the dielectric film in the first region I to form the first through hole 210; and etching the dielectric film of the second area II to form the second through hole 220, wherein the opening of the second through hole 220 is smaller than the opening of the first through hole 210. And the residual dielectric film is used as the dielectric layer 200.
The opening of the first through hole 210 is larger than the opening of the second through hole 220, and in the same process step, a first oxide layer is formed on the sidewall and the bottom of the first through hole 210, and a second oxide layer is formed on the sidewall and the bottom of the second through hole 220, wherein the thickness of the first oxide layer at the bottom of the first through hole 210 is smaller than the thickness of the first oxide layer at the bottom of the second through hole 220.
In this embodiment, the opening of the first through hole 210 is circular, and the opening of the second through hole 220 is also circular.
In the embodiment, the ratio of the opening width L1 of the first via 210 to the opening width L2 of the second via 220 is 1.5-2. If the ratio of the opening width L1 of the first via 210 to the opening width L2 of the second via 220 is too small, the difference between the thicknesses of the first oxide layer formed at the bottom of the first via 210 and the second oxide layer formed at the bottom of the second via 220 is small, and in the subsequent etching process, the second oxide layer is easily etched and removed together with the first oxide layer, so that the control gate layer 170 in the second region ii is etched. If the ratio of the opening width L1 of the first via 210 to the opening width L2 of the second via 220 is too large, the aspect ratio of the second via 220 is too large, which results in difficulty in forming the second oxide layer 320 on the sidewall and bottom of the second via 220.
In this embodiment, the opening width L1 of the first via 210 is 0.32 μm, and the opening width L2 of the second via 220 is 0.16 μm to 0.19 μm.
Referring to fig. 8, in the same process step, a first oxide layer 310 is formed on the sidewall and bottom of the first via 210, and a second oxide layer 320 is formed on the sidewall and bottom of the second via 220.
The first oxide layer 310 and the second oxide layer 320 are made of the same material. In this embodiment, the first oxide layer 310 and the second oxide layer 320 are made of silicon oxide. In other embodiments, the first oxide layer 310 and the second oxide layer 320 are both made of germanium oxide.
In this embodiment, the first oxide layer 310 and the second oxide layer 320 are formed by a chemical vapor deposition process. In other embodiments, the first oxide layer 310 and the second oxide layer 320 are formed by an atomic layer deposition process.
The first oxide layer 310 and the second oxide layer 320 are formed in the same process step, which helps to save process time; on the other hand, the first via hole 210 and the second via hole 220 are in the same process environment, and the amount of the first oxide layer 310 deposited at the bottom of the first via hole 210 and the amount of the second oxide layer 320 deposited at the bottom of the second via hole 220 are substantially the same in the same time; since the opening width L1 (refer to fig. 7) of the first via 210 is greater than the opening width L2 (refer to fig. 7) of the second via 220, the thickness d1 of the first oxide layer 310 at the bottom of the first via 210 is less than the thickness d2 of the first oxide layer 310 at the bottom of the second via 220 after the deposition process is completed.
In this embodiment, the ratio of the thickness d1 of the first oxide layer 310 covering the bottom of the first via 210 to the thickness d2 of the second oxide layer 320 covering the bottom of the second via 220 is 0.4-0.6. If the ratio of the thickness d1 of the first oxide layer 310 covering the bottom of the first via 210 to the thickness d2 of the second oxide layer 320 covering the bottom of the second via 220 is too large, the second oxide layer 320 at the bottom of the second via 220 is easily etched completely in the subsequent process step of etching the first oxide layer 310 to form a groove in the first area i, thereby etching the substrate 100 in the second area ii. If the ratio of the thickness d1 of the first oxide layer 310 covering the bottom of the first via 210 to the thickness d2 of the second oxide layer 320 covering the bottom of the second via 220 is too small, the thickness of the second oxide layer 320 at the bottom of the second via 220 is too large, and accordingly, the depth of the second via 220 is too large, which results in too large thickness of the dielectric layer 200, and unnecessarily increases the process time for removing the second oxide layer 320 and the dielectric layer 200 in the second region ii.
Referring to fig. 9 and 10, in the same process step, the first oxide layer 310 at the bottom of the first through hole 210 and the second oxide layer 320 at the bottom of the second through hole 220 are etched and removed, and the substrate 100 at the bottom of the first through hole 210 is etched and removed, so that a groove 400 is formed in the substrate 100. In the same process step, a first sidewall 510 is formed on the sidewall of the first via 210 and the sidewall of the groove 400, and a second sidewall 520 is formed on the sidewall of the second via 220.
In this embodiment, while the process of forming the recess 400 is performed, in the second region ii, since the thickness of the second oxide layer 320 deposited at the bottom of the second via 220 is greater than the thickness of the first oxide layer 310 deposited at the bottom of the first via 210, only a portion of the thickness of the second oxide layer 320 located at the bottom of the second via 220 is etched away, and the remaining second oxide layer 320 still covers the sidewall and the bottom of the second via 220.
In this embodiment, the groove 400 is formed by an anisotropic dry etching process.
In this embodiment, the recess 400 and a portion of the second oxide layer 320 are formed in the same process step, which helps to shorten the process time.
Since the second oxide layer 320 of the second region ii still covers the bottom of the second via 220, the bottom of the second sidewall 520 is formed higher than the top surface of the substrate 100.
Fig. 11 is an enlarged view of the second sidewall spacer 520 shown in fig. 10.
In this embodiment, the bottom of the groove 400 exposes the surface of the substrate 110 under the first through hole 210.
Referring to fig. 11, in the present embodiment, the first sidewall 510 includes: the first sub-sidewall 511, where the first sub-sidewall 511 covers the sidewalls of the first oxide layer 310, the sidewalls of the control gate layer 170, the sidewalls of the second adhesive layer 160, the sidewalls of the second isolation layer 150, and the sidewalls of the first adhesive layer 140; the second sub-side walls 512, the second sub-side walls 512 cover the side walls of the first sub-side walls 511; the third sub-side walls 513 are arranged, and the third sub-side walls 513 cover the side walls of the second sub-side walls 512; and a fourth sub-sidewall 514, wherein the fourth sub-sidewall 514 covers the sidewalls of the third sub-sidewall 513, the sidewalls of the floating gate layer 130, the sidewalls of the first isolation layer 120, and the surface of the substrate 110 exposed at the bottom of the groove 400.
In this embodiment, the sidewall of the recess 400 exposes the sidewall surface of the control gate layer 170, the sidewall surface of the second adhesion layer 160, the sidewall surface of the second isolation layer 150, the sidewall surface of the first adhesion layer 140, the sidewall surface of the floating gate layer 130, and the sidewall surface of the first isolation layer 120. A first word line layer is formed in the first via 210 and the groove 400, and the first sub-sidewall 511, the second sub-sidewall 512, and the third sub-sidewall 513 are used to isolate the control gate layer 170 from the first word line layer. The fourth sub-sidewall spacers 514 are used for isolating the floating gate layer 130 from the first word line layer 610.
In this embodiment, the process steps for forming the groove 400 and the first sidewall 510 include: as shown in fig. 9, the first oxide layer 310 at the bottom of the first via 210 is etched to expose the surface of the control gate layer 170; further etching the exposed control gate layer 170, the second adhesion layer 160, the second isolation layer 150, and the first adhesion layer 140 until the surface of the floating gate layer 130 is exposed, so as to form an initial groove 410; as shown in fig. 10 and 11, the first sub-sidewall 511, the second sub-sidewall 512, and the third sub-sidewall 513 are formed on the sidewalls of the first through-hole 210 and the sidewalls of the initial groove 410; etching the bottom of the initial groove 410 until the surface of the substrate 110 is exposed, so as to form the groove 400; and forming the fourth sub-sidewall 514 on the sidewalls of the third sub-sidewall 513, the sidewalls of the floating gate layer 130, the sidewalls of the first isolation layer 120, and the surface of the substrate 110 exposed at the bottom of the groove 400.
Fig. 12 is an enlarged view of the second sidewall spacer 520 shown in fig. 10.
Referring to fig. 12, in the present embodiment, the second side wall 520 includes: a fifth sub-sidewall 521, wherein the fifth sub-sidewall 521 covers the sidewall of the second oxide layer 320; a sixth sub-sidewall 522, wherein the sixth sub-sidewall 522 covers the sidewall of the fifth sub-sidewall 521; a seventh sub-sidewall 523, wherein the seventh sub-sidewall 523 covers the sidewall of the sixth sub-sidewall 522; and the eighth sub-side wall 524, wherein the eighth sub-side wall 524 covers the seventh sub-side wall 523 and the second oxide layer 320 located at the bottom of the second through hole 220.
In this embodiment, the first sub-sidewall 511 and the fifth sub-sidewall 521 are formed in the same process step.
The first sub-sidewall 511 and the fifth sub-sidewall 521 are made of the same material. In this embodiment, the first sub-sidewall 511 and the fifth sub-sidewall 521 are made of silicon oxide. In other embodiments, the first sub-sidewall 511 and the fifth sub-sidewall 521 are made of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the second sub-sidewall 512 and the sixth sub-sidewall 522 are formed in the same process step.
The second sub-side wall 512 and the sixth sub-side wall 522 are made of the same material. In this embodiment, the second sub-sidewall 512 and the sixth sub-sidewall 522 are made of silicon nitride. In other embodiments, the second sub-sidewall 512 and the sixth sub-sidewall 522 are made of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the third sub-sidewall 513 and the seventh sub-sidewall 523 are formed in the same process step.
The third sub-side wall 513 and the seventh sub-side wall 523 are made of the same material. In this embodiment, the third sub-sidewall 513 and the seventh sub-sidewall 523 are made of silicon oxide. In other embodiments, the third sub-sidewall 513 and the seventh sub-sidewall 523 are made of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the fourth sub-sidewall 514 and the eighth sub-sidewall 524 are formed in the same process step.
The fourth sub-sidewall 514 and the eighth sub-sidewall 524 are made of the same material. In this embodiment, the fourth sub-sidewall 514 and the eighth sub-sidewall 524 are made of silicon oxide. In other embodiments, the fourth sub-sidewall 514 and the eighth sub-sidewall 524 are made of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Referring to fig. 13, a first word line layer 610 is formed within the first via hole 210 and the groove 400; a second word line layer 620 is formed within the second via 220.
In this embodiment, the first word line layer 610 and the second word line layer 620 are formed in the same process step.
In this embodiment, the process steps of forming the first word line layer 610 and the second word line layer 620 include: forming a word line film (not shown) filling the first via hole 210, the groove 400 and the second via hole 220, wherein the word line film covers the top surface of the dielectric layer 200; and performing planarization treatment on the word line film, removing the word line film higher than the top of the dielectric layer 200, wherein the word line film remaining in the first through hole 210 and the groove 400 is used as the first word line layer 610, and the word line film remaining in the second through hole 220 is used as the second word line layer 620.
The first word line layer 610 and the second word line layer 620 are the same material. In this embodiment, the first word line layer 610 and the second word line layer 620 are made of polysilicon.
In this embodiment, the first word line layer 610 covers the surface of the fourth sub-sidewall 514. The second word line layer 620 covers the surfaces of the eighth sub-side walls 524.
In this embodiment, after forming the first word line layer 610 and the second word line layer 620, the method further includes: in the same process step, a first spacer layer 710 is formed overlying the top of the first word line layer 610 and a second spacer layer 720 is formed overlying the top of the second word line layer 620.
After the first liner layer 710 and the second liner layer 720 are formed, the method further includes: the insulating layer 730 is formed overlying the top of the first liner layer 710, the top of the second liner layer 720, and the top of the dielectric layer 200.
In this embodiment, the first liner layer 710 helps to improve the adhesion between the insulating layer 730 and the first word line layer 610; the second liner layer 720 is advantageous for enhancing the adhesion of the insulating layer 730 to the second word line layer 620.
In this embodiment, the first liner layer 710 and the second liner layer 720 are made of silicon oxide.
In this embodiment, the insulating layer 730 is made of silicon nitride. In other embodiments, the material of the insulating layer 730 is silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Referring to fig. 14, a second photoresist layer 800 is formed on top of the insulating layer 730 in the first region i.
In this embodiment, the second photoresist layer 800 exposes the top surfaces of the insulating layers 730 in the second region ii and the third region.
Referring to fig. 15, the dielectric layer 200, the second oxide layer 320, the second sidewall spacers 520, and the second word line layer 620 in the second region ii are removed.
In this embodiment, the dielectric layer 200, the second oxide layer 320, the second sidewall 520, and the second word line layer 620 in the second region ii are removed by a dry etching process. In other embodiments, a wet etch process may also be employed.
In this embodiment, in the step of the dry etching process, the method further includes: removing the insulating layer 730 and the second liner layer 720 in the second region ii, and removing the insulating layer 730 and the dielectric layer 200 in the third region.
In this embodiment, the dry etching process is performed until the surface of the substrate 100 of the second region ii is exposed, specifically, until the top surface of the control gate layer 170 of the second region ii is exposed.
In this embodiment, since the bottom of the second sidewall 520 is higher than the top surface of the substrate 100, and since the etching rates of the second sidewall 520, the dielectric layer 200, the second oxide layer 320, and the second word line layer 620 are close to each other in the dry etching process, the second sidewall 520 can be completely etched and removed, the material residue of the second sidewall 520 is reduced, and the material residue of the substrate 100 and the second sidewall 520 is prevented from being continuously retained due to a large etching selectivity ratio in the subsequent process of removing the substrate 100 with a partial thickness of the second region ii.
Referring to fig. 16, a portion of the thickness of the substrate 100 in the second region ii is removed.
In this embodiment, the control gate layer 170 in the second region ii is removed by etching. Since the second side walls 520 are completely removed in the previous process step, in the process of removing the control gate layer 170 in the second region ii, the material residue of the second side walls 520 can be prevented from being continuously retained due to the larger etching selection ratio with the control gate layer 170, and the influence of the material residue of the second side walls 520 (refer to fig. 14) on the product yield can be avoided.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area;
forming a dielectric layer on the surface of the substrate, wherein a first through hole is formed in the dielectric layer of the first region, a second through hole is formed in the dielectric layer of the second region, and the opening of the first through hole is larger than that of the second through hole;
in the same process step, forming a first oxide layer on the side wall and the bottom of the first through hole, and forming a second oxide layer on the side wall and the bottom of the second through hole;
in the same process step, etching and removing a first oxide layer at the bottom of the first through hole and a second oxide layer with partial thickness at the bottom of the second through hole, etching and removing a substrate with partial thickness below the first through hole, and forming a groove in the substrate;
in the same process step, forming a first side wall on the side wall of the first through hole and the side wall of the groove, and forming a second side wall on the side wall of the second through hole;
forming a first word line layer in the first through hole and the groove;
forming a second word line layer in the second through hole;
removing the dielectric layer, the second oxide layer, the second side wall and the second word line layer in the second region;
and removing part of the thickness substrate of the second area.
2. The method according to claim 1, wherein a ratio of an opening width of the first via to an opening width of the second via is 1.5 to 2.
3. The forming method according to claim 2, wherein a width of the first via opening is 0.32 μm, and an opening width of the second via opening is 0.16 μm to 0.19 μm.
4. The method of claim 1, wherein in the step of forming the first oxide layer and the second oxide layer, a ratio of a thickness of the first oxide layer covering the bottom of the first via to a thickness of the second oxide layer covering the bottom of the second via is 0.4 to 0.6.
5. The method of forming of claim 1, wherein the recess is formed using an anisotropic dry etch process.
6. The method of forming of claim 1, wherein in the process of providing the substrate, the substrate comprises:
a substrate;
a first isolation layer on the substrate;
a floating gate layer on the first isolation layer;
a first bonding layer on the floating gate layer;
a second release layer on the first adhesive layer;
a second adhesive layer on the second barrier layer;
a control gate layer on the second adhesion layer.
7. The method of claim 6, wherein the bottom of the recess exposes the surface of the substrate during the forming of the recess.
8. The method of forming as claimed in claim 7, wherein the first sidewall includes:
the first sub-side wall covers the side wall of the first oxide layer, the side wall of the control gate layer, the side wall of the second bonding layer, the side wall of the second isolation layer and the side wall of the first bonding layer;
the second sub-side wall covers the side wall of the first sub-side wall;
the third sub-side wall covers the side wall of the second sub-side wall;
and the fourth sub-side wall covers the side walls of the third sub-side wall, the side walls of the floating gate layer, the side walls of the first isolation layer and the surface of the substrate exposed at the bottom of the groove.
9. The method of forming as claimed in claim 8, wherein the second sidewall includes:
the fifth sub-side wall covers the side wall of the second oxidation layer;
the sixth sub-side wall covers the side wall of the fifth sub-side wall;
the seventh sub-side wall covers the side wall of the sixth sub-side wall;
and the eighth sub-side wall covers the seventh sub-side wall and the second oxidation layer positioned at the bottom of the second through hole.
10. The method according to claim 6, wherein the step of removing the portion of the thickness of the substrate in the second region is a step of removing the control gate layer in the second region.
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| CN102361022A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for manufacturing embedded flash memory |
| CN103021953A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Formation method of semiconductor integrated device |
| CN104465727A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of separation gate flash memory structure |
| CN106783866A (en) * | 2017-01-05 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | The manufacture method of flush memory device |
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| CN102361022A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for manufacturing embedded flash memory |
| CN103021953A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Formation method of semiconductor integrated device |
| CN104465727A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of separation gate flash memory structure |
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