CN104465727A - Forming method of separation gate flash memory structure - Google Patents
Forming method of separation gate flash memory structure Download PDFInfo
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- CN104465727A CN104465727A CN201310446046.1A CN201310446046A CN104465727A CN 104465727 A CN104465727 A CN 104465727A CN 201310446046 A CN201310446046 A CN 201310446046A CN 104465727 A CN104465727 A CN 104465727A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000000926 separation method Methods 0.000 title abstract 4
- 230000005641 tunneling Effects 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 20
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention provides a forming method of a separation gate flash memory structure. The size of an erasing gate, the size of a control gate and the size of a floating gate are controlled according to the first opening size of a hard mask layer and the thickness of a dielectric side wall; a compression side wall is formed at a time; ion injection of a flash memory source end does not need a light resistance mask, and the light resistance mask is not needed when the hard mask layer is removed and the control gate and the floating gate are formed through etching, a tunneling dielectric layer is formed at a time, overlapping of other oxide layers is not needed, the reliability of the separation gate flash memory structure can be improved, the number of times of using light resistance is reduced, the production cost is reduced, and meanwhile the reliability of the separation gate flash memory structure is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of formation method of separate gate flash memory structure.
Background technology
Separate gate flash memory structure comprises erase gate (Erase gate), control gate (Control gate) and floating boom (Floating gate).Wherein, control gate is positioned on floating boom, and is kept apart by dielectric layer; Erase gate is at two pairs between control gate and floating boom, and be public erase gate, two wordline lay respectively at two pairs of control gates and floating boom both sides, and all have dielectric layer to keep apart, and between erase gate and floating boom, oxide layer is tunneling medium layer.And floating boom can stretch into a part to erase gate, form eclipsed form structure of frame covered (Wrap round), this unique texture can improve ability and the efficiency of erasing.Separate gate flash memory structure due to said structure has that high reliability, well manufacturing process are compatible, lower starting resistor and prevented the advantages such as erasing, and therefore, above-mentioned separate gate flash memory structure is by as embedded flash memory extensive use.
Please refer to Fig. 1 to Fig. 7, Fig. 1 to Fig. 7 is the cross-sectional view formed in prior art in separate gate flash memory configuration process; In prior art, the formation method of separate gate flash memory structure comprises step:
There is provided Semiconductor substrate, described Semiconductor substrate is provided with device region (Cell) 11, higher-pressure region (Highvoltage) 12 and low-pressure area (Low voltage) 13;
Form the first photoresist layer 61 of resilient coating 20, floating gate layer 31, flash media layer 40, control grid layer 32, hard mask layer 50 and patterning on the semiconductor substrate successively, as shown in Figure 1;
With the first photoresist layer 61 of described patterning for mask, etch described hard mask layer 50, control grid layer 32 and flash media layer 40 successively, hard mask layer 50, control grid layer 32 and flash media layer 40 described in the reserve part of device region 11, erase gate groove 41 is formed between the described hard mask layer 50 of part retained, control grid layer 32 and flash media layer 40, be convenient to follow-up formation erase gate, as shown in Figure 2;
Then side wall 71 and protection side wall 72 is formed successively in the both sides of the hard mask layer 50 retained, control grid layer 32 and flash media layer 40, for the protection of the hard mask layer 50 retained, control grid layer 32 and flash media layer 40, as shown in Figure 2;
Then in erase gate groove 41, the second photoresist layer 62 is formed, for the protection of the side wall 71 in erase gate groove 41 and protection side wall 72;
Then etching remove retain hard mask layer 50, control grid layer 32 and the not protected side of flash media layer 40 protection side wall 72, as shown in Figure 3;
Then, remove described second photoresist layer 62, and with described side wall 71 and protection side wall 72 for mask, etch described floating gate layer 31, retain a part of floating gate layer 31 under the flash media layer 40 retained, expose described resilient coating 20, owing to still there is described protection side wall 72 in erase gate groove 41, therefore by described protection side wall 72 as mask, the floating gate layer 31 retained can extend a part in erase gate groove 41, due to the hard mask layer 50 retained, the protection side wall 72 of control grid layer 32 and the not protected side of flash media layer 40 is removed, therefore this side can not be extended by floating gate layer 31 with a grain of salt, as shown in Figure 4,
Then, form compensation side wall 72 in the both sides of the side of the side wall 71 exposed and floating gate layer 31, deposit high pressure grid oxic horizon (scheming not shown) in higher-pressure region 12, as shown in Figure 4 simultaneously;
Then, the surface of the hard mask layer 50 retained on the surface of described buffering 20 and part forms the 3rd photoresist layer 63, then to carrying out the process of flash memory source ion implantation in described erase gate groove 41, as shown in Figure 5;
Then, with described 3rd photoresist layer 63 for mask, wet etching removes the compensation side wall 72 in described erase gate groove 41, as shown in Figure 5;
Then, tunneling medium layer 73 is formed in described erase gate groove 41, as shown in Figure 6, then described 3rd photoresist layer 63 is removed, and deposit low pressure gate oxide (scheming not shown) in described low-pressure area 13, therefore, final tunneling medium layer is superposed by tunneling medium layer 73 and low pressure gate oxide to be formed;
Then, in described erase gate groove 41, form erase gate 33, form wordline 81 in the both sides of described protection side wall 72, form high-voltage grid 82 and low pressure grid 83 respectively in described higher-pressure region 12 and low-pressure area 13, as described in Figure 7.
But, form the method relative complex of separate gate flash memory structure in prior art, be unfavorable for reducing production cost and enhancing productivity.
Summary of the invention
The object of the present invention is to provide a kind of formation method of separate gate flash memory structure, this method reduce photoresistance access times, while reducing production cost, be conducive to the reliability improving flash memory.
In order to realize the problems referred to above, a kind of formation method of separate gate flash memory structure, comprises step:
Semiconductor substrate is provided, is formed with resilient coating, floating gate layer, flash media layer, control grid layer, hard mask layer and photoresist layer on the semiconductor substrate successively;
With described photoresist layer for mask, etch described hard mask layer, form the first opening, described first opening exposes described control grid layer;
A dielectric layer side wall is formed at the inwall of described first opening;
With described dielectric layer side wall for mask, etch described control grid layer and flash media layer successively, form the second opening, the size of described second opening is less than the size of described first opening, and exposes described floating gate layer;
A protection side wall and a compensation side wall is formed successively at the inwall of described first opening and the second opening;
With described protection side wall and compensate side wall for mask, etch described floating gate layer, expose resilient coating;
Tunneling medium layer is formed at the sidewall of described floating gate layer;
Erase gate is formed in described first opening and the second opening;
Remove described hard mask layer;
Non-mask etching removes the part control grid layer of first medium layer both sides, flash media layer and floating gate layer, formation control grid, flash media and floating boom;
Flash memory side wall is formed respectively at the sidewall of described control gate, flash media and floating boom;
Form wordline at the sidewall of described flash memory side wall, form separate gate flash memory structure.
Further, the size of erase gate, control gate and floating boom is decided by the thickness of the size and medium side wall that control described first opening.
Further, after etching floating gate layer, before forming tunneling medium layer, adopt and carry out the process of flash memory source without photolithographic mask ion implantation mode in described second opening.
Further, after ion processing is carried out to described second opening, before forming tunneling medium layer, adopt wet etching to remove described compensation side wall and portion of buffer layer, expose part semiconductor substrate.
Further, while formation wears dielectric layer then, again resilient coating is formed at the semiconductor substrate surface exposed.
Further, after formation tunneling medium layer, deposition forms erasing gate layer.
Further, adopt cmp to grind described erasing gate layer, form erase gate, grinding stops at described hard mask layer.
Further, after the described erase gate of formation, before removing described hard mask layer, ion implantation process is carried out to the surface of described erase gate.
Further, after ion implantation process is carried out on the surface of described erase gate, thermal oxidation method is used to form an oxide layer on the surface of described erase gate.
Further, the thickness of described oxide layer is greater than 20 nanometers.
Further, wet etching is adopted to remove hard mask layer.
Further, described flash memory side wall is silicon nitride-silicon oxide silicon structure.
Further, described Semiconductor substrate comprises logic area, while etching forms wordline, forms grid at logic region.
Further, the material of described floating gate layer, control grid layer, erase gate and wordline is polysilicon.
Further, described flash media layer is oxide-nitride-oxide structure.
Further, the material of described tunneling medium layer, resilient coating and compensation side wall is silica.
Further, the material of described hard mask layer is silicon nitride.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: the size being defined erase gate, control gate and floating boom by the first opening size of hard mask layer and the thickness of medium side wall; Compensate side wall once to be formed; Flash memory source ion implantation is also without the need to photolithographic mask, at removal hard mask layer and all without the need to photolithographic mask when etching formation control grid and floating boom, and tunneling medium layer is once formed, superpose without other oxide layer, separate gate flash memory reliability of structure can be improved, the method is decreasing photoresistance access times, while reducing production cost, is beneficial to and improves separate gate flash memory reliability of structure.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is the cross-sectional view formed in prior art in separate gate flash memory configuration process;
Fig. 8 is the flow chart of the formation method of separate gate flash memory structure in one embodiment of the invention;
Fig. 9 to Figure 17 is the cross-sectional view formed in one embodiment of the invention in separate gate flash memory configuration process.
Embodiment
Be described in more detail below in conjunction with the formation method of schematic diagram to separate gate flash memory structure of the present invention, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 8, propose a kind of formation method of separate gate flash memory structure in the present embodiment, comprise step:
S100: provide Semiconductor substrate, is formed with resilient coating 200, floating gate layer 310, flash media layer 400, control grid layer 320, hard mask layer 500 and photoresist layer 600, as shown in Figure 9 on the semiconductor substrate successively;
In the present embodiment, described Semiconductor substrate comprises device region 110, higher-pressure region 120 and low-pressure area 130, described higher-pressure region 120 and low-pressure area 130 belong to logic area, follow-up separate gate flash memory structure is formed on described device region 110, wherein, described higher-pressure region 120 and low-pressure area 130 are all formed with silica (scheming not shown) and fleet plough groove isolation structure 140; The material of described resilient coating 200 is silica, for isolating described floating gate layer 310 and described Semiconductor substrate; The material of described floating gate layer 310 and control grid layer 320 is polysilicon; Described flash media layer 400 is oxide-nitride-oxide structure, for isolating described floating gate layer 310 and control grid layer 320; The material of described hard mask layer 500 is silicon nitride, as shown in Figure 9.
S200: with described photoresist layer 600 for mask, etches described hard mask layer 500, forms the first opening, and described first opening exposes described control grid layer 320;
After described first opening of formation, remove described photoresist layer 600.
S300: form a medium side wall 710 at the inwall of described first opening, as shown in Figure 10;
The material of described medium side wall 710 is silica, is convenient to subsequent etching as mask layer, also can avoid using photoresistance.
S400: with described medium side wall 710 for mask, etch described control grid layer 320 and flash media layer 400 successively, form the second opening 410, described second opening 410 exposes described floating gate layer 310, the size of described second opening 410 is less than described first opening, as shown in Figure 10;
S500: form protection side wall 720 and a compensation side wall 730 successively at the inwall of described first opening and the second opening 410, as shown in figure 11;
Wherein, the material of described protection side wall 720 is silicon nitride, and the material of described compensation side wall 730 is silica.
S600: with described protection side wall 720 with compensate side wall 730 for mask, etching floating gate layer 310, exposes resilient coating 200, as shown in figure 12;
Wherein, because described compensation side wall 730 can as etching mask, also just can avoid using photoresistance, meanwhile, described compensation side wall 730 can ensure that described floating gate layer 310 can some extend in described second opening 410.
At etching floating gate layer 310, after exposing resilient coating 200, photolithographic mask ion implantation mode is adopted to carry out the process of flash memory source to the resilient coating 200 in described second opening 410 and Semiconductor substrate, after to use ion processing in described second opening 410, re-use wet etching and remove described compensation side wall 730 and portion of buffer layer 200, expose part semiconductor substrate, as shown in figure 12.
S700: form tunneling medium layer 740 at the sidewall of described floating gate layer 310, as shown in figure 13;
In the present embodiment, because described compensation side wall 730 is subject to certain damage with the resilient coating 200 exposed in etching, in order to ensure its performance, therefore described compensation side wall 730 and portion of buffer layer 200 can first be removed, tunneling medium layer 740 is formed again at the sidewall of the surface of the protection side wall 720 exposed and described floating gate layer 310, in the Semiconductor substrate exposed, again form resilient coating 200 simultaneously, as shown in figure 13, the material of described tunneling medium layer 740 is silica, because the tunneling medium layer 740 in the present embodiment superposes without other oxide layer, one step is formed, its thickness and quality can be controlled effectively, the Performance And Reliability of separate gate flash memory structure can be improved to a great extent.
S800: form erase gate 331 in described first opening and the second opening 410, as shown in figure 15;
The material of described erase gate 331 is polysilicon, the step forming described erase gate 331 comprises: first described first opening and the second opening 410 in and the surface deposition of described hard mask layer 500 formed and wipe gate layer 330, as shown in figure 14, cmp is adopted to remove the erasing gate layer 330 being formed in described hard mask layer 500 excess surface again, form erase gate 331, wherein, described hard mask layer 500 is as grinding stop layer.
After the described erase gate 331 of formation, before removing described hard mask layer 500, ion implantation process is carried out to the surface of described erase gate 331, then, thermal oxidation method is used to form an oxide layer 750 on the surface of described erase gate 331, as shown in figure 15, wherein, the thickness of described oxide layer 750 is greater than 20 nanometers.
S900: remove described hard mask layer 500,
Wet etching is adopted to remove hard mask layer 500.
S1000: non-mask etching removes the part control grid layer 320 of described first medium layer 710 both sides, flash media layer 400 and floating gate layer 310, formation control grid 321, flash media 401 and floating boom 311, as shown in figure 16;
When etching, protecting because described erase gate 331 is surface-oxidised layer 750, therefore etching
S1100: form flash memory side wall at the sidewall of described control gate 321, flash media 401 and floating boom 311 respectively, as shown in figure 16;
Described flash memory side wall is silicon nitride 760-silica 770 structure, and in order to isolate the wordline of follow-up formation, and silicon nitride 760-silica 770 structure can improve the anti-interference of separate gate flash memory structure.
S1200: form wordline 810 at the sidewall of described flash memory side wall, form separate gate flash memory structure, as shown in figure 17.
Wherein, in the present embodiment, described hard mask layer 500, and after etching the control grid layer 320 of described medium side wall 710 both sides, flash media layer 400 and floating gate layer 310 successively, resilient coating 200 can be exposed, and expose described higher-pressure region 120 and low-pressure area 130 completely, and form high pressure grid oxic horizon and low voltage gate oxide layer in described higher-pressure region 120 and low-pressure area 130 place, because this step is this area conventional techniques means, the present invention does not make change, therefore repeats no more in the present embodiment.But, while formation wordline 810, also form high pressure grid 820 and low voltage gate 830 respectively in higher-pressure region 120 and low-pressure area 130 place.
To sum up, in the formation method of the separate gate flash memory structure provided in the embodiment of the present invention, the size of erase gate, control gate and floating boom is defined by the first opening size of hard mask layer and the thickness of medium side wall; Compensate side wall once to be formed; Flash memory source ion implantation is also without the need to photolithographic mask, at removal hard mask layer and all without the need to photolithographic mask when etching formation control grid and floating boom, and tunneling medium layer is once formed, superpose without other oxide layer, separate gate flash memory reliability of structure can be improved, the method is decreasing photoresistance access times, while reducing production cost, is beneficial to and improves separate gate flash memory reliability of structure.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (17)
1. a formation method for separate gate flash memory structure, comprises step:
Semiconductor substrate is provided, is formed with resilient coating, floating gate layer, flash media layer, control grid layer, hard mask layer and photoresist layer on the semiconductor substrate successively;
With described photoresist layer for mask, etch described hard mask layer, form the first opening, described first opening exposes described control grid layer;
A dielectric layer side wall is formed at the inwall of described first opening;
With described dielectric layer side wall for mask, etch described control grid layer and flash media layer successively, form the second opening, the size of described second opening is less than the size of described first opening, and exposes described floating gate layer;
A protection side wall and a compensation side wall is formed successively at the inwall of described first opening and the second opening;
With described protection side wall and compensate side wall for mask, etch described floating gate layer, expose resilient coating;
Tunneling medium layer is formed at the sidewall of described floating gate layer;
Erase gate is formed in described first opening and the second opening;
Remove described hard mask layer;
Non-mask etching removes the part control grid layer of first medium layer both sides, flash media layer and floating gate layer, formation control grid, flash media and floating boom;
Flash memory side wall is formed respectively at the sidewall of described control gate, flash media and floating boom;
Form wordline at the sidewall of described flash memory side wall, form separate gate flash memory structure.
2. the formation method of separate gate flash memory structure as claimed in claim 1, be is characterized in that, decided the size of erase gate, control gate and floating boom by the thickness of the size and medium side wall that control described first opening.
3. the formation method of separate gate flash memory structure as claimed in claim 1, is characterized in that, after etching floating gate layer, before forming tunneling medium layer, adopts and carries out the process of flash memory source without photolithographic mask ion implantation mode in described second opening.
4. the formation method of separate gate flash memory structure as claimed in claim 3, it is characterized in that, after ion processing is carried out to described second opening, before forming tunneling medium layer, adopt wet etching to remove described compensation side wall and portion of buffer layer, expose part semiconductor substrate.
5. the formation method of separate gate flash memory structure as claimed in claim 4, is characterized in that, while formation tunneling medium layer, again forms resilient coating at the semiconductor substrate surface exposed.
6. the formation method of separate gate flash memory structure as claimed in claim 1, is characterized in that, after formation tunneling medium layer, deposition forms erasing gate layer.
7. the formation method of separate gate flash memory structure as claimed in claim 6, is characterized in that, adopt cmp to grind described erasing gate layer, form erase gate, grinding stops at described hard mask layer.
8. the formation method of separate gate flash memory structure as claimed in claim 1, is characterized in that, after the described erase gate of formation, before removing described hard mask layer, carries out ion implantation process to the surface of described erase gate.
9. the formation method of separate gate flash memory structure as claimed in claim 8, is characterized in that, after ion implantation process is carried out on the surface of described erase gate, uses thermal oxidation method to form an oxide layer on the surface of described erase gate.
10. the formation method of separate gate flash memory structure as claimed in claim 9, it is characterized in that, the thickness of described oxide layer is greater than 20 nanometers.
The formation method of 11. separate gate flash memory structures as claimed in claim 1, is characterized in that, adopts wet etching to remove hard mask layer.
The formation method of 12. separate gate flash memory structures as claimed in claim 1, it is characterized in that, described flash memory side wall is silicon nitride-silicon oxide silicon structure.
The formation method of 13. separate gate flash memory structures as claimed in claim 1, it is characterized in that, described Semiconductor substrate comprises logic area, while etching forms wordline, forms grid at logic region.
The formation method of 14. separate gate flash memory structures as claimed in claim 1, it is characterized in that, the material of described floating gate layer, control grid layer, erase gate and wordline is polysilicon.
The formation method of 15. separate gate flash memory structures as claimed in claim 1, it is characterized in that, described flash media layer is oxide-nitride-oxide structure.
The formation method of 16. separate gate flash memory structures as claimed in claim 1, it is characterized in that, the material of described tunneling medium layer, resilient coating and compensation side wall is silica.
The formation method of 17. separate gate flash memory structures as claimed in claim 1, is characterized in that, the material of described hard mask layer is silicon nitride.
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| CN107230678A (en) * | 2017-08-09 | 2017-10-03 | 上海华虹宏力半导体制造有限公司 | The manufacture method of flash memory |
| CN107230678B (en) * | 2017-08-09 | 2020-04-10 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory |
| CN109273449A (en) * | 2018-09-11 | 2019-01-25 | 上海华虹宏力半导体制造有限公司 | Memory and its manufacturing method |
| CN109273449B (en) * | 2018-09-11 | 2020-09-25 | 上海华虹宏力半导体制造有限公司 | Memory and manufacturing method thereof |
| CN110634746A (en) * | 2019-09-25 | 2019-12-31 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing embedded flash memory |
| CN110828373A (en) * | 2019-11-19 | 2020-02-21 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor structure |
| CN110828373B (en) * | 2019-11-19 | 2022-02-22 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor structure |
| CN113675205A (en) * | 2021-08-20 | 2021-11-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN113675205B (en) * | 2021-08-20 | 2024-04-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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