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CN110739305B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110739305B
CN110739305B CN201910574024.0A CN201910574024A CN110739305B CN 110739305 B CN110739305 B CN 110739305B CN 201910574024 A CN201910574024 A CN 201910574024A CN 110739305 B CN110739305 B CN 110739305B
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China
Prior art keywords
transistor
emitter
bipolar
bipolar transistors
semiconductor device
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CN201910574024.0A
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CN110739305A (zh
Inventor
大部功
小屋茂树
梅本康成
筒井孝幸
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

本发明提供在安装到外部基板时能够抑制电连接不良的产生的半导体装置。半导体装置具有：半导体基板；多个第一双极晶体管，设置于半导体基板的第一主面侧，在与第一主面垂直的方向上，在发射层与发射极之间具有第一高度；至少一个以上的第二双极晶体管，设置于半导体基板的第一主面侧，在与第一主面垂直的方向上，在发射层与发射极之间具有比第一高度高的第二高度；以及第一凸块，遍布多个第一双极晶体管和至少一个以上的第二双极晶体管而配置。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
在专利文献1记载有在同一半导体基板上设置有第一双极晶体管和第二双极晶体管的半导体装置。构成第一双极晶体管的多个单位晶体管不具有发射极镇流电阻层。构成第二双极晶体管的多个单位晶体管具有发射极镇流电阻层。
专利文献1：日本特开2017－220584号公报
在专利文献1的半导体装置中，半导体基板的背面与第一双极晶体管的发射极布线(发射极的上表面)之间的高度不同于半导体基板的背面与第二双极晶体管的发射极布线(发射极的上表面)之间的高度。因此，在第一双极晶体管以及第二双极晶体管分别设置凸块，并经由凸块将半导体装置安装到模块基板的情况下，存在产生连接不良的可能性。
发明内容
本发明的目的在于提供在安装到外部基板时能够抑制电连接不良的产生的半导体装置。
本发明的一方面的半导体装置具有：半导体基板；多个第一双极晶体管，设置于上述半导体基板的第一主面侧，在与上述第一主面垂直的方向上，在发射层与发射极之间具有第一高度；至少一个以上的第二双极晶体管，设置于上述半导体基板的上述第一主面侧，在与上述第一主面垂直的方向上，在发射层与发射极之间具有比上述第一高度高的第二高度；以及第一凸块，遍布多个上述第一双极晶体管和至少一个以上的上述第二双极晶体管而配置。
发明效果
根据本发明的半导体装置，在安装到外部基板时，能够抑制电连接不良的产生。
附图说明
图1是第一实施方式所涉及的半导体装置的俯视图。
图2是沿着图1的II－II’线的剖视图。
图3是第一双极晶体管的剖视图。
图4是第二双极晶体管的剖视图。
图5是第一晶体管组的等效电路图。
图6是第二晶体管组的等效电路图。
图7是用于对第一实施方式所涉及的半导体装置的制造方法进行说明的说明图。
图8是第一实施方式的第一变形例所涉及的半导体装置的俯视图。
图9是沿着图8的IX－IX’线的剖视图。
图10是第一实施方式的第一变形例所涉及的第一晶体管组的等效电路图。
图11是第一实施方式的第二变形例所涉及的半导体装置的俯视图。
图12是第一实施方式的第三变形例所涉及的半导体装置的俯视图。
图13是第一实施方式的第四变形例所涉及的半导体装置的俯视图。
图14是第一实施方式的第五变形例所涉及的半导体装置的俯视图。
图15是第一实施方式的第六变形例所涉及的半导体装置的俯视图。
图16是第二实施方式所涉及的半导体装置的俯视图。
图17是沿着图16的XVII－XVII’线的剖视图。
图18是第二实施方式所涉及的半导体装置的等效电路图。
图19是第三实施方式所涉及的半导体装置的剖视图。
图20是第四实施方式所涉及的功放模块的剖视图。
图21是表示第四实施方式所涉及的功放模块的构成的框图。
具体实施方式
以下，基于附图对本发明的半导体装置的实施方式详细地进行说明。此外，本发明并不被该实施方式限定。各实施方式是例示，当然能够进行不同的实施方式中示出的构成的部分置换或者组合。在第二实施方式以后，省略与第一实施方式共用的事项的描述，仅对不同点进行说明。特别是，相同的构成所得到的相同的作用效果并不在每个实施方式依次言及。
(第一实施方式)
图1是第一实施方式的半导体装置的俯视图。图2是沿着图1的II－II’线的剖视图。图3是第一双极晶体管的剖视图。图4是第二双极晶体管的剖视图。图5是第一晶体管组的等效电路图。图6是第二晶体管组的等效电路图。此外，在图1中，省略表示各双极晶体管的详细构成，示意性地表示各双极晶体管的配置关系。
如图1所示，半导体装置100具有半导体基板1、第一晶体管组Qa、第二晶体管组Qb、第一凸块61以及第二凸块62。
在以下的说明中，将与半导体基板1的第一主面S1平行的面内的一方向作为X方向。另外，将在与第一主面S1平行的面内与X方向正交的方向作为Y方向。另外，将与X方向以及Y方向的各个正交的方向作为Z方向。此外，并不局限于此，Y方向也可以相对于X方向以90°以外的角度交叉。Z方向也可以相对于X方向以及Y方向以90°以外的角度交叉。
如图1所示，半导体基板1在从Z方向观察时的俯视中具有大致矩形形状。如图2所示，半导体基板1具有第一主面S1、和与第一主面S1对置的第二主面S2。半导体基板1的长边方向沿着X方向设置，短边方向沿着Y方向设置，与第一主面S1垂直的方向是Z方向。半导体基板1例如由半绝缘性的砷化镓(GaAs)构成。
如图1以及图2所示，第一晶体管组Qa以及第二晶体管组Qb设置于半导体基板1的第一主面S1侧。第一晶体管组Qa和第二晶体管组Qb在X方向上具有间隔地相邻配置。第一晶体管组Qa具有多个第一双极晶体管20和多个第二双极晶体管30。第二晶体管组Qb具有多个第三双极晶体管40。即，多个第一双极晶体管20、多个第二双极晶体管30以及多个第三双极晶体管40设置于半导体基板1的第一主面S1侧。
第一双极晶体管20、第二双极晶体管30以及第三双极晶体管40分别是异质结型的双极晶体管(HBT：Heterojunction Bipolar Transistor)。此外，在图1中，为了与第一双极晶体管20区别，对第二双极晶体管30以及第三双极晶体管40标注斜线来表示。
第一双极晶体管20、第二双极晶体管30以及第三双极晶体管40也分别被称为单位晶体管。第一双极晶体管20电并联连接而构成第一晶体管组Qa。第二双极晶体管30的集电极以及基极的至少一方与第一双极晶体管20非连接，不作为晶体管发挥作用。另外，多个第三双极晶体管40电并联连接而构成第二晶体管组Qb。此外，上述的单位晶体管被定义为构成第一晶体管组Qa、或者第二晶体管组Qb的最小的晶体管。
在本实施方式中，作为一个例子，第一晶体管组Qa具有6个第一双极晶体管20和3个第二双极晶体管30。在第一晶体管组Qa中，3个第二双极晶体管30在X方向的两端部以及中央部分别分离配置。多个第一双极晶体管20在X方向上配置于相邻的第二双极晶体管30之间。但是，并不局限于此，第一双极晶体管20以及第二双极晶体管30的数目以及配置也可以适当地变更。例如，第二双极晶体管30也可以是一个。
在本实施方式中，第二晶体管组Qb具有6个第三双极晶体管40。在第二晶体管组Qb中，多个第三双极晶体管40在X方向上并排配置。但是，并不局限于此，第三双极晶体管40的数目以及配置也可以适当地变更。
第一凸块61遍布多个第一双极晶体管20和多个第二双极晶体管30而配置。第二凸块62遍布多个第三双极晶体管40而配置。
如图2所示，在第一晶体管组Qa与第二晶体管组Qb之间，在半导体基板1以及子集电层2设置有隔离区域50。隔离区域50是通过离子注入而半导体基板1以及子集电层2的一部分被绝缘化的区域。通过隔离区域50，第一晶体管组Qa和第二晶体管组Qb被电隔离。
第一双极晶体管20是不具有发射极镇流电阻88的晶体管。第二双极晶体管30以及第三双极晶体管40是具有发射极镇流电阻88的晶体管。
具体而言，如图3所示，第一双极晶体管20包括子集电层2、集电层3、基层4、发射层5、第一接触层6、各种电极以及布线。子集电层2、集电层3、基层4、发射层5、第一接触层6按该顺序层叠在半导体基板1上。
子集电层2设置于半导体基板1的第一主面S1上。集电层3设置于子集电层2上。子集电层2与集电层3一起作为第一双极晶体管20的集电极发挥作用。子集电层2以及集电层3是例如将GaAs作为主要成分的n型半导体。子集电层2能够为Si掺杂浓度约5×1018cm－3，膜厚约600nm。集电层3能够为Si掺杂浓度约1×1016cm－3，膜厚约1000nm。
基层4设置于集电层3上。基层4是例如将GaAs作为主要成分的p型半导体。基层4能够为C掺杂浓度约5×1019cm－3，膜厚约96nm。
发射层5设置于基层4上。发射层5是例如将InGaP作为主要成分的n型半导体。发射层5能够为InP摩尔比约0.48，Si掺杂浓度约4×1017cm－3，膜厚约35nm。
第一接触层6设置于发射层5上。第一接触层6是例如将GaAs作为主要成分的n型半导体。第一接触层6能够为Si掺杂浓度约5×1018cm－3，膜厚约50nm。
2个集电极15设置于子集电层2上，在X方向上夹着集电层3设置。集电极15是AuGe(膜厚约60nm)/Ni(膜厚约10nm)/Au(膜厚约200nm)。此外，“/”表示层叠结构。例如，AuGe/Ni/Au表示在AuGe上层叠有Ni，在Ni上层叠有Au的结构。
在本实施方式中，集电极15被相邻的第一双极晶体管20共享。换句话说，如图2所示，在相邻的第一双极晶体管20之间设置有一个集电极15。一个集电极15与相邻的第一双极晶体管20的各个电连接。由此，与在每个第一双极晶体管20设置2个集电极15的情况相比，能够减少第一晶体管组Qa的电极以及布线的数目。
如图3所示，2个基极16设置于基层4上。在俯视时，在2个基极16之间设置有第一接触层6。基极16例如是Pt(膜厚约20nm)/Ti(膜厚约50nm)/Pt(膜厚约50nm)/Au(膜厚约200nm)。
发射极17设置于第一接触层6上。发射极17例如是Mo(膜厚约10nm)/Ti(膜厚约5nm)/Pt(膜厚约30nm)/Au(膜厚约200nm)。
保护膜57覆盖子集电层2、集电层3、基层4、发射层5、第一接触层6以及各种电极而设置。集电极连接布线51a以及发射极连接布线52a设置于保护膜57上。集电极连接布线51a经由设置于保护膜57的贯通孔与集电极15连接。发射极连接布线52a经由设置于保护膜57的贯通孔与发射极17连接。
层间绝缘膜58设置于覆盖集电极连接布线51a以及发射极连接布线52a的保护膜57上。第一发射极布线53a设置于层间绝缘膜58上。第一发射极布线53a经由设置于层间绝缘膜58的贯通孔与发射极连接布线52a连接。由此，第一发射极布线53a经由发射极连接布线52a与发射极17电连接。
保护膜57以及层间绝缘膜58例如是SiN。集电极连接布线51a、发射极连接布线52a以及第一发射极布线53a例如是Au。
第一凸块61隔着下部金属层56a设置于第一发射极布线53a上。第一凸块61是Cu柱凸块，通过电场电镀法形成。第一凸块61也可以由Au等其他的金属材料构成。下部金属层56a例如是Ti/Cu，是形成第一凸块61时的电镀种子电极。
图4表示第二双极晶体管30的层构成。此外，第三双极晶体管40的层构成与第二双极晶体管30相同，与第二双极晶体管30的层构成有关的说明也能够应用于第三双极晶体管40。
如图4所示，第二双极晶体管30与第一双极晶体管20相同地，在半导体基板1的第一主面S1上设置有子集电层2、集电层3、基层4、发射层5、第一接触层6、集电极15、基极16以及集电极连接布线51a。在第一接触层6与发射极17之间按顺序层叠有沟道阻挡层7、隔离层8、发射极镇流电阻88、第二接触层12、第三接触层13以及第四接触层14。
沟道阻挡层7设置于第一接触层6上。沟道阻挡层7是例如将InGaP作为主要成分的n型半导体。沟道阻挡层7能够为InP摩尔比约0.48，Si掺杂浓度约5×1018cm－3，膜厚约3nm。
隔离层8设置于沟道阻挡层7上。隔离层8是例如将GaAs作为主要成分的n型半导体。隔离层8能够为Si掺杂浓度约3×1017cm－3，膜厚约100nm。
发射极镇流电阻88具有第一发射极镇流电阻层9、第二发射极镇流电阻层10以及第三发射极镇流电阻层11。第一发射极镇流电阻层9、第二发射极镇流电阻层10以及第三发射极镇流电阻层11按该顺序层叠在隔离层8上。第一发射极镇流电阻层9、第二发射极镇流电阻层10以及第三发射极镇流电阻层11分别是将AlGaAs作为主要成分的n型半导体。
第一发射极镇流电阻层9能够为Si掺杂浓度约1×1017cm－3，膜厚约50nm。第一发射极镇流电阻层9的AlAs摩尔比随着接近第二发射极镇流电阻层10而变大。具体而言，在第一发射极镇流电阻层9与隔离层8相接的界面中，AlAs摩尔比是0，在第一发射极镇流电阻层9与第二发射极镇流电阻层10相接的界面中，AlAs摩尔比约为0.33。第一发射极镇流电阻层9的AlAs摩尔比被形成为线性变化。
第二发射极镇流电阻层10能够为AlAs摩尔比约0.33，Si掺杂浓度约1×1017cm－3，膜厚约200nm。
第三发射极镇流电阻层11能够为Si掺杂浓度约1×1017cm－3，膜厚约50nm。第三发射极镇流电阻层11的AlAs摩尔比随着接近第二接触层12而变小。具体而言，在第三发射极镇流电阻层11与第二发射极镇流电阻层10相接的界面中，AlAs摩尔比约是0.33，在第三发射极镇流电阻层11与第二接触层12相接的界面中，AlAs摩尔比为0。第三发射极镇流电阻层11的AlAs摩尔比被形成为线性变化。发射极镇流电阻88具有比第一接触层6高的电阻率。此外，发射极镇流电阻88并不局限于由3层构成的情况，例如也可以由第二发射极镇流电阻层10的1层构成。
第二接触层12、第三接触层13以及第四接触层14按该顺序层叠在第三发射极镇流电阻层11上。第二接触层12是例如将GaAs作为主要成分的n型半导体。第二接触层12能够为Si掺杂浓度约5×1018cm－3，膜厚约50nm。
第三接触层13是例如将InGaAs作为主要成分的n型半导体。第三接触层13能够为Si掺杂浓度约5×1018cm－3，膜厚约50nm。第三接触层13的InAs摩尔比随着接近第四接触层14而变大。具体而言，在第三接触层13与第二接触层12相接的界面中，InAs摩尔比是0，在第三接触层13与第四接触层14相接的界面中，InAs摩尔比约为0.5。第三接触层13的InAs摩尔比被形成为线性变化。
第四接触层14是例如将InGaAs作为主要成分的n型半导体。第四接触层14能够为InAs摩尔比约0.5，Si掺杂浓度约1×1019cm－3，膜厚约50nm。
发射极17设置于第四接触层14上。保护膜57被设置为覆盖从子集电层2到第四接触层14的各层和集电极15、基极16以及发射极17。
在第二双极晶体管30中，也与第一双极晶体管20相同地，第一发射极布线53a设置于层间绝缘膜58上。第一发射极布线53a经由设置于层间绝缘膜58的贯通孔与发射极连接布线52a连接。由此，第一发射极布线53a经由发射极连接布线52a与第二双极晶体管30的发射极17电连接。
如图3所示，将第一双极晶体管20的、发射层5的上表面与发射极17的下表面之间的Z方向上的距离作为第一高度HEa。如图4所示，将第二双极晶体管30的、发射层5的上表面与发射极17的下表面之间的Z方向上的距离作为第二高度HEb。第二高度HEb比第一高度HEa高。另外，第三双极晶体管40也具有与第二双极晶体管30相同的第二高度HEb。
如图2所示，在第一晶体管组Qa中，具有第一高度HEa的多个第一双极晶体管20和具有第二高度HEb的多个第二双极晶体管30在X方向上排列。第一发射极布线53a遍布多个第一双极晶体管20以及多个第二双极晶体管30而设置，并与各个发射极17电连接。
第一凸块61在第一发射极布线53a的上侧遍布多个第一双极晶体管20以及多个第二双极晶体管30而设置。第一凸块61沿着第一发射极布线53a设置，形成有与多个第一双极晶体管20的高度与多个第二双极晶体管30的高度的差异对应的凹凸。
这里，将Z方向上的、第二主面S2与第一凸块61的最上面的距离作为第一最大高度Ha。在本实施方式中，设置有至少覆盖第一晶体管组Qa的侧面的钝化膜59，第一凸块61也设置于与钝化膜59的一部分重叠的区域。在图2中，第一凸块61中与钝化膜59的一部分重叠的部分的上表面与第二主面S2之间为第一最大高度Haと。但是，在钝化膜59未设置于比第一发射极布线53a靠上侧的情况下，第一凸块61中与第二双极晶体管30重叠的部分的上表面与第二主面S2之间为第一最大高度Ha。
在第二晶体管组Qb中，具有第二高度HEb的多个第三双极晶体管40沿X方向排列。第二发射极布线53b遍布多个第三双极晶体管40而设置，经由发射极连接布线52b与第三双极晶体管40的发射极17电连接。
第二凸块62隔着下部金属层56b设置于第二发射极布线53b的上侧，遍布多个第三双极晶体管40而设置。第二凸块62沿着第二发射极布线53b设置。第二凸块62是使用了与第一凸块61相同的金属材料的Cu柱凸块，通过电场电镀方法形成。第二凸块62也可以由Au等其他的金属材料构成。
这里，将Z方向上的、第二主面S2与第二凸块62的最上面的距离作为第二最大高度Hb。在本实施方式中，设置有至少覆盖第二晶体管组Qb的侧面的钝化膜59，第二凸块62也设置于与钝化膜59的一部分重叠的区域。在图2中，第二凸块62中与钝化膜59的一部分重叠的部分的上表面与第二主面S2之间为第二最大高度Hb。但是，在钝化膜59未设置于比第二发射极布线53b靠上侧的情况下，第二凸块62中与第三双极晶体管40重叠的部分的上表面与第二主面S2之间为第二最大高度Hb。
在本实施方式中，第一晶体管组Qa具有多个第一双极晶体管20以及多个第二双极晶体管30，所以第一晶体管组Qa的第一最大高度Ha和第二晶体管组Qb的第二最大高度Hb相等。因此，在使第一凸块61以及第二凸块62与外部基板对置，而安装了半导体装置100的情况下，第一凸块61的至少具有第一最大高度Ha的部分被电连接。即，第一凸块61的至少与第二双极晶体管30重叠的部分与外部基板电连接。而且，具有第一高度HEa的第一双极晶体管20经由第一凸块61与外部基板电连接。由此，与仅由具有第一高度HEa的多个第一双极晶体管20构成了第一晶体管组Qa的情况相比，半导体装置100能够在安装到外部基板时抑制电连接不良的产生。
如图5所示，在第一晶体管组Qa中，第一双极晶体管20的各基极(基极16)经由电容86与共用的第一基极布线54a连接。第一基极布线54a与基极高频输入端子81a连接。电容86是用于截止直流分量的电容元件。另外，第一双极晶体管20的各基极(基极16)经由基极镇流电阻87与共用的第一基极偏置布线55a连接。第一基极偏置布线55a与基极偏置端子82a连接。第二双极晶体管30的各基极与第一基极布线54a以及第一基极偏置布线55a非连接。
第一双极晶体管20的各发射极(发射极17)以及第二双极晶体管30的各发射极(发射极17)与共用的第一发射极布线53a连接，被接地。
第一双极晶体管20的各集电极(集电极15)与共用的第一集电极布线51c连接。第一集电极布线51c与集电极高频输出端子83a以及集电极偏置端子84a连接。第二双极晶体管30的各集电极(集电极15)与第一集电极布线51c非连接。
通过这样的构成，多个第一双极晶体管20放大从基极高频输入端子81a输入的高频信号，并将放大后的信号输出到集电极高频输出端子83a。另外，第二双极晶体管30与基极高频输入端子81a以及集电极高频输出端子83a非连接，不作为晶体管动作。此外，第二双极晶体管30的基极以及集电极的至少一方与第一基极布线54a以及第一集电极布线51c非连接即可。因此，第二双极晶体管30不动作，所以也不发热。因为不发热，所以第二双极晶体管30被作为空间使用，因此能够期待使热偏差分散的效果。热偏差是指中央与两端的晶体管的热的差δ较小。或者，第二双极晶体管30不动作，所以能够期待第一晶体管组Qa的热电阻变小的效果。
如图6所示，在第二晶体管组Qb中，第三双极晶体管40的各基极(基极16)与共用的第二基极布线54b连接。第二基极布线54b经由电容85与基极高频输入端子81b连接。电容85是用于截止直流分量的电容元件。另外，第三双极晶体管40的各基极(基极16)与共用的第二基极偏置布线55b连接。第二基极偏置布线55b与基极偏置端子82b连接。
第三双极晶体管40的各发射极(发射极17)与共用的第二发射极布线53b连接，被接地。第三双极晶体管40的各集电极(集电极15)与共用的第二集电极布线51d连接。第二集电极布线51与集电极高频输出端子83b以及集电极偏置端子84b连接。
通过这样的构成，多个第三双极晶体管40放大从基极高频输入端子81b输入的高频信号，并将放大后的信号输出到集电极高频输出端子83b。
通过上述的构成，在半导体装置100中，在发射层5上不具备发射极镇流电阻88的多个第一双极晶体管20和具备发射极镇流电阻88的第三双极晶体管40安装于同一半导体基板1上。半导体装置100通过切换与集电极电压相应地使其动作的晶体管(第一晶体管组Qa或者第二晶体管组Qb)，能够保证晶体管的放大特性并抑制晶体管的破坏。具体而言，在集电极电压比较低(例如，约6V以下)的情况下使不具备发射极镇流电阻88的第一双极晶体管20动作。另外，在集电极电压比较高(例如，约6V以上)的情况下使具备发射极镇流电阻88的第三双极晶体管40动作。由此，半导体装置100在低输出电力时以及高输出电力时的双方维持较高的电力附加效率，并且可靠性提高。
另外，通过在与第三双极晶体管40相同的半导体基板1上具备发射极镇流电阻88，从而与在半导体装置100的外部设置发射极镇流电阻的情况相比，能够抑制由于多个第三双极晶体管40间的差别引起的部分的热暴走等不良情况的产生。具体而言，在第二晶体管组Qb中，在各第三双极晶体管40流动的电流量不均匀，电流集中于一部分的第三双极晶体管40。这样的情况下，即使在半导体装置100的外部设置发射极镇流电阻，也仅抑制第二晶体管组Qb整体中的电流量，不能有效地抑制该一部分的第三双极晶体管40中的电流量。另一方面，在本实施方式中，在半导体装置100的内部，在各第三双极晶体管40设置有发射极镇流电阻88，所以能够有效地抑制在一部分的第三双极晶体管40中集中产生的大电流。
(半导体装置的制造方法)
图7是用于对第一实施方式所涉及的半导体装置的制造方法进行说明的说明图。如图7所示，在半导体基板1的第一主面S1形成多个第一双极晶体管20、多个第二双极晶体管30以及多个第三双极晶体管40(步骤ST1)。
因为在同一半导体基板1上形成不具有发射极镇流电阻88的第一双极晶体管20和具有发射极镇流电阻88的第二双极晶体管30以及第三双极晶体管40的具体的制造方法记载于专利文献1，所以使专利文献1的记载包含于本实施方式，并省略记载。
钝化膜59遍布第一晶体管组Qa以及第二晶体管组Qb而设置，通过光刻以及蚀刻形成有开口59a。第一发射极布线53a以及第二发射极布线53b在开口59a露出。
接下来，形成下部金属层56以及抗蚀剂71(步骤ST2)。下部金属层56例如通过溅射法形成。下部金属层56覆盖钝化膜59以及开口59a，形成于第一发射极布线53a以及第二发射极布线53b的表面。抗蚀剂71在下部金属层56的整个面形成抗蚀剂层之后，使用光掩模进行曝光、显影。由此，抗蚀剂71设置于与钝化膜59重叠的区域，在与第一发射极布线53a以及第二发射极布线53b重叠的区域设置有开口71a。
接下来，通过电镀法形成第一凸块61以及第二凸块62(步骤ST3)。第一凸块61遍布多个第一双极晶体管20以及多个第二双极晶体管30形成于第一发射极布线53a的上侧。第二凸块62遍布多个第三双极晶体管40形成于第二发射极布线53b的上侧。多个第一凸块61以及第二凸块62通过同一工序形成。因此，第一凸块61的高度与第二凸块62的高度实际相等。此外，第一凸块61的高度是Z方向上的从第一发射极布线53a的表面到第一凸块61的表面的距离。第二凸块62的高度是Z方向上的从第二发射极布线53b的表面到第二凸块62的表面的距离。
在第一凸块61中，设置于第一双极晶体管20的上侧的部分的第一凸块61的高度和设置于第二双极晶体管30的上侧的部分的第一凸块61的高度实质上相等。另外，设置于第二双极晶体管30的上侧的部分的第一凸块61的高度和设置于第三双极晶体管40的上侧的部分的第二凸块62的高度实质上相等。
接下来，通过蚀刻除去抗蚀剂71，通过蚀刻除去未设置有第一凸块61以及第二凸块62的部分的下部金属层56(步骤ST4)。通过以上那样的工序，半导体装置100被形成为第一晶体管组Qa的第一最大高度Ha与第二晶体管组Qb的第二最大高度Hb相等。此外，图7所示的制造方法只不过是一个例子，半导体装置100的制造方法并不局限于此。
(第一实施方式的第一变形例)
图8是第一实施方式的第一变形例所涉及的半导体装置的俯视图。图9是沿着图8的IX－IX’线的剖视图。图10是第一实施方式的第一变形例所涉及的第一晶体管组的等效电路图。在第一实施方式的第一变形例中，对第一晶体管组Qa的排列与上述第一实施方式不同的构成进行说明。
如图8以及图9所示，在半导体装置100A中，第一晶体管组Qa具有6个第一双极晶体管20和2个第二双极晶体管30。在X方向上，6个第一双极晶体管20配置于2个第二双极晶体管30之间。2个第二双极晶体管30中，一方的第二双极晶体管30设置于比第一双极晶体管20远离第二晶体管组Qb的位置。另外，另一方的第二双极晶体管30设置于比第一双极晶体管20接近第二晶体管组Qb的位置。
另外，如图10所示，多个第一双极晶体管20与第一基极布线54a、第一基极偏置布线55a、第一发射极布线53a以及第一集电极布线51c连接，而作为晶体管发挥作用。第二双极晶体管30的基极分别与第一基极布线54a以及第一基极偏置布线55a非连接。第二双极晶体管30的集电极分别与第一集电极布线51c非连接。由此，第二双极晶体管30不作为晶体管发挥作用。
在本变形例的半导体装置100A中，与上述第一实施方式相比，第二双极晶体管30的数目较少，所以能够实现第一晶体管组Qa的小型化。
(第一实施方式的第二变形例)
图11是第一实施方式的第二变形例所涉及的半导体装置的俯视图。在第一实施方式的第二变形例中，与上述第一实施方式不同，对设置有一个第二双极晶体管30的构成进行说明。
如图11所示，第二双极晶体管30在X方向上设置于比多个第一双极晶体管20远离第二晶体管组Qb的位置。换言之，在第二双极晶体管30与第三双极晶体管40之间配置有多个第一双极晶体管20。这样，第一晶体管组Qa并不局限于具有多个第二双极晶体管30的构成，具有至少一个以上的第二双极晶体管30即可。在本变形例的半导体装置100B中，即使是设置有一个第二双极晶体管30的情况，第一最大高度Ha也与第二最大高度Hb相等。
(第一实施方式的第三变形例)
图12是第一实施方式的第三变形例所涉及的半导体装置的俯视图。在第一实施方式的第三变形例中，与上述第一实施方式的第二变形例不同，对一个第二双极晶体管30的位置不同的构成进行说明。
如图12所示，在半导体装置100B中，一个第二双极晶体管30位于第一晶体管组Qa的X方向的中央部。第二双极晶体管30设置于多个第一双极晶体管20与多个第一双极晶体管20之间。在第二双极晶体管30与第二晶体管组Qb之间设置有3个第一双极晶体管20。在比第二双极晶体管30远离第二晶体管组Qb的位置设置有3个第一双极晶体管20。
此外，配置于第二双极晶体管30的一方侧的第一双极晶体管20的数目与配置于另一方侧的第一双极晶体管20的数目也可以不同。优选设置于第二双极晶体管30与第二晶体管组Qb之间的第一双极晶体管20的数目比设置于比第二双极晶体管30远离第二晶体管组Qb的位置的第一双极晶体管20的数目多。由此，第一晶体管组Qa的具有第一最大高度Ha的第二双极晶体管30与第二晶体管组Qb的距离变大，所以能够将半导体装置100C稳定地安装到外部基板。
(第一实施方式的第四变形例)
图13是第一实施方式的第四变形例所涉及的半导体装置的俯视图。在第一实施方式的第四变形例中，与上述第一实施方式不同，对第一晶体管组Qa以及第二晶体管组Qb分别具有多个晶体管列的构成进行说明。
如图13所示，第一晶体管组Qa具有第一晶体管列Qas和第二晶体管列Qat。第一晶体管列Qas和第二晶体管列Qat在Y方向上相邻地配置。第一晶体管列Qas以及第二晶体管列Qat分别具有沿X方向排列的多个第一双极晶体管20以及多个第二双极晶体管30。在第一晶体管列Qas以及第二晶体管列Qat的各个中，3个第一双极晶体管20配置于2个第二双极晶体管30之间。
第一晶体管列Qas以及第二晶体管列Qat的第一双极晶体管20与共用的第一发射极布线53a、第一基极布线54a、第一基极偏置布线55a以及第一集电极布线51c(参照图5)电连接，被构成为一个第一晶体管组Qa。第一晶体管列Qas以及第二晶体管列Qat的第二双极晶体管30均是基极或者集电极的至少一方与第一基极布线54a、第一基极偏置布线55a以及第一集电极布线51c非连接。
第二晶体管组Qb具有第一晶体管列Qbs和第二晶体管列Qbt。第一晶体管列Qbs和第二晶体管列Qbt在Y方向上相邻配置。第二晶体管组Qb的第一晶体管列Qbs与第一晶体管组Qa的第一晶体管列Qas在X方向上相邻配置。第二晶体管组Qb的第二晶体管列Qbt与第一晶体管组Qa的第二晶体管列Qat在X方向上相邻配置。第一晶体管列Qbs以及第二晶体管列Qbt分别具有沿X方向排列的多个第三双极晶体管40。
本变形例的半导体装置100D在具备与第一实施方式数目相同或者比第一实施方式多的数目的晶体管的情况下，也能够缩短第一晶体管组Qa以及第二晶体管组Qb的X方向的长度。其结果，半导体装置100D能够缩短半导体基板1的X方向的长度。
(第一实施方式的第五变形例)
图14是第一实施方式的第五变形例所涉及的半导体装置的俯视图。在第一实施方式的第五变形例中，与上述第一实施方式的第四变形例不同，对第一晶体管组Qa的第一晶体管列Qas以及第二晶体管列Qat分别具有一个第二双极晶体管30的构成进行说明。
如图14所示，在半导体装置100E中，第一晶体管列Qas具有多个第一双极晶体管20和一个第二双极晶体管30。第二双极晶体管30在X方向上设置于比多个第一双极晶体管20远离第二晶体管组Qb的第一晶体管列Qbs的位置。换言之，在X方向上，在一个第二双极晶体管30与第二晶体管组Qb的第一晶体管列Qbs之间配置有多个第一双极晶体管20。第二晶体管列Qat是与第一晶体管列Qas相同的排列。换句话说，在第一晶体管列Qas以及第二晶体管列Qat中，多个第一双极晶体管20在Y方向上相邻配置，并且，多个第二双极晶体管30在Y方向上相邻配置。
(第一实施方式的第六变形例)
图15是第一实施方式的第六变形例所涉及的半导体装置的俯视图。在第一实施方式的第六变形例中，与上述第一实施方式的第五变形例不同，对第一晶体管组Qa的第一晶体管列Qas和第二晶体管列Qat分别具有不同的排列的构成进行说明。
如图15所示，在半导体装置100F中，第一晶体管列Qas是与图14相同的构成。在第二晶体管列Qat中，一个第二双极晶体管30在X方向上，设置于比多个第一双极晶体管20接近第二晶体管组Qb的第一晶体管列Qbs的位置。换言之，在X方向上，一个第二双极晶体管30配置于第二晶体管组Qb的第一晶体管列Qbs与多个第一双极晶体管20之间。第一晶体管列Qas的第二双极晶体管30与第二晶体管列Qat的第一双极晶体管20在Y方向上相邻配置。第二晶体管列Qat的第二双极晶体管30与第一晶体管列Qas的第一双极晶体管20在Y方向上相邻配置。
如以上说明那样，本实施方式的半导体装置100、100A－100F具有半导体基板1、多个第一双极晶体管20、至少一个以上的第二双极晶体管30、以及第一凸块61。第一双极晶体管20设置于半导体基板1的第一主面S1侧，在与第一主面S1垂直的方向上，在发射层5与发射极17之间具有第一高度HEa。第二双极晶体管30设置于半导体基板1的第一主面S1侧，在与第一主面S1垂直的方向上，在发射层5与发射极17之间，具有比第一高度HEa高的第二高度HEb。第一凸块61遍布多个第一双极晶体管20和至少一个以上的第二双极晶体管30而配置。
由此，在使第一凸块61与外部基板对置，安装了半导体装置100的情况下，第一凸块61的至少与第二双极晶体管30重叠的部分与外部基板电连接。由此，具有第一高度HEa的第一双极晶体管20经由第一凸块61与外部基板电连接。因此，半导体装置100在安装到外部基板时能够抑制电连接不良的产生。
另外，本实施方式的半导体装置100、100A－100F具有第三双极晶体管40和第二凸块62。第三双极晶体管40设置于半导体基板1的第一主面S1侧，在与第一主面S1垂直的方向上，在发射层5与发射极17之间具有上述第二高度HEb。第二凸块62遍布多个第三双极晶体管40而配置。
由此，第三双极晶体管40具有与第二双极晶体管30相同的最大高度。与仅由具有第一高度HEa的多个第一双极晶体管20构成第一晶体管组Qa的情况相比，半导体装置100能够在安装到外部基板时抑制电连接不良的产生。
另外，在本实施方式的半导体装置100、100A－100F中，在与半导体基板1的第一主面S1平行的方向(X方向)上，第一双极晶体管20配置于第二双极晶体管30与第三双极晶体管40之间。
由此，第一晶体管组Qa的具有第一最大高度Ha的第二双极晶体管30与第二晶体管组Qb的第三双极晶体管40的距离变大，所以能够将半导体装置100C稳定地安装到外部基板。
另外，在本实施方式的半导体装置100、100A－100F中，第一双极晶体管20、第二双极晶体管30以及第三双极晶体管40是异质结双极晶体管。
由此，第一晶体管组Qa以及第二晶体管组Qb的各晶体管作为放大元件，电力附加效率以及线形性优异。
另外，在本实施方式的半导体装置100、100A－100F中，第一凸块61以及第二凸块62是柱凸块。
由此，通过倒装安装将半导体装置100安装到外部基板，从而能够将外部基板的连接焊盘和柱凸块良好地连接。
另外，在本实施方式的半导体装置100、100A－100F中，第三双极晶体管40在发射层5与发射极17之间具有电阻层(发射极镇流电阻88)。
由此，第一晶体管组Qa由不具有电阻层的第一双极晶体管20构成，第二晶体管组Qb由具有电阻层的第三双极晶体管40构成。半导体装置100能够根据集电极电压切换第一晶体管组Qa和第二晶体管组Qb来使其动作。因此，半导体装置100能够在低输出电力时以及高输出电力时的双方维持较高的电力附加效率。
另外，在本实施方式的半导体装置100、100A－100F中，第二双极晶体管30在发射层5与发射极17之间具有电阻层(发射极镇流电阻88)。
由此，能够将第一晶体管组Qa的第一最大高度Ha形成为与第二晶体管组Qb的第二最大高度Hb相同的高度。
另外，在本实施方式的半导体装置100、100A－100F中，第二双极晶体管30以及第三双极晶体管40的电阻层将AlGaAs作为主要成分。
由此，能够使第三双极晶体管40的电阻层的电阻值为所希望的大小。另外，能够用相同的工序形成第二双极晶体管30以及第三双极晶体管40的电阻层，能够将第二双极晶体管30的第二高度HEb形成为与第三双极晶体管40的第二高度HEb相同的高度。
另外，在本实施方式的半导体装置100、100A－100F中，多个第一双极晶体管20的基极16分别与共用的第一基极布线54a电连接。多个第一双极晶体管20的集电极15分别与共用的第一集电极布线51c电连接。第二双极晶体管30的基极16以及集电极15的至少一方与第一基极布线54a以及第一集电极布线51c非连接。
由此，第一晶体管组Qa中，多个第一双极晶体管20作为晶体管发挥作用，第二双极晶体管30不作为晶体管发挥作用。
另外，在本实施方式的半导体装置100、100A－100F中，多个第一双极晶体管20以及第二双极晶体管30的发射极17与共用的第一发射极布线53a电连接。多个第三双极晶体管40的发射极17与共用的第二发射极布线53b电连接。第一凸块61沿着第一发射极布线53a设置于第一发射极布线53a的上侧。第二凸块62沿着第二发射极布线53b设置于第二发射极布线53b的上侧。
由此，在第一凸块61形成有与第一双极晶体管20的第一高度HEa和第二双极晶体管30的第二高度HEb相应的凹凸。第一凸块61中设置有第二双极晶体管30的部分为第一最大高度Ha。由此，第一晶体管组Qa的第一最大高度Ha和第二晶体管组Qb的第二最大高度Hb相等。
(第二实施方式)
图16是第二实施方式所涉及的半导体装置的俯视图。图17是沿着图16的XVII－XVII’线的剖视图。图18是第二实施方式所涉及的半导体装置的等效电路图。在第二实施方式中，与上述第一实施方式不同，对在第一晶体管组Qa以及第二晶体管组Qb上设置有一个凸块63的构成进行说明。
如图16所示，在与半导体基板1的第一主面S1平行的X方向上，多个第一双极晶体管20和多个第二双极晶体管30被交替地配置。第一晶体管组Qa具有多个第一双极晶体管20。第二晶体管组Qb具有多个第二双极晶体管30。
如图17所示，发射极布线53、下部金属层56以及凸块63遍布多个第一双极晶体管20以及多个第二双极晶体管30而设置。发射极布线53与多个第一双极晶体管20的发射极17以及多个第二双极晶体管30的发射极17电连接。下部金属层56设置于发射极布线53上。凸块63设置于下部金属层56上。凸块63沿着发射极布线53设置于发射极布线53的上侧。
隔离区域50分别设置于第一双极晶体管20与第二双极晶体管30之间。集电极15与第一双极晶体管20以及第二双极晶体管30的各个对应地设置。换句话说，集电极15不被第一双极晶体管20和第二双极晶体管30共享。
如图18所示，第一双极晶体管20的各发射极(发射极17)以及第二双极晶体管30的各发射极(发射极17)与共用的发射极布线53连接，并被接地。
在第一晶体管组Qa中，多个第一双极晶体管20的各基极(基极16)经由电容86与共用的第一基极布线54a连接。另外，第一双极晶体管20的各基极(基极16)经由基极镇流电阻87与共用的第一基极偏置布线55a连接。第一双极晶体管20的各集电极(集电极15)与共用的第一集电极布线51c连接。
在第二晶体管组Qb中，多个第二双极晶体管30的各基极(基极16)与共用的第二基极布线54b连接。第二基极布线54b经由电容85与基极高频输入端子81b连接。另外，第二双极晶体管30的各基极(基极16)与共用的第二基极偏置布线55b连接。第二双极晶体管30的各集电极(集电极15)与共用的第二集电极布线51d连接。
通过这样的构成，构成第一晶体管组Qa的多个第一双极晶体管20放大从基极高频输入端子81a输入的高频信号，并将放大后的信号输出到集电极高频输出端子83a。另外，构成第二晶体管组Qb的第二双极晶体管30放大从基极高频输入端子81b输入的高频信号，并将放大后的信号输出到集电极高频输出端子83b。
如以上所述，在本实施方式的半导体装置100G中，构成第一晶体管组Qa的多个第一双极晶体管20和构成第二晶体管组Qb的多个第二双极晶体管30被交替地设置。而且，遍布多个第一双极晶体管20和多个第二双极晶体管30设置有共用的凸块63。
在本实施方式的半导体装置100G中，从第二主面S2到第一晶体管组Qa上的凸块63的最上面的高度和从第二主面S2到第二晶体管组Qb上的凸块63的最上面的高度不同。在该情况下，在将半导体装置100G安装到外部基板时，第一晶体管组Qa以及第二晶体管组Qb经由共用的凸块63与外部基板电连接。由此，半导体装置100G在安装到外部基板时能够抑制电连接不良的产生。
(第三实施方式)
图19是第三实施方式所涉及的半导体装置的剖视图。在第三实施方式中，与上述第一实施方式以及第二实施方式不同，对在第一凸块61以及第二凸块62上分别设置有焊料层65a、65b的构成进行说明。
如图19所示，焊料层65a遍布多个第一双极晶体管20以及多个第二双极晶体管30设置在第一凸块61上。焊料层65b遍布多个第三双极晶体管40设置在第二凸块62上。由此，在将半导体装置100H安装到外部基板时，搭载为焊料层65a、65b与外部基板的连接焊盘相接。而且，通过焊料回流处理等，第一凸块61以及第二凸块62经由焊料层65a、65b与连接焊盘粘合。
此外，本实施方式的构成能够应用于上述的第一实施方式以及第二实施方式的半导体装置100、100A－100G。
(第四实施方式)
图20是第四实施方式所涉及的功放模块的剖视图。图21是表示第四实施方式所涉及的功放模块的构成的框图。功放模块200具有模块基板210、半导体装置100、以及树脂层240。
模块基板210具有第一焊盘220、贯通导通孔211、第二焊盘212以及设置于基板内层的布线等。第一焊盘220是用于安装半导体装置100的端子。第二焊盘212是供给有基准电位的端子。第一焊盘220和第二焊盘212通过多个贯通导通孔211连接。
半导体装置100倒装(Flip chip)安装于模块基板210上。第一凸块61以及第二凸块62分别经由焊料230与第一焊盘220连接。由此，第一晶体管组Qa以及第二晶体管组Qb的各双极晶体管与模块基板210电连接。树脂层240设置于覆盖半导体装置100的模块基板210上。
如图21所示，功放模块200具有第一信号链Sc1和第二信号链Sc2。
第一信号链Sc1是第一高频信号流动的路径，具有第一输入端子91a、第一输入匹配电路93a、第一初级放大电路96a、第一级间匹配电路94a、第一输出级放大电路97a、第一输出匹配电路95a以及第一输出端子92a。第一输入匹配电路93a是匹配第一初级放大电路96a的输入侧的阻抗的电路。第一级间匹配电路94a是匹配第一初级放大电路96a的输出侧与第一输出级放大电路97a的输入侧之间的阻抗的电路。第一输出匹配电路95a是匹配第一输出级放大电路97a的输出侧的阻抗的电路。第一输入匹配电路93a、第一级间匹配电路94a以及第一输出匹配电路95a分别使用电容器以及电感器等构成。第一初级放大电路96a以及第一输出级放大电路97a分别由例如半导体装置100的第一晶体管组Qa构成。第一高频信号被从第一输入端子91a输入，通过各匹配电路以及各放大电路而放大，并从第一输出端子92a输出。
第二信号链Sc2是第二高频信号流动的路径，具有第二输入端子91b、第二输入匹配电路93b、第二初级放大电路96b、第二级间匹配电路94b、第二输出级放大电路97b、第二输出匹配电路95b以及第二输出端子92b。第二输入匹配电路93b、第二级间匹配电路94b以及第二输出匹配电路95b分别是具有与第一输入匹配电路93a、第一级间匹配电路94a以及第一输出匹配电路95a相同的功能的电路。第二初级放大电路96b以及第二输出级放大电路97b分别由例如半导体装置100的第二晶体管组Qb构成。第二高频信号被从第二输入端子91b输入，通过各匹配电路以及各放大电路放大，并从第二输出端子92b输出。
第一信号链Sc1和第二信号链Sc2不会同时电动作，按时间分开动作。即，在第一信号链Sc1电动作的期间，第二信号链Sc2电停止动作。在第二信号链Sc2电动作的期间，第一信号链Sc1电停止动作。由此，与低输出电力时以及高输出电力时的各个相应地，使第一信号链Sc1或者第二信号链Sc2动作，从而能够维持良好的电力附加效率。
附图标记说明
1…半导体基板；2…子集电层；3…集电层；4…基层；5…发射层；9…第一发射极镇流电阻层；10…第二发射极镇流电阻层；11…第三发射极镇流电阻层；15…集电极；16…基极；17…发射极；20…第一双极晶体管；30…第二双极晶体管；40…第三双极晶体管；51a…集电极连接布线；51c…第一集电极布线；51d…第二集电极布线；52a、52b；发射极连接布线；53…发射极布线；53a…第一发射极布线；53b…第二发射极布线；54a…第一基极布线；54b…第二基极布线；61…第一凸块；62…第二凸块；63…凸块；88…发射极镇流电阻；100…半导体装置；200…功放模块；Ha…第一最大高度；Hb…第二最大高度；HEa…第一高度；HEb…第二高度；Qa…第一晶体管组；Qb…第二晶体管组；S1…第一主面；S2…第二主面。

Claims (13)

1.一种半导体装置，具有：
半导体基板；
多个第一双极晶体管，它们设置于上述半导体基板的第一主面侧，且在与上述第一主面垂直的方向上在发射层与发射极之间具有第一高度；
至少一个的第二双极晶体管，设置于上述半导体基板的上述第一主面侧，且在与上述第一主面垂直的方向上在发射层与发射极之间具有比上述第一高度高的第二高度；以及
第一凸块，遍布多个上述第一双极晶体管和至少一个的上述第二双极晶体管的上侧而配置，
多个第三双极晶体管，设置于上述半导体基板的上述第一主面侧，且在与上述第一主面垂直的方向上在发射层与发射极之间具有上述第二高度；以及
第二凸块，遍布多个上述第三双极晶体管而配置，
多个上述第一双极晶体管的基极分别与共用的第一基极布线电连接，多个上述第一双极晶体管的集电极分别与共用的第一集电极布线电连接，
上述第二双极晶体管的基极以及集电极两者中的至少一个不与上述第一基极布线以及上述第一集电极布线连接。
2.根据权利要求1所述的半导体装置，其中，
在与上述半导体基板的上述第一主面平行的方向上，上述第一双极晶体管配置于上述第二双极晶体管与上述第三双极晶体管之间。
3.根据权利要求1或者2所述的半导体装置，其中，
上述第三双极晶体管是异质结双极晶体管。
4.根据权利要求1或者2所述的半导体装置，其中，
上述第二凸块是柱凸块。
5.根据权利要求1或者2所述的半导体装置，其中，
上述第三双极晶体管在上述发射层与上述发射极之间具有电阻层。
6.根据权利要求5所述的半导体装置，其中，
上述第三双极晶体管的上述电阻层以AlGaAs为主要成分。
7.根据权利要求1或者2所述的半导体装置，其中，
多个上述第一双极晶体管以及上述第二双极晶体管的发射极与共用的第一发射极布线电连接，
多个上述第三双极晶体管的发射极与共用的第二发射极布线电连接，
上述第一凸块沿着上述第一发射极布线设置于上述第一发射极布线的上侧，
上述第二凸块沿着上述第二发射极布线设置于上述第二发射极布线的上侧。
8.根据权利要求1所述的半导体装置，其中，
具有多个上述第二双极晶体管，
在与上述半导体基板的上述第一主面平行的方向上，多个上述第一双极晶体管和多个上述第二双极晶体管交替而配置。
9.根据权利要求8所述的半导体装置，其中，
多个上述第一双极晶体管的基极分别与共用的第一基极布线电连接，多个上述第一双极晶体管的集电极分别与共用的第一集电极布线电连接，
上述第二双极晶体管的基极分别与共用的第二基极布线电连接，多个上述第二双极晶体管的集电极分别与共用的第二集电极布线电连接。
10.根据权利要求1或者2所述的半导体装置，其中，
上述第一双极晶体管以及上述第二双极晶体管是异质结双极晶体管。
11.根据权利要求1或者2所述的半导体装置，其中，
上述第一凸块是柱凸块。
12.根据权利要求1或者2所述的半导体装置，其中，
上述第二双极晶体管在上述发射层与上述发射极之间具有电阻层。
13.根据权利要求12所述的半导体装置，其中，
上述第二双极晶体管的上述电阻层以AlGaAs为主要成分。
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