CN110676213B - Silicon through hole interconnection copper wire barrier layer optimization method aiming at small line width requirement - Google Patents
Silicon through hole interconnection copper wire barrier layer optimization method aiming at small line width requirement Download PDFInfo
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- CN110676213B CN110676213B CN201910883203.2A CN201910883203A CN110676213B CN 110676213 B CN110676213 B CN 110676213B CN 201910883203 A CN201910883203 A CN 201910883203A CN 110676213 B CN110676213 B CN 110676213B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
The invention discloses a method for optimizing a barrier layer of a Through Silicon Via (TSV) interconnected copper wire aiming at the requirement of small line width, which comprises the following steps of: the Ta-TaN barrier layer with different thicknesses is prepared by adopting a Ta and TaN double layer as a through hole barrier layer, the electromigration performance of the resistance of the interconnection system under different thicknesses is measured, and a Ta-TaN barrier layer film with expected electromigration capability and low interconnection resistance and proper thickness is selected as a target barrier layer. The Ta-TaN barrier layer film with the expected electromigration capability and the low interconnection resistance and the proper thickness is finally obtained by preparing the Ta-TaN barrier layers with different thicknesses and measuring the electromigration performance of the resistance of the interconnection system under different thicknesses.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing processes, in particular to a method for optimizing a silicon through hole interconnection copper wire barrier layer aiming at a small line width requirement.
Background
With the development of super large scale hybrid integrated circuits, the falling speed of gate delay is faster and faster, the resistance and the capacitance are increased, and the distance is narrower, so that the increase of the integration level is limited. The solution is to use Cu interconnect technology based on through-silicon vias, which are used to connect one metal layer to another, providing a critical path for signals to flow from different devices through the chip. Since via resistance is directly related to RC delay, via resistance is critical to device performance.
The via holes are obtained by deep reactive ion etching (DIRE) or Inductively Coupled Plasma (ICP) etching, and in order to prevent short circuit between devices, an insulating layer SiO is first formed on the via holes2Since Cu has a strong diffusivity in Si and a Si-containing dielectric layer, so that Cu generates traps therein to degrade device performance, it is necessary to prepare a barrier layer on the insulating layer. The most direct method for reducing the via resistance is to increase the feature size of the bottom via, but the increase of the feature size reduces the Time Dependent Dielectric Breakdown (TDDB) performance and affects the yield of the product; the current integration process is changed and may be tuned by introducing new barrier layer materials such as cobalt (Co) and ruthenium (Ru)The swimming process has an influence; extending the via into the underlying trench by the etching process may increase the contact area and thus reduce resistance, but may cause corner cut problems and sidewall damage during etching. Reducing the barrier thickness at the bottom of the via is currently the most feasible solution without introducing new integration solutions.
At present, the barrier layer materials are mainly high-melting point metals (Cr, Ti, Nb, Mo, Ta and W), nitrides, carbides and silicides of the high-melting point metals (TaN, TaSi, TaC and TiN), and high-melting point metal ternary compounds (Ti-Si-N, Zr-Si-N, W-Si-N, Ta-B-N, Zr-Al-N, Ti-Al-N). Ta and its nitride TaN have been established as the key position of copper diffusion barrier layer in various experiments at home and abroad. Ta and compounds thereof have good interfacial adhesion, low resistivity, good thermal stability and high electrical conductivity, and Ta materials gradually become barrier layer materials for preventing copper diffusion and are receiving more and more attention.
Barrier deposition processes are a key component in balancing feature coverage and electrical parameters while achieving desired Electromigration (EM) performance. The thickness of the barrier layer, dc/ac bias during deposition, etc. play an important role in determining the quality and quantity of the deposited barrier film. Balancing these parameters allows the film to be tuned for good reliability while reducing the resistance of the via.
Disclosure of Invention
The invention aims to provide a method for optimizing a barrier layer of a through silicon via interconnection copper wire aiming at the requirement of small line width aiming at the technical defects in the prior art.
The technical scheme adopted for realizing the purpose of the invention is as follows:
a method for optimizing a barrier layer of a through silicon via interconnection copper wire aiming at the requirement of small line width comprises the following steps: and preparing Ta-TaN barrier layers with different thicknesses by adopting the Ta and TaN double layers as the through hole barrier layers, measuring the electromigration performance of the resistance of the interconnection system under different thicknesses, and obtaining the Ta-TaN barrier layer film with the expected electromigration capability and low interconnection resistance and proper thickness.
The Ta-TaN barrier layer film with the expected electromigration capability and the low interconnection resistance and the proper thickness is finally obtained by preparing the Ta-TaN barrier layers with different thicknesses and measuring the electromigration performance of the resistance of the interconnection system under different thicknesses.
Drawings
Fig. 1 is a process flow diagram of the method for optimizing a barrier layer of a copper wire for a through silicon via interconnection according to the small line width requirement of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In order to obtain a barrier layer with better barrier effect and obtain the lowest possible resistance of an interconnection system, a Ta-TaN double-layer structure is generally adopted as a diffusion barrier layer of a copper interconnection line. There are many ways to reduce resistance, increasing the feature size of the bottom of the via can reduce the TDDB performance, changing the barrier material can introduce new process problems, deepening the etching to increase the contact area can damage the sidewalls.
One important factor for the increase in RC delay is the resistance and capacitance constraints on smaller and smaller line widths. The copper interconnect lines encapsulated by the diffusion barrier layer increase in size and resistance, assuming the interconnect material resistivity is ρ and the barrier material resistivity is ρbThe length L, the width W and the height H of the interconnection line, the thickness of the barrier layer is b, then the diffusion barrier layer is removed, and the self resistance of the interconnection line is R:
R＝Lρ/(W×H)
when the interconnect line is coated with a barrier layer, the interconnect system resistance becomes Rb:
let us show ρbAnd b will lead to an increase in the resistance Rb, so in order to reduce the resistance of the interconnect system, the resistivity and thickness of the barrier layer should be as low as possible.
Therefore, the present invention provides an optimum combination of Ta-TaN bilayer barrier Ta and TaN thickness, starting from Ta and TaN thickness, by taking the example of a through-silicon via, and composing the barrier with a moderately thick Ta layer and a thinner TaN layer to obtain a barrier layer that best suppresses copper diffusion at the minimum interconnect system resistance.
The technical scheme for preparing the Ta-TaN double-layer barrier layer with different thicknesses is as follows:
(1) using ethanol and acetone to make the surface have SiO2Carrying out ultrasonic cleaning and drying on the Si substrate 1 of the insulating layer 4, and then carrying out sputtering cleaning in a vacuum chamber for 15 minutes;
(2) first to SiO2Etching the insulating layer, and then etching the Si substrate by using Inductively Coupled Plasma (ICP) to obtain 5 through holes with the same depth and width, wherein the depth of each through hole is 200nm, the width of each through hole is 30nm (as shown in a second graph in figure 1), and the side wall and the bottom of each through hole are oxidized to generate the insulating layer (as shown in a third graph in figure 1);
(3) depositing a Ta film 2 on the through hole by a reactive magnetron sputtering method by using a target material of a metal Ta target with the purity of 99.95 percent, wherein argon (Ar)2) The flow rate of the sputtering target is 36mL/min, the working air pressure is 0.3Pa during sputtering, the sputtering power is 100W, and the surfaces of No. 1 to No. 5 through holes are sputtered by 10nm, 30nm, 50nm, 70nm and 90nm respectively;
(4) maintaining Ar2The flow is unchanged, and N passes through the through hole2，N2The flow rate is 4mL/min, TaN films 3 with different thicknesses are obtained by controlling the time, and through holes from No. 1 to No. 5 sputter 90nm, 70nm, 50nm, 30nm and 10nmTaN films respectively;
(5) depositing a Cu film 5 by using a synchronous etching filling method, filling a through hole, directly performing synchronous etching in a cavity after depositing Cu for a single time until the through hole is filled with Cu, wherein the thickness of the Cu film is about 100 nm;
(6) carrying out aging diffusion characteristic research on a sample by adopting vacuum annealing, annealing at 450 ℃ for 30min, and keeping the vacuum degree at 1 x 10 < -3 > Pa;
(7) the resistivity of vias No. 1 through 5 were measured separately and the expected Electromigration (EM) performance of each via was compared.
The invention realizes the optimization of the copper diffusion barrier layer, well reduces the resistance of the barrier layer, improves the product performance, obtains better reliability and improves the product yield.
The invention designs the Ta layer with reduced TaN thickness and proper thickness as the barrier layer of copper diffusion by considering the resistance of the through hole and the electromigration characteristic without adding a new process, so that the TaN layer has better performance and saves the cost.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (2)
1. The optimization method of the silicon through hole interconnection copper wire barrier layer aiming at the small line width requirement is characterized by comprising the following steps of: and preparing Ta-TaN barrier layers with different thicknesses by adopting the Ta and TaN double layers as the through hole barrier layers, measuring the electromigration performance of the resistance of the interconnection system under different thicknesses, and obtaining the Ta-TaN barrier layer film with the expected electromigration capability and low interconnection resistance and proper thickness.
2. The optimization method for the barrier layer of the copper wire for the interconnection of the through silicon via aiming at the small linewidth requirement, according to claim 1, wherein the Ta-TaN barrier layer is prepared by the following steps:
ultrasonically cleaning and drying the Si substrate by using ethanol and acetone, and then carrying out sputtering cleaning in a vacuum chamber for 15 minutes;
etching by using inductively coupled plasma to obtain 5 through holes with the same depth and width, wherein the depth of each through hole is 200nm, the width of each through hole is 30nm, and the side wall and the bottom of each through hole are oxidized to generate an insulating layer;
depositing Ta on the through hole by using a target material of a metal Ta target with the purity of 99.95 percent by using a reactive magnetron sputtering method, wherein Ar is argon2The flow rate of (2) is 36mL/min, the working air pressure is 0.3Pa during sputtering, and the sputtering power isSputtering 10nm, 30nm, 50nm, 70nm and 90nm on the surfaces of 100W through holes from No. 1 to No. 5 respectively;
maintaining Ar2The flow is unchanged, and N passes through the through hole2，N2The flow rate is 4mL/min, TaN films with different thicknesses are obtained by controlling the time, and through holes from No. 1 to No. 5 are respectively sputtered with 90nm, 70nm, 50nm, 30nm and 10nmTaN films;
depositing a Cu film by using a synchronous etching filling method, directly performing synchronous etching in the cavity after depositing Cu for a single time until the through hole is filled with Cu, wherein the thickness of the Cu film is about 100 nm;
carrying out aging diffusion characteristic research on a sample by adopting vacuum annealing, annealing at 450 ℃ for 30min, and keeping the vacuum degree at 1 x 10 < -3 > Pa;
the resistivity of vias No. 1 through 5 were measured separately and the expected electromigration performance of each via was compared.
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| CN102332426A (en) * | 2011-09-23 | 2012-01-25 | 复旦大学 | Manufacturing method of copper diffusion impervious layers for nanometer ICs (integrated circuits) |
| CN102768988A (en) * | 2012-07-25 | 2012-11-07 | 上海华力微电子有限公司 | Method for effectively judging blocking capability of copper diffusion blocking layer |
| CN103681573A (en) * | 2012-09-12 | 2014-03-26 | 三星电子株式会社 | Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices including a via structure |
| CN103972160A (en) * | 2014-04-22 | 2014-08-06 | 上海华力微电子有限公司 | Method for lowering influence on copper interconnection reliability from online WAT testing |
| CN105097664A (en) * | 2012-07-31 | 2015-11-25 | 台湾积体电路制造股份有限公司 | Device and method for reducing contact resistance of metal |
| CN105514093A (en) * | 2016-01-22 | 2016-04-20 | 天津大学 | Semiconductor capacitor based on through-silicon via technology and manufacturing method and packaging structure thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6979648B2 (en) * | 2003-06-11 | 2005-12-27 | Texas Instruments Incorporated | Method for BARC over-etch time adjust with real-time process feedback |
| US9704804B1 (en) * | 2015-12-18 | 2017-07-11 | Texas Instruments Incorporated | Oxidation resistant barrier metal process for semiconductor devices |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332426A (en) * | 2011-09-23 | 2012-01-25 | 复旦大学 | Manufacturing method of copper diffusion impervious layers for nanometer ICs (integrated circuits) |
| CN102768988A (en) * | 2012-07-25 | 2012-11-07 | 上海华力微电子有限公司 | Method for effectively judging blocking capability of copper diffusion blocking layer |
| CN105097664A (en) * | 2012-07-31 | 2015-11-25 | 台湾积体电路制造股份有限公司 | Device and method for reducing contact resistance of metal |
| CN103681573A (en) * | 2012-09-12 | 2014-03-26 | 三星电子株式会社 | Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices including a via structure |
| CN103972160A (en) * | 2014-04-22 | 2014-08-06 | 上海华力微电子有限公司 | Method for lowering influence on copper interconnection reliability from online WAT testing |
| CN105514093A (en) * | 2016-01-22 | 2016-04-20 | 天津大学 | Semiconductor capacitor based on through-silicon via technology and manufacturing method and packaging structure thereof |
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