CN110676213A - Silicon through hole interconnection copper wire barrier layer optimization method aiming at small line width requirement - Google Patents

Abstract

The invention discloses a method for optimizing a copper wire barrier layer of through-silicon-hole interconnection for small line width requirements, comprising the steps of: using Ta and TaN double layers as the through-hole barrier layer, preparing Ta-TaN barrier layers with different thicknesses, and measuring different thicknesses. The resistance-resistance electromigration performance of the interconnection system under thickness, a Ta-TaN barrier layer film of suitable thickness with expected electromigration ability and low interconnection resistance was selected as the target barrier layer. The invention adopts Ta and TaN double layers as the through-hole barrier layer, prepares Ta-TaN barrier layers with different thicknesses, measures the resistance electromigration performance of the interconnection system under different thicknesses, and finally obtains the expected electromigration ability and low interconnection resistance. Ta-TaN barrier film of suitable thickness.

Description

A method for optimizing the copper wire barrier layer of through-silicon via interconnection for small line width requirements

technical field

The present invention relates to the technical field of integrated circuit manufacturing process, in particular to a method for optimizing a copper wire barrier layer of through-silicon via interconnection for small wire width requirements.

Background technique

With the development of VLSI, the gate delay is decreasing faster and the resistance and capacitance are increasing, and the pitch is narrower, which limits the increase of integration. The solution is to use Cu interconnect technology based on through-silicon vias, which are used to connect one metal layer to another, providing a critical path for signals to flow through the chip from different devices. Via resistance is critical to device performance because it is directly related to RC delay.

The through hole is obtained by deep reactive ion etching (DIRE) or inductively coupled plasma (ICP) etching. In order to prevent short circuit between devices, an insulating layer of SiO ₂ is firstly made on it. There is strong diffusivity in the dielectric layer of Cu, so that Cu will generate traps in it, which will degrade the device performance. Therefore, a barrier layer needs to be prepared on the insulating layer. The most direct way to reduce through-hole resistance is to increase the feature size of the bottom via, but the increase of the feature size will reduce the performance of time-dependent dielectric breakdown (TDDB) and affect the product yield; by introducing new barrier layer materials Such as cobalt (Co) and ruthenium (Ru) will change current integration processes and may have an impact on downstream processes; extending vias into the underlying trenches through etching processes can increase contact area and thus reduce resistance, but in etching Cornering problems and sidewall damage may occur during the process. Reducing the thickness of the barrier layer at the bottom of the via is currently the most feasible solution without introducing a new integration solution.

At present, the barrier layer materials are mainly high melting point metals (Cr, Ti, Nb, Mo, Ta and W), nitrides, carbides and silicides (TaN, TaSi, TaC, TiN) of high melting point metals, and three high melting point metals. Elemental compounds (Ti-Si-N, Zr-Si-N, W-Si-N, Ta-B-N, Zr-Al-N, Ti-Al-N). Various experiments at home and abroad have established the key position of Ta and its nitride TaN as copper diffusion barrier. Ta and its compounds have good interfacial adhesion, low resistivity, good thermal stability and high electrical conductivity. Ta material has gradually become a barrier material to prevent copper diffusion, and has attracted more and more people's attention .

The barrier layer deposition process is a critical component to achieve desired electromigration (EM) performance while balancing feature coverage and electrical parameters. Barrier thickness, DC/AC bias during deposition, etc. play an important role in determining the quality and quantity of the deposited barrier film. Balancing these parameters can tune the film for good reliability while reducing via resistance.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for optimizing the copper wire barrier layer of through-silicon via interconnection for the requirements of small wire width in view of the technical defects existing in the prior art.

The technical scheme adopted for realizing the purpose of the present invention is:

A method for optimizing a copper wire barrier layer of a through-silicon via interconnection for small line width requirements, comprising the steps of: using Ta and TaN double layers as the through-hole barrier layer, preparing Ta-TaN barrier layers with different thicknesses, and measuring the interconnection under different thicknesses. The resistive electromigration performance of the interconnected system is obtained, and a Ta-TaN barrier film of suitable thickness with expected electromigration capability and low interconnection resistance is obtained.

In the present invention, Ta and TaN double layers are used as the through hole blocking layer, and the resistance electromigration performance of the interconnection system under different thicknesses is measured by preparing Ta-TaN blocking layers with different thicknesses, and finally the expected electromigration ability and low interconnection resistance are obtained. suitable thickness of Ta-TaN barrier film.

Description of drawings

FIG. 1 is a process flow diagram of a method for optimizing a copper line barrier layer of a TSV interconnection according to the present invention for a small line width requirement.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

In order to obtain a barrier layer with better barrier effect and to obtain the smallest possible resistance of the interconnection system, a Ta-TaN double-layer structure is generally used as the diffusion barrier layer of the copper interconnection. There are many ways to reduce resistance. Increasing the feature size at the bottom of the via will reduce the performance of the TDDB, changing the barrier layer material will introduce new process problems, and increasing the contact area by deepening the etching method will cause damage to the sidewall.

An important factor in the increase in RC delay is the resistance and capacitance constraints on smaller and smaller line widths. The size and resistance of the copper connection encapsulated by the diffusion barrier layer will increase. It is assumed that the resistivity of the interconnect material is ρ, the resistivity of the barrier layer material is ρ _b , the length of the interconnect line is L, the width is W, and the thickness of the barrier layer is high H. is b, then the de-diffusion barrier layer is de-diffused, and the resistance of the interconnect is R:

R=Rρ/(W×H)

When the interconnect is covered with a barrier layer, the interconnect system resistance becomes Rb:

It can be seen from the formula that the increase of ρ _b and b will lead to the increase of the resistance Rb, so in order to reduce the resistance of the interconnection system, the resistivity and thickness of the barrier layer should be as low as possible.

Therefore, the present invention takes TSV as an example to provide an optimal combination of Ta and TaN thicknesses of Ta-TaN double-layer barrier layers, that is, starting from the thickness of Ta and TaN, with moderately thick Ta layer and thinner TaN layer The barrier layer is composed to obtain the best barrier layer for inhibiting copper diffusion at minimum interconnect system resistance.

Among them, the technical solutions for preparing Ta-TaN double-layer barrier layers with different thicknesses are as follows:

(1) with ethanol and acetone, the Si matrix ₁ with SiO insulating layer 4 on the surface is ultrasonically cleaned and dried, and then 15 minutes of sputter cleaning is carried out in a vacuum chamber;

(2) First etch the _SiO2 insulating layer, and then use Inductively Coupled Plasma (ICP) to etch the Si substrate to obtain 5 through holes with the same depth and width. The depth of the through holes is 200nm and the width is 30nm (Figure 1). The second picture in the middle), oxidize the sidewall and bottom of the through hole to generate an insulating layer (the third picture in Figure 1);

(3) Using a target with a purity of 99.95% metal Ta target, the Ta film 2 is deposited on the through hole by reactive magnetron sputtering, wherein the flow rate of argon (Ar ₂ ) is 36 mL/min, and the working pressure during sputtering is 0.3Pa, sputtering power 100W, surface sputtering of 10nm, 30nm, 50nm, 70nm, 90nm through holes 1 to 5 respectively;

(4) Keep the flow rate of Ar ₂ unchanged, pass N ₂ to the through hole, the flow rate of N ₂ is 4 mL/min, and obtain TaN films with different thicknesses by controlling the time. , 50nm, 30nm, 10nm TaN film;

(5) Using the synchronous etching and filling method to deposit the Cu film 5, fill the through holes, and directly perform synchronous etching in the cavity after a single deposition of Cu, until the through holes are filled with Cu, and the thickness of the Cu film is about 100 nm ;

(6) The aging diffusion characteristics of the samples were studied by vacuum annealing, annealed at 450℃ for 30min, and the vacuum degree was kept at 1×10-3Pa;

(7) Measure the resistivity of No. 1 to No. 5 vias respectively, and compare the expected electromigration (EM) performance of each via.

The invention realizes the optimization of the copper diffusion barrier layer, reduces the resistance of the barrier layer well, improves the product performance, obtains better reliability, and improves the product yield.

In the present invention, without adding a new process, considering the resistance and electromigration characteristics of the through hole itself, a Ta layer with a reduced TaN thickness and a moderately thick Ta layer is designed as a barrier layer for copper diffusion, so that it can obtain better performance, save costs.

The above are only the preferred embodiments of the present invention. It should be noted that, for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. These improvements and Retouching should also be regarded as the protection scope of the present invention.

Claims (2)

1. the method for optimizing the copper wire barrier layer of through-silicon via interconnection required for small line width, is characterized in that, comprises the steps: using Ta and TaN double layers as the through-hole barrier layer, preparing the Ta-TaN barrier layers of different thicknesses, measuring The resistance electromigration performance of the interconnection system under different thicknesses was obtained, and a Ta-TaN barrier layer film of suitable thickness with expected electromigration capability and low interconnection resistance was obtained. 2. according to the described method for optimizing the copper wire barrier layer of through-silicon via interconnection required for small line width according to claim 1, it is characterized in that, the preparation step of described Ta-TaN barrier layer is as follows: The Si substrate was ultrasonically cleaned and dried with ethanol and acetone, and then sputtered in a vacuum chamber for 15 minutes; Five through holes with the same depth and width were obtained by inductively coupled plasma etching, the depth of the through holes was 200nm and the width was 30nm, and the sidewalls and bottoms of the through holes were oxidized to generate an insulating layer; A target material with a purity of 99.95% metal Ta target was used to deposit Ta on the through-hole by reactive magnetron sputtering. _The flow rate of argon gas was 36mL/min, the working pressure during sputtering was 0.3Pa, and the sputtering power was 100W. , 10nm, 30nm, 50nm, 70nm, 90nm surface sputtering of through holes 1 to 5 respectively; Keep the flow rate of Ar ₂ unchanged, pass N ₂ to the through hole, the flow rate of N ₂ is 4mL/min, and obtain TaN films with different thicknesses by controlling the time. No. 1 to No. 5 through holes are sputtered at 90nm, 70nm, 50nm, 30nm respectively. , 10nm TaN film; For the Cu film deposited by the synchronous etching and filling method, after a single deposition of Cu, synchronous etching is performed directly in the cavity until the through hole is filled with Cu, and the thickness of the Cu film is about 100 nm; The aging diffusion characteristics of the samples were studied by vacuum annealing, annealed at 450℃ for 30min, and the vacuum degree was kept at 1×10-3Pa; The resistivity of vias No. 1 to No. 5 were measured respectively, and the EM performance of each via was compared.

Images