CN110620040A

CN110620040A - Method for improving process stability in production

Info

Publication number: CN110620040A
Application number: CN201910862345.0A
Authority: CN
Inventors: 史丹丹; 胡明; 罗世金; 张帜; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2019-12-27
Anticipated expiration: 2039-09-12
Also published as: CN110620040B

Abstract

The invention relates to the technical field of semiconductors, and provides a method for improving process stability in production. After the polysilicon deposition process is completed in the common source array, the method comprises the following steps: detecting a warping value of the wafer, and determining a polysilicon annealing strategy according to the warping value; or determining the processing technology type of the current wafer, and acquiring a corresponding polycrystalline silicon annealing strategy according to the processing technology type; the polycrystalline silicon annealing strategy comprises an annealing mode for solidifying polycrystalline silicon and/or an annealing mode for adjusting the stress of the polycrystalline silicon; and executing the obtained polysilicon annealing strategy on the currently processed wafer. The invention combines the annealing characteristics of the polysilicon, designs a set of perfect annealing strategy for the annealing characteristics, and fully exerts the capability of the annealing strategy on the warping condition in the wafer processing process. Particularly, the saddle-shaped warpage can be effectively improved.

Description

Method for improving process stability in production

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of semiconductors, in particular to a method for improving process stability in production.

[ background of the invention ]

During the manufacturing process of the wafer and the subsequent process of manufacturing electronic components on the surface of the wafer, the curvature distribution of the wafer may be unbalanced, resulting in the warpage of the wafer. The occurrence of wafer warpage can cause various problems, such as the falling of stacked films on the wafer surface, wafer cracking, unstable layout alignment performance, failure of the chuck to suck the wafer in the subsequent process, etc., which can not complete the subsequent process, ultimately resulting in unstable wafer product performance and reduced yield and yield of wafer products.

Bowl wafers are a common wafer bow profile imbalance. For bowl-shaped wafers, the curvature distribution is usually balanced by depositing a layer on the back side of the wafer (the surface opposite to the front side on which the device structures are formed or pre-formed) to balance the curvature distribution in the X-direction and the Y-direction (the direction perpendicular to the X-direction and both in the plane of the wafer). The reason is that the main reason for unbalanced wafer curvature distribution is stress, and the film layer deposited on the back surface can counteract the stress on the front surface of the wafer, so as to improve the problem of unbalanced wafer curvature distribution.

However, the additional film layer manufacturing method not only increases the use of additional materials in the wafer processing process, but also increases unnecessary process procedures, thereby affecting the wafer processing and production efficiency.

[ summary of the invention ]

The technical problem to be solved by the embodiment of the invention is to find a method for compensating the wafer warpage for improving the process stability in production, and can overcome the problems of resource waste and complicated process in the warpage solution of the wafer in the prior art.

The technical problem to be further solved by the embodiment of the invention is how to adapt to the recovery of wafer warpage under different warpage values under the condition that the total annealing time is the same in the process with strictly limited process node duration through the design of the annealing process.

The embodiment of the invention adopts the following technical scheme:

in a first aspect, the present invention provides a method for improving process stability in production, the method being implemented after filling polysilicon into a common source trench of a three-dimensional memory, the method comprising:

detecting a warping value of the wafer, and determining a polysilicon annealing strategy according to the warping value; or determining the processing technology type of the current wafer, and acquiring a corresponding polycrystalline silicon annealing strategy according to the processing technology type;

the polycrystalline silicon annealing strategy comprises an annealing mode for solidifying polycrystalline silicon and/or an annealing mode for adjusting the stress of the polycrystalline silicon;

and executing the obtained polysilicon annealing strategy on the currently processed wafer.

Preferably, when the polysilicon annealing strategy is determined according to the warp value by detecting the warp value of the wafer, the annealing strategy includes:

when the warpage value is determined to belong to the first interval, annealing is carried out in an annealing mode of solidified polycrystalline silicon;

when the warping value is determined to belong to the second interval, annealing is carried out by adopting an annealing mode of adjusting the stress of the polycrystalline silicon;

the first interval is a process stability allowable warping range, and the second interval is a warping range which needs to be adjusted according to process stability.

Preferably, when the processing technology type of the current wafer is determined and the corresponding polysilicon annealing strategy is obtained according to the processing technology type, the annealing strategy is obtained according to wafer statistics of historical processing, wherein the statistical process comprises:

determining the type of a processing technology of the wafer, and detecting the warping value of the wafer;

when the warpage value is determined to belong to the second interval, annealing by adopting one or more preset annealing control parameters for adjusting the stress of the polycrystalline silicon;

determining a first interval to which the wafer warpage value after the control parameter for adjusting the polysilicon stress is annealed, and taking the annealing control parameter for correspondingly adjusting the polysilicon stress as an annealing mode for adjusting the polysilicon stress corresponding to the processing technology type; and the annealing strategy of the wafer under the corresponding processing technology type is the annealing mode for adjusting the stress of the polycrystalline silicon.

Preferably, the detecting the warpage value of the wafer specifically includes:

detecting the warpage value of the wafer in the Y-axis direction, wherein the first interval is [ -50,0] um; the second interval is [ -500, -50) um;

wherein the Y direction is perpendicular to the extending direction of the common source trench.

Preferably, the annealing method for solidifying the polysilicon specifically includes:

the temperature on the initial annealing time node and the temperature on the finish annealing time node are both larger than or equal to 900 ℃, and the annealing time is controlled to be 5-10 s.

Preferably, the annealing temperature and time control curve in the annealing mode for solidifying the polysilicon is a peak curve, wherein the starting point of the peak curve corresponding to the annealing starting temperature is 900 ℃, the maximum temperature of the corresponding peak curve is 1100 ℃, and the annealing end point temperature is 900 ℃.

Preferably, the annealing method for adjusting the stress of the polysilicon specifically includes:

the annealing temperature is controlled at 600-900 ℃, and the annealing time is controlled at 5-60 min.

Preferably, the annealing proportion is determined according to the warpage value, specifically:

determining the proportion of crystal grains with the crystal orientation converted into (100) in the polycrystalline silicon and crystal grains with the crystal orientation converted into (110) in the polycrystalline silicon according to the warpage value, and controlling the annealing temperature 625 in the annealing process+Annealing time and annealing temperature 675 of 5 deg.C+The annealing time is 5 ℃; wherein, temperature 625+5 ℃ is the annealing temperature corresponding to the formation of the (100) crystal orientation, temperature 675+5 ℃ is the annealing temperature corresponding to the formation of the (110) crystal orientation.

Preferably, the determining the annealing mixture ratio specifically further comprises:

determining the annealing proportion by combining the distribution characteristic of the common source trench on the wafer and the structural characteristic of the polycrystalline silicon;

the distribution characteristics of the common source trenches on the wafer comprise one or more of the total number of the common source trenches on the wafer, the average length of the common source trenches on the wafer, and the distribution parameters of the common source trenches on the wafer; the structural characteristics of the polysilicon include the width and depth of the polysilicon in the common source trench.

Preferably, the first interval is [ -30,0] um, and the second interval is [ -80, -30) um, then the method further comprises:

if the warpage value is less than [ -80, -50] um, directly using 625 ℃ for annealing treatment; if the warping value is between-50 and-30 um, then annealing treatment is carried out at 625 ℃ and 675 ℃ according to a first preset time ratio.

Preferably, before detecting the warpage value of the wafer, the method further comprises: and doping the polysilicon.

Compared with the prior art, the embodiment of the invention has the beneficial effects that:

the technical scheme provided by the invention is a feasible and effective solution obtained after a plurality of test experiments by the inventor. The method combines the annealing characteristics of the polycrystalline silicon, and a set of perfect annealing strategy is designed for the annealing characteristics, so that the capability of the method for improving the warping condition in the wafer processing process is fully exerted. Particularly, the saddle-shaped warpage can be effectively improved.

Furthermore, in a preferred embodiment of the present invention, by setting the time ratio of the specific annealing temperature, a solution matched with the specific annealing temperature can be provided for different warpage conditions under the condition of uniform total annealing time length, so that the adjusted warpage not only meets the preset requirement of the first interval, but also does not cross from a negative warpage value in the Y direction to a positive warpage value in the Y direction, and the stability of the structure obtained by historical processing is ensured.

[ description of the drawings ]

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic illustration of a prior art bowl wafer warpage provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a prior art raised wafer warpage provided by an embodiment of the present invention;

FIG. 3 is a schematic illustration of a saddle-shaped wafer warp according to the prior art provided by an embodiment of the present invention;

FIG. 4 is a schematic flow chart of a method for improving process stability in production according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an annealing temperature-control time curve according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another annealing temperature-control time curve provided by the embodiment of the invention;

FIG. 7 is a schematic flow chart of an annealing process for adjusting polysilicon stress according to an embodiment of the present invention;

FIG. 8 is a graph illustrating an annealing temperature control time curve in another annealing method for adjusting polysilicon stress according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating an ACS structure in a 3D NAND structure according to an embodiment of the present invention;

FIG. 10 is a schematic flow chart of a method for improving process stability in production according to an embodiment of the present invention;

FIG. 11 is a schematic flow chart of a method for improving process stability in production according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a 3D NAND structure including memory strings and a stack structure during formation according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of an insulating pillar structure formed during a process of forming a 3D NAND structure according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of an ACS trench structure formed during the formation of a 3D NAND structure according to an embodiment of the present invention;

FIG. 15 is a schematic diagram illustrating a 3D NAND structure according to an embodiment of the present invention after etching a sacrificial layer;

FIG. 16 is a schematic diagram illustrating the formation of a source dopant region structure during the formation of a 3D NAND structure according to an embodiment of the present invention;

FIG. 17 is a structural diagram illustrating a completed gate during formation of a 3D NAND structure in accordance with an embodiment of the present invention;

FIG. 18 is a schematic diagram illustrating ACS trench processing performed during formation of a 3D NAND structure according to an embodiment of the present invention;

FIG. 19 is a schematic diagram illustrating ACS fabrication performed during formation of a 3D NAND structure according to an embodiment of the present invention;

fig. 20 is a structural diagram illustrating a control gate conductive contact is formed in a process of forming a 3D NAND structure according to an embodiment of the invention.

[ detailed description ] embodiments

Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures. The flowcharts, block diagrams, and possible architectures, functions, and operations of the systems, devices, and the apparatus according to the embodiments of the present invention are illustrated in the figures, and the block diagrams, and the block sequences of the figures are only used for better illustrating the processes and steps of the embodiments, and should not be taken as limiting the invention itself.

In the embodiments of the present invention, the symbol "/" indicates the meaning of having both functions, and the symbol "a and/or B" indicates that the combination between the preceding and following objects connected by the symbol includes three cases of "a", "B", "a and B".

In general, terms may be understood at least in part from the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a" or "the" may be understood to convey a singular use or to convey a plural use, depending at least in part on the context. Moreover, also depending at least in part on the context, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily expressly stated.

It should be readily understood that the meaning of "on …", "above …" and "above …" in this disclosure should be read in the broadest manner such that "on …" means not only "directly on" but also including the meaning of "on" something with intervening features or layers therebetween, and "above …" or "above …" means not only "above" or "above" something, but may also include the meaning of "above" or "above" something with no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature or features, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations in use or operation of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to an object onto which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers.

As used in embodiments of the present invention, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

As used herein, the term "nominal" refers to a desired or target value, and a range of values above and/or below the desired value, of a characteristic or parameter set during a design phase of a production or process for a component or process operation. The range of values may be due to slight variations in manufacturing processes or tolerances. As used herein, the terms "about" and "left or right" indicate a value of a given quantity that may vary based on the particular technology node associated with the subject semiconductor device. The terms "about" and "left or right" may indicate a value of a given quantity, e.g., varying within 10% -30% of the value (e.g., ± 10%, ± 20%, or ± 30% of the value), based on the particular technology node.

It is noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Currently, flash memory is an important non-volatile memory, and one commonly used architecture is the NAND flash architecture. In a NAND flash architecture, two or more memory cells are coupled together in a source-to-drain manner into a string; wherein, the plurality of sources form a Common Source Array (ACS); the existing ACS is usually formed by using tungsten filling, and during the formation process, various process problems such as wafer warpage and slip, lithography deformation, stack dislocation and the like are caused due to severe pressure, which finally results in the performance degradation of the device. As the applicant's research on this technology has found, the ACS may also be implemented using doped polysilicon, or a combination of polysilicon and tungsten. The applicant further found that, in the ACS processing process, the wafer often has a warpage form not the traditional bowl-shaped warpage as shown in fig. 1, nor the convex warpage as shown in fig. 2, but the saddle-shaped warpage as shown in fig. 3, or even the U-shaped warpage, wherein, in the ACS processing process, the warpage plays a decisive factor in the warpage, the stress variation generated in the ACS processing process can bring about the stress variation, and the ACS processing process includes etching of ACS trenches, deposition of polysilicon in ACS trenches, and besides, deposition of metal tungsten in ACS shallow trenches, deposition of polysilicon in ACS shallow trenches, deposition of tungsten on polysilicon in ACS shallow trenches, and the like. Wherein, the etching of the ACS groove comprises the following steps: forming a graphical hard mask layer on the surfaces of the dielectric layer and the stacking structure, wherein the graphical hard mask layer defines the position and the size of the ACS groove; and sequentially etching the stacked structure to a semiconductor substrate by taking the graphical hard mask layer as a mask to form the ACS groove. In fig. 1-3, the substrate area is defaulted below the wafer in the figures, as viewed from the perspective of the figures.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Example 1:

embodiment 1 of the present invention provides a method for improving process stability in production, as shown in fig. 4, the method is implemented after polysilicon is filled in a common source trench (also referred to as an ACS trench in an embodiment of the present invention) of a three-dimensional memory, and the method includes:

in step 101, a warp value of the wafer is detected.

In the embodiment of the present invention, the warpage value of the wafer is a description manner, and in a specific implementation, there may be multiple expression manners, for example, as shown in fig. 1to fig. 3, the warpage value may be expressed as a color value in a manner of color mapping (based on the reason that the drawing of the specification does not carry color, and is not expressed in a color form, if the color form indicates the warpage magnitude degree by the vividness of color); the method can also be presented in an array mode corresponding to different partitions of the wafer, wherein numerical values corresponding to array positions are corresponding warping values (the size of the partition can be determined according to research precision of the warping values, and the size of the partition can be set according to an empirical warping curve); the maximum value of the warpage in the coordinate direction can be also specified as a warpage value for representing the warpage degree of the wafer.

In the embodiment of the present invention, for simplicity and clarity of description, the maximum value of the warpage in the coordinate direction is specified as a representation form of the warpage value of the wafer described in the subsequent scheme of the embodiment of the present invention. However, through the above description, those skilled in the art can implement the presentation of the warpage value of other wafers as equivalent alternative representation forms without creative work in combination with the contents of the subsequent embodiments of the present invention, and therefore, the solution formed by combining different warpage value representation forms of wafers falls within the protection scope of the present invention.

In step 102, when it is determined that the warpage value belongs to the first interval, annealing is performed in an annealing mode of solidifying polysilicon.

In the embodiment of the invention, the first interval and the second interval can show different parameter values under the conditions of different wafer sizes with different sizes, wafers made of different materials, different process requirements (mainly aiming at the constraint degree of warping) and different chip structure processing scenes (for example, some chip structure processing scenes can relate to bonding between wafers, more chips can directly process structures on a single wafer, and the two limit requirements on warping are different); in the use process of the embodiment of the invention:

the first interval is mainly defined as that if the warpage value of the wafer belongs to the first interval range, the warpage condition of the wafer is considered to belong to the allowable range of the actual processing technology, so that the annealing mode of solidifying the polysilicon can be directly adopted for annealing.

The second region corresponding to the first region is mainly used to limit the warpage value of the wafer within the compensation range of the method provided by the embodiment of the invention, and the annealing can be performed according to the specific annealing mode for adjusting the stress of the polysilicon. However, the applicant finds several factors mainly influencing the warpage in the research process, establishes a forward or reverse correlation between the factors, and can derive specific annealing operation contents from the correlation, so that the warpage value of the annealed wafer by adopting the annealing mode of adjusting the stress of the polysilicon can fall into the first interval again, and the influence relationship is specifically described in the subsequent technical scheme of the invention.

In step 103, when it is determined that the warpage value belongs to the second interval, annealing is performed by adjusting the stress of the polysilicon.

In an embodiment of the present invention, empirical values are given for a set of first and second intervals, wherein the first interval comprises [ -50,0] um; the second interval includes [ -500, -50) um. Generally, for a wafer with a size of 12 inches (300 mm in diameter) or more, the first region is set to [ -50,0] um, and the warpage of the wafer is controlled within the first region, so as to meet the chip process requirement of general quality. Taking fig. 3 as an example, the effect of negative warpage (the warpage value belongs to the first section or the second section) on the Y-axis is shown.

If the second interval exceeds-500, the warpage of the wafer is determined to be beyond the warpage range which can be compensated by the scheme of the invention; accordingly, either the material is discarded or a more complicated or expensive adjustment method (e.g., improved by providing a stress film) may be used, which is not considered to be within the scope of the present invention and will not be described herein.

Through theoretical derivation and sufficient experimental demonstration, the reason for the saddle-shaped warping structure of the wafer in the prior art is found to be: referring to a saddle-shaped warpage diagram in the prior art, as shown in fig. 3, a certain degree of warpage in the X axis direction is usually formed before the ACS is fabricated, and during the particular ACS fabrication process, a saddle-shaped warpage structure is formed due to warpage in the Y axis direction (a warpage which is concave in the Y axis direction as shown in fig. 3, i.e., a negative warpage as described in the embodiment of the present invention). In the embodiments of the present invention, the warpage in the Y axis is described as a positive warpage in the Y axis or a negative warpage in the Y axis by referring to whether the warpage direction is directed to the positive direction or the negative direction in the Z axis, and the absolute value of the warpage value is determined by the magnitude of the warpage.

The convex warpage is caused by the fact that in the prior art, processing and manufacturing of storage area channel holes are usually completed before ACS manufacturing, and the arrangement of the channel holes on a chip and the array formed on a wafer are accordingly enabled to enable the middle area of the wafer to be easily warped along the X axis direction, and the warpage protruding direction points to the positive direction of the Z axis. In the prior art, for bowl-shaped and convex warping, improvement by using a mask mode is a relatively mature technology, however, in the prior art, the research and solution for saddle-shaped warping are not numerous, and the reason for the formation of the warping is that the warping belongs to two nodes (respectively channel hole making and ACS making) in the processing technology, so that if the two processes are divided, masks are respectively made on the channel hole making node and the ACS making node, the processing material cost and the processing period cost are further increased; if only one set of mask is designed before the channel hole is manufactured, it is difficult to satisfy the comprehensive stress supplement in the processing process of two nodes, and the problem of overcompensation generated on the processing nodes of the channel hole is solved. The reason for this is that the warp in the X-axis direction and the warp in the Y-axis direction are different in process node, and a set of masks is designed to compensate the warp in advance, so that when the warp in the X-axis direction is compensated in advance, an unnecessary compensation result is formed in the Y-axis direction, which affects the subsequent ACS manufacturing process.

The scheme provided by the embodiment of the invention is a feasible and effective solution obtained after a plurality of test experiments by the inventor. The method combines the annealing characteristics of the polycrystalline silicon, and a set of perfect annealing strategy is designed for the annealing characteristics, so that the capability of the method for improving the warping condition in the wafer processing process is fully exerted. Particularly, the saddle-shaped warpage can be effectively improved.

In the embodiment of the present invention, the annealing method for solidifying polysilicon is specifically implemented as follows: the temperature on the initial annealing time node and the temperature on the finish annealing time node are both larger than or equal to 900 ℃, and the annealing time is controlled to be 5-10 s. Research shows that the polycrystalline silicon is annealed at the temperature of over 900 ℃ and fixed, the polycrystalline silicon can be considered as physical change, high temperature of several seconds is directly applied, the polycrystalline silicon is not melted and recrystallized, partial chemical bonds are broken before the polycrystalline silicon is melted, the annealing time of several seconds only breaks some chemical bonds which are not strong enough, namely the chemical bonds near gaps, and the breaking of the chemical bonds macroscopically means that the polycrystalline silicon is solidified.

When the annealing method for solidifying the polysilicon is specifically implemented in the embodiment of the present invention, an annealing temperature of greater than or equal to 900 ℃ is a basic condition, and further, from the consideration of stability of the whole wafer in the annealing process, that is, characteristics of other formed structural components (including channel holes, dielectric layers of storage regions, and the like) are not affected or damaged in the annealing process, and an upper limit of the annealing temperature in the annealing method for solidifying the polysilicon is also limited. Therefore, there is also an extended implementation in combination with the embodiments of the present invention, in which the annealing temperature and time control curve in the annealing mode for solidifying polysilicon is a peak curve, as shown in fig. 5, wherein the starting point of the peak curve corresponding to the annealing starting temperature is 900 ℃, the maximum temperature of the corresponding peak curve is 1100 ℃, and the annealing end point temperature is 900 ℃. The maximum temperature of 1100 c is controlled here so as not to damage or affect the structure that has been formed historically.

After the principle introduction of the annealing mode for curing the polysilicon stress is carried out and the related expansion of the characteristics is added in combination with the complex situation during the specific implementation, the specific implementation explanation under different scenes and different factors under consideration is carried out by taking the annealing mode for adjusting the polysilicon stress as a research focus.

The most common conditions for adjusting the annealing mode of polysilicon stress include controlling the annealing temperature at 600-900 ℃ and the annealing time at 5-60 min. An annealing temperature-time curve in an annealing manner for adjusting the stress of polysilicon is shown in fig. 6, wherein the annealing temperature is set to 700 ℃ and the annealing time is set to 5-60 min. Wherein, the specific annealing time can be comprehensively set according to the severity of the actual warping and the time length reserved for annealing in the production line.

As mentioned above, controlling the annealing temperature at 600-:

in step 1031, the ratio of the crystal grains in the polycrystalline silicon converted to have the (100) crystal orientation to the crystal grains in the polycrystalline silicon converted to have the (110) crystal orientation is determined according to the warpage value.

In step 1032, the annealing process is controlledModerate annealing temperature 625+Annealing time and annealing temperature 675 of 5 deg.C+The annealing time is 5 ℃. Wherein, temperature 625+5 ℃ is the annealing temperature corresponding to the formation of the (100) crystal orientation, temperature 675+5 ℃ is the annealing temperature corresponding to the formation of the (110) crystal orientation.

Since the annealing temperature of the (110) crystal orientation is higher than that of the (100) crystal orientation, the preferred implementation is to advance the annealing process of the annealing temperature of the (110) crystal orientation and then perform the annealing process of the (100) crystal orientation.

As shown in fig. 8, a possible annealing manner for adjusting the stress of the polysilicon is given, in which the annealing time allocation of 625 ℃ corresponding to the annealing temperature of the (100) crystal orientation and 675 ℃ corresponding to the annealing temperature of the (110) crystal orientation is 1: 1, it is considered that the crystal grains of (100) crystal orientation and the crystal grains of (110) crystal orientation obtained by conversion are similar in amount. The principle of the above-described improvement of the annealing method for adjusting the stress of polycrystalline silicon is that the interplanar spacing of the (110) crystal orientation in polycrystalline silicon is larger than the interplanar spacing of the (100) crystal orientation, and therefore, the amount of each transformation can be controlled by allocating the time ratio of the temperatures prevailing for the crystal grain formation of the two crystal orientations, and the adjustment of the warpage value can be controlled on a macro level. The solution formed by steps 1031-1032 is particularly suitable for the situation where the first interval is very small (i.e. higher adjustment accuracy is required), and the detected warpage value of the wafer is very close to the boundary value of the first interval. After the factors influencing the determination of the annealing ratio are analyzed next, the deeper implementation significance of the scheme formed by steps 1031-1032 will be further explained.

The inventor confirms far more than one wafer warpage value influencing the adjustment of the warpage value through experimental and theoretical derivation, so that the determination of the annealing proportion also relates to the determination of the annealing proportion by combining the distribution characteristic of the common source trench on the wafer and the structural characteristic of the polysilicon under a further severe application scene;

the distribution characteristics of the common source trenches on the wafer comprise one or more of the total number of the common source trenches on the wafer, the average length of the common source trenches on the wafer, and the distribution parameters of the common source trenches on the wafer; moreover, the distribution characteristics of the common-source trenches on the wafer are usually the number and the layout mode of chips manufactured through the layout required on the wafer, and each chip corresponds to the number, the length and the position of the common-source trenches according to the design structure of the chip, so that the number, the length and the distribution parameters of the common-source trenches are finally embodied. The relation is that if the number and the length of the common source grooves are larger, the effect of adjusting the wafer warpage in the same polysilicon stress annealing mode is more obvious; the distribution parameters show that the higher the consistency of the chip layouts on the wafer, the more obvious the effect of adjusting the wafer warpage in the same polysilicon stress annealing manner, and here, as a comparative example, if a similar irregular layout manner is adopted when actually designing the chip layout structure on the wafer, and the layout manner of the chips is intentionally designed to have a common source array orientation diversity (as the solution proposed in patent CN 109065536 a), the effect of adjusting the wafer warpage in the same polysilicon stress annealing manner is weakened.

Wherein the structural characteristics of the polysilicon include the width and depth of the polysilicon in the common source trench. In a specific implementation, the trench etched in the ACS and used for depositing the polysilicon has a strip layout, and the depth of the trench is generally related to the number of stacked layers of the three-dimensional memory, and generally, the higher the number of stacked layers, the deeper the depth of the common source trench is; as shown in fig. 9, in a structural representation of a common source array in a certain chip structure, the common source array 305 shown in fig. 9 can be considered as a structural effect schematic diagram after polysilicon deposition (or polysilicon and tungsten combined deposition) is completed in a common source trench, wherein a symbolic memory string 201 structure is also labeled in fig. 9.

Returning to the first and second regions listed in the embodiments of the present invention as an example, taking a 12-inch wafer as an example, the distribution parameters of the common source array fabricated on the wafer show that the distribution density in the Y direction is about 90 ten thousand, and the layout structure of each chip on the wafer has high uniformity (i.e., regular arrangement). The annealing method for adjusting the stress of the polysilicon by setting the time proportioning method is specifically embodied as follows: the first interval is [ -30,0] um, and the second interval is [ -80, -30) um, then the executing the obtained polysilicon annealing strategy on the currently processed wafer specifically includes: if the warpage value is less than [ -80, -50] um, directly using 625 ℃ for annealing treatment; if the warping value is between-50 and-30 um, then annealing treatment is carried out at 625 ℃ and 675 ℃ according to a first preset time ratio. Experiments prove that the implementation mode can recover the warpage value of the wafer to be within the first interval range.

It should be noted that, in the embodiment of the present invention, the annealing manner for adjusting the polysilicon stress including at least two annealing temperatures is proposed, and also in consideration of a specific industrial implementation requirement (i.e. the solution formed by steps 1031-1032 mentioned above has a deeper implementation meaning):

generally, the influence on the whole production line is considered when the adjustment is made in the processing technology, so that certain uniformity needs to be achieved for controlling the time length of each processing node, and the connection of the front and rear working procedures can be effectively guaranteed. Corresponding requirements also exist on the annealing mode of the invention, and the proposed annealing mode for adjusting the stress of the polycrystalline silicon adopts multi-stage annealing temperatures and carries out time proportioning setting, so as to ensure that the effective warpage adjustment can be completed through the set annealing time under the situation of different warpage of wafers. The effective warpage adjustment described herein is particularly specific to ensure that if the warpage value of the initial wafer is-60 um, the effective warpage adjustment is increased to ensure that the warpage value is not adjusted too much to jump to a value greater than zero, i.e. to ensure that the warpage value returns to the first interval, which is considered from the viewpoint of process stability, because if the [ -50,0] um in the first interval is restored to meet the subsequent process requirement, the excessive adjustment of the warpage value to a positive value will cause unnecessary additional stress burden and even damage to the historically processed device. In consideration of the above problem, when an annealing manner for adjusting the stress of the polysilicon is specifically implemented, the annealing times corresponding to the annealing temperature 625 ℃ in the (100) crystal orientation and the annealing temperature 675 ℃ in the (110) crystal orientation can be adjusted according to empirical distribution by using the above differentiated distribution characteristics, so that the adjustment of the wafer warpage can be implemented in the above finer range.

In an embodiment of the present invention, before detecting the warpage value of the wafer, the method may further include: and doping the polysilicon. The doping process is typically performed using either n-type or p-type dopants. Of course, the doping process may also be performed before the annealing for adjusting the polysilicon stress or the annealing for consolidating the polysilicon structure according to the embodiment of the present invention. However, it should be emphasized that the doping of the polysilicon also causes a change in the stress of the wafer, and therefore, in an implementation of the embodiment of the present invention, it is preferable to perform the doping of the polysilicon before detecting the warpage value of the wafer.

As a three-dimensional memory processing procedure, it has been described above that the fabrication of the memory string is usually completed before the ACS is fabricated by depositing the polysilicon, and therefore, in the embodiment of the present invention, a procedure after the annealing operation for the polysilicon is completed is further described, so as to define the process nodes in the whole three-dimensional memory processing procedure more clearly, and therefore, after the step 103 is performed, the method further includes:

manufacturing a contact part on the polycrystalline silicon; or depositing metal tungsten on the polysilicon, and then manufacturing a contact part on the metal tungsten. The contact part is generally processed on the insulating layer through an etching process, and the insulating layer is arranged on the upper surface of the common source array and the stacking region.

Example 2:

embodiment 1 introduces a method for improving process stability during production, which is based on utilizing real-time wafer warpage detection during actual wafer processing to produce a three-dimensional memory (3D NAND), and making a next annealing method for consolidating a polysilicon structure or adjusting polysilicon stress. However, it is clear from the development analysis in the specific implementation manner in embodiment 1 that factors affecting the warpage are complex and various, and there is no unique relational expression in the prior art to establish the correspondence between the warpage value and the two annealing manners when the two annealing manners are specifically implemented, and more, the operation is performed by virtue of practical experience accumulated in the production period, because the number of processed wafers corresponding to one three-dimensional memory is thousands of, and a set of processing technology cannot be changed or adjusted at will, this also provides a guarantee for the popularization and the solution of embodiment 1. Also under such objective environment, embodiment 2 of the present invention provides an implementation scheme that is more efficiently applied to the production process based on the core idea of the present invention. Different from the embodiment 1, the embodiment of the present invention identifies the processing technology of the specific three-dimensional memory, counts the historical wafer warpage generated in the ACS processing process and the adjustment results set by various specific adjustment parameters in the annealing mode for adjusting the polysilicon stress, counts a set of control parameters for achieving the expected effect or the optimal effect of the improvement effect, establishes a mapping relationship with the identifier, and stores the mapping relationship in the server or the local storage area, so that when the processing technology of the specific three-dimensional memory is performed subsequently, the corresponding control parameters can be directly called to complete the annealing mode for adjusting the polysilicon stress according to the mapping relationship between the identifier and the control parameters. As shown in fig. 10, the method is implemented after polysilicon is filled in a common source trench of a three-dimensional memory, and the method according to the embodiment of the present invention includes:

in step 101', the type of the current wafer processing process is determined, and a corresponding polysilicon annealing strategy is obtained according to the type of the current wafer processing process. The machining process type can be understood as the machining and manufacturing process of the three-dimensional memory with any structure, and the unique identification is calibrated, so that the production line can be ensured to adjust the control parameters of each link on the machining production line according to the machining process type, and the three-dimensional memory corresponding to the machining process type is machined and manufactured.

The polysilicon annealing strategy comprises an annealing mode for solidifying the polysilicon and/or an annealing mode for adjusting the stress of the polysilicon. The method comprises the steps of determining the processing technology type of a current wafer, and acquiring a corresponding polycrystalline silicon annealing strategy according to the processing technology type, wherein the step is specifically shown in the step that a servo control system for wafer processing acquires the polycrystalline silicon annealing strategy corresponding to the wafer from a local storage area or a server side according to the processing technology type; wherein, the polysilicon annealing strategy comprises the content of related annealing control parameters. In actual operation, the local storage area or the server side stores the mapping relation of the annealing strategies corresponding to a plurality of processing technology types, and the mapping relation is obtained through statistical analysis of a historical test process.

In step 102', the acquired polysilicon annealing strategy is performed on the currently processed wafer.

Wherein the executing the obtained polysilicon annealing strategy comprises: annealing by adopting an annealing mode of solidifying the polycrystalline silicon; or, annealing by adopting an annealing mode of adjusting the stress of the polysilicon; or, annealing is carried out by adopting an annealing mode of adjusting the stress of the polysilicon firstly, and then annealing is carried out by adopting an annealing mode of solidifying the polysilicon.

The embodiment of the present invention can also achieve the advantageous effects described in embodiment 1: the method combines the annealing characteristics of the polycrystalline silicon, and a set of perfect annealing strategy is designed for the annealing characteristics, so that the capability of the method for improving the warping condition in the wafer processing process is fully exerted. Particularly, the saddle-shaped warpage can be effectively improved. The production efficiency of the wafer processing process can be improved, and in the embodiment of the present invention, it is not necessary to detect the warpage value (various warpage value calculation methods are proposed in the prior art, for example, in patent CN107478171A, real-time wafer warpage condition detection is realized by raman spectroscopy), as any detection method will inevitably increase the wafer processing production cycle. In practical cases, the relationship between annealing and warpage is affected by many factors, so that the corresponding relationship of formula level cannot be established, therefore, as shown in embodiment 1, determining an annealing strategy by detecting the warpage of a wafer in real time brings a lower cost performance than the solution of embodiment 2, and embodiment 2 describes that a specific annealing strategy is directly implanted into the processing process flow of a specific wafer as a curing process step by virtue of test experiments and manufacturing experiences.

Based on the comparative analysis, in the embodiment of the present invention, the annealing strategy is obtained according to wafer statistics of historical processing, and when the annealing strategy is implemented after polysilicon is filled in a common source trench of a three-dimensional memory, the annealing strategy may be directly executed according to an annealing strategy determined by the history, as shown in fig. 11, the statistical process includes:

in step 201', the type of the wafer processing process is determined, and the warpage value of the wafer is detected.

In a specific implementation, the warpage value of the wafer can be represented in various manners, such as shown in fig. 1-3, in a manner of color mapping warpage degree (based on the description, the reason why the drawings do not carry color is not represented in a color form); the warping value can be displayed in an array mode corresponding to different partitions of the wafer, wherein the numerical value corresponding to the array position is the corresponding warping value; the maximum value of the warpage in the coordinate direction can be also specified as a warpage value for representing the warpage degree of the wafer.

In the embodiment of the present invention, for simplicity and clarity of implementation, the maximum value of the warpage in the coordinate direction is specified as a representation form of the warpage value of the wafer described in the subsequent scheme of the embodiment of the present invention. However, through the above description, those skilled in the art can implement the presentation of the warpage value of other wafers as equivalent alternative representation forms without creative work in combination with the contents of the subsequent embodiments of the present invention, and therefore, the solution formed by combining different warpage value representation forms of wafers falls within the protection scope of the present invention.

In step 202', when it is determined that the warpage value belongs to the second interval, annealing is performed by using one or more preset annealing control parameters for adjusting the stress of the polysilicon. The preset one or more annealing control parameters for adjusting the polysilicon stress may be set empirically, may be derived theoretically, or may be set tentatively, and is not limited herein.

In an embodiment of the present invention, empirical values are given for a set of first and second intervals, wherein the first interval comprises [ -50,0] um; the second interval includes [ -500, -50) um. Generally, for a wafer with a size of more than 12 inches, the first region is set to [ -50,0] um, and the warpage of the wafer is controlled within the first region, so that the requirement of chip process with general quality can be satisfied.

If the second interval exceeds-500, the wafer is determined to be out of the warpage range which can be compensated by the scheme of the invention; accordingly, either the scrapping or the use of more complicated or more expensive adjustment methods that may exist are not described in detail herein since the latter are not considered to be within the scope of the present invention.

In step 203', it is determined that the wafer warpage value after annealing by the control parameter for adjusting the polysilicon stress belongs to the first interval, and the annealing control parameter for adjusting the polysilicon stress correspondingly is used as the annealing mode for adjusting the polysilicon stress corresponding to the type of the processing technology. Then, in actual operation, when the same process type is encountered, the corresponding annealing strategy is the annealing manner for adjusting the polysilicon stress determined in step 203'. In the actual operation process, if there is a set of annealing control parameters for adjusting the polysilicon stress (the number of specific cases is not limited to one set), which may finally satisfy the condition of step 203', the set of annealing control parameters for adjusting the polysilicon stress is used as the annealing mode for adjusting the polysilicon stress corresponding to the type of the processing process.

The annealing strategy is obtained according to the wafer statistics of the historical processing, and the annealing strategy corresponding to a certain processing technology type may be an annealing mode for solidifying the polysilicon. The annealing strategy of each processing technology type is determined according to the respective actual statistical result, and is not described herein again.

If the result is determined to fall into the first interval, the corresponding test result is recorded as an effective warping compensation process realized by using the method provided by the embodiment of the invention. And preferably, after sufficient experimental tests, one or more types of chips to be processed and manufactured, which have high probability that the warpage value falls into the second interval on the ACS processing node, can be determined, and an annealing control mode (i.e., an annealing mode for correspondingly adjusting the stress of the polysilicon) with the optimal warpage compensation success rate and/or warpage compensation effect is set for the chip type according to the statistical result.

In step 203', if it is determined that the wafer does not fall into the first region, the wafer warpage after annealing is fed back to the system as a basis for modifying and adjusting the annealing control parameter of the polysilicon stress. Wherein, the control parameters in the annealing mode for modifying and adjusting the stress of the polysilicon comprise: adjusting the annealing temperature 625 corresponding to the (100) crystal orientation during annealing+Annealing temperature 675 at 5 ℃ and corresponding to the (110) crystal orientation+The annealing time distribution ratio was 5 ℃.

As in embodiment 1, in the embodiment of the present invention, the first interval and the second interval may show different parameter values in different wafer sizes, wafers made of different materials, different process requirements, and different chip structure processing scenarios; in the use process of the embodiment of the invention:

the first interval is mainly used for limiting, and if the warpage value of the wafer belongs to the range of the first interval, the warpage condition of the wafer is considered to belong to the allowable range of the actual processing technology, so that the annealing mode of solidifying the polycrystalline silicon can be directly adopted for annealing.

And the second interval corresponding to the first interval is mainly used for limiting the warpage value of the wafer within a compensation range and can carry out annealing according to the deduced annealing mode for adjusting the stress of the polysilicon. However, the applicant finds several factors mainly influencing the warpage in the research process, establishes a forward or reverse correlation relationship between the factors, and can deduce specific annealing operation content from the forward or reverse correlation relationship, so that the warpage value of the wafer annealed by the annealing method for adjusting the stress of the polysilicon can meet the requirement of falling into the first interval again, and the influence relationship is specifically described in the subsequent technical scheme of the invention.

In the embodiment of the present invention, the related specific implementation contents of the annealing manner for curing the polysilicon and the annealing manner for adjusting the stress of the polysilicon and the improvement scheme based on the specific application scenario requirements can refer to the description related to embodiment 1, and are not described herein again.

However, in the embodiment of the present invention, a method for implementing how to determine the annealing time allocation in step 1032 in embodiment 1 is also added. The following processes are all based on a large number of test experiments to achieve statistical completion of data.

Firstly, a very clear problem scene is given, and for the specific wafer processing, the wafer processing is under the objective constraint conditions of the warpage value generated in the ACS processing process, the correspondingly set first interval and the set annealing time length. When single (110) crystal orientation conversion exists, the wafer warpage value jumps from a negative warpage value of a Y axis to a positive warpage value of the Y axis (or jumps from the positive warpage value to the negative warpage value), and the single (100) crystal orientation conversion cannot enable the annealed wafer warpage to fall into a first interval; further, according to the above analysis, the annealing time is not easily adjusted due to the design of the production line, and in this case, it is effective to provide the annealing temperature for the (110) crystal orientation conversion and the annealing temperature for the (100) crystal orientation conversion with an appropriate distribution of the annealing time.

In the specific implementation, the magnitude of the change of the generated warping value can be counted respectively in the annealing process of single (110) crystal orientation conversion and the annealing process of single (100) crystal orientation conversion, and the change is used as a reference factor for the distribution of the annealing time, so that a more reasonable distribution parameter can be obtained.

Example 3:

in the embodiment of the present invention, a more typical wafer processing process is used to describe the specific implementation of the embodiment 1 or the embodiment 2 of the present invention in combination with a corresponding wafer processing process.

Fig. 12 to 20 are schematic structural diagrams illustrating a process of forming a 3D NAND detection structure according to an embodiment of the invention.

Referring to fig. 12, a semiconductor substrate 100 is provided, a stacked structure 200 and a dielectric layer 110 surrounding the stacked structure 200 are formed on a surface of the semiconductor substrate 100, the stacked structure 200 is formed by stacking a sacrificial layer 2002 and an isolation layer 2001, and includes a core region 220 and a step region 210 surrounding the core region 220, and the dielectric layer 110 covers the stacked structure 200.

The stack structure 200 also has a memory string 201 extending through the core region 220 to the semiconductor substrate 100.

The semiconductor substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like; the semiconductor substrate 100 may be selected according to actual requirements of the device, and is not limited herein. In this embodiment, the semiconductor substrate 100 is a single crystal silicon wafer.

The sacrificial layer 2002 and the isolation layer 2001 are composed of different materials. In some embodiments, the material of the sacrificial layer 2002 and the isolation layer 2001 may be one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the sacrificial layer 2002 of the stacked structure 200 is made of silicon nitride, and the isolation layer 2001 is made of silicon oxide. The memory string 201 comprises a substrate epitaxial layer 2011 formed at the bottom of a channel hole and a channel material layer 2012 located in the channel hole, wherein the channel material layer 2012 comprises a functional side wall, a polycrystalline silicon layer covering the surface of the functional side wall and a channel medium layer located on the surface of the polycrystalline silicon layer and filled in the channel hole. The functional sidewall comprises a blocking layer, a charge trapping layer and a tunneling layer which are stacked in sequence, and in the specific embodiment, the functional sidewall is of a composite layer structure of O-N-O (silicon oxide-silicon nitride-silicon oxide).

In this embodiment, the stacked structure 200 includes two sub-stacked structures, namely a bottom stacked structure 200a and an upper stacked structure 200b, and the bottom stacked structure 200a is separated from the upper stacked structure 200b by a dielectric layer 110; the storage string 201 includes a bottom storage string located in the bottom stacked structure 200a and an upper storage string located in the upper stacked structure 200 b. The overall height of the stacked structure 200 can be increased by forming a plurality of sub-stacked structures, thereby increasing the density of the memory cells.

Specifically, in this embodiment, the method for forming the stacked structure 200 and the dielectric layer 110 includes sequentially stacking a sacrificial layer 2002 and an isolation layer 2001 on the surface of the semiconductor substrate 100, and then etching edge regions of the sacrificial layer 2002 and the isolation layer 2001 into a step shape to form a bottom stacked structure 200 a; then depositing a bottom dielectric layer to cover the bottom stacked structure 200a and flattening; forming a bottom storage string in the bottom stacked structure 200 a; and after covering an isolation medium layer on the surface of the bottom storage string, forming an upper-layer stacked structure 200b on the surface of the isolation medium layer by the same method, forming an upper-layer medium layer covering the upper-layer stacked structure 200b and an upper-layer storage string penetrating through the stacked structure 200b and connected with the bottom storage string, wherein the bottom storage string and the upper-layer storage string integrally form a storage string 201. The bottom dielectric layer, the isolation dielectric layer and the upper dielectric layer are integrally formed as a dielectric layer 110.

In other embodiments of the present invention, the stack structure 200 may also include only one sub-stack structure or more than three sub-stack structures.

Referring to fig. 13, an insulating pillar 202 is formed through the dielectric layer 110 and the step region 210 to the semiconductor substrate 100. The method for forming the insulating column 202 comprises the following steps: etching the dielectric layer 110 and the stepped region 210 to the surface of the semiconductor substrate 100 to form a pseudo through hole; and filling an insulating medium material in the dummy through hole, and flattening to form an insulating column 202 positioned in the dummy through hole. The insulating pillars 202 can support the isolation layer 2001 during the subsequent removal of the sacrificial layer 2002.

In this embodiment, the insulating column 202 is made of silicon oxide. Due to the fact that the height of the stacked structure 200 is high, the depth of the formed dummy through hole is large, and in order to improve the filling quality of the insulating dielectric material in the dummy through hole, an atomic layer deposition process can be adopted to fill the insulating dielectric material in the dummy through hole.

Referring to fig. 14, a common source trench 203 is formed through the core region 220 to the surface of the semiconductor substrate 100. Specifically, the method for forming the common source trench 203 includes: forming a graphical hard mask layer on the surfaces of the dielectric layer and the stacked structure, wherein the graphical hard mask layer defines the position and the size of the common source trench 203; and sequentially etching the stacked structure 200 to a semiconductor substrate by taking the patterned hard mask layer as a mask to form the common source trench 203.

Referring to fig. 15, the sacrificial layer 2002 is removed along the common source trench 203, and an opening 204 is formed between the isolation layers 2001. The sacrificial layer 2002 may be removed by a wet etching process, and specifically, an etching solution used in the wet etching process may be a hot phosphoric acid solution.

Referring to fig. 16, a source doped region 205 is formed in the semiconductor substrate 100 at the bottom of the common source trench 203; and forming an oxide layer 206 on the surface of the semiconductor substrate 100 at the bottom of the common source trench 203.

And performing ion implantation on the bottom of the common source trench 203 to form a source doped region 205. The ion implantation uses N-type doping ions such As P or As.

After the source doped region 205 is formed, the surface of the semiconductor substrate 100 at the bottom of the common source trench 203 is oxidized to form an oxide layer 206. The oxidation treatment may be an in-situ water vapor generation process or an oxidation process such as thermal oxidation. The oxide layer 206 serves as a spacer between a common source formed subsequently in the common source trench 203 and the source dopant region 205.

Referring to fig. 17, a gate material is deposited on the inner wall surfaces of the opening 204 and the common-source trench 203, a control gate 301 is formed in the opening 204, and a gate material layer 302 is formed on the inner wall surface of the common-source trench 203.

In this embodiment, the gate material is W, and an atomic layer deposition process may be used to deposit the gate material, so as to ensure that the control gate 301 in the opening 204 has high deposition quality and avoid the problems of voids in the control gate 301. In other embodiments, the gate material may also be polysilicon, Al, Cu, Co, Ag, metal silicide, or other conductive materials.

The control gate 301 and the isolation layer 2001 are alternately stacked to form a memory stack structure, which includes a bottom memory stack structure 200c and an upper memory stack structure 200 d.

Before depositing the gate material, a TiN adhesion layer may be deposited on the surface of the opening 204 and the inner wall of the common-source trench 203 to improve adhesion between the subsequent gate material and the inner wall of the opening 204 and the inner wall of the common-source trench 203.

The gate material layer 302 covers the surface of the inner wall of the common source trench 203 and the surface of the dielectric layer 110.

Referring to fig. 18, the gate material layer 302 on the bottom surface of the common source trench 203 is removed by etching, and a conductive sidewall 303 covering the sidewall of the common source trench 203 is formed.

Since the thickness of the gate material layer 302 on the surface of the inner wall of the common source trench 203 is small, in order to remove the bottom gate material layer 302 and simultaneously retain the conductive sidewall 303 on the sidewall, in this embodiment, the gate material layer 302 is etched by sequentially using a wet etching process and a dry etching process.

Firstly, a wet etching process is adopted to etch the gate material layer on the surface of the inner wall of the common source trench 203, and because the wet etching process has isotropy, the gate material layer avoided on the side wall and the bottom of the common source trench 203 is simultaneously etched, so that the thickness of the gate material layer 302 is reduced. The temperature of the wet etching process is 20-200 ℃, a mixed solution of phosphoric acid, nitric acid, acetic acid and deionized water is used as an etching solution, and the etching amount of the gate material layer 302 is adjusted by controlling the etching time.

And then, etching the gate material at the bottom of the common source trench 203 by using an anisotropic dry etching process, further removing the gate material layer remaining at the bottom of the common source trench 203, and exposing the oxide layer 206 at the bottom of the common source trench 203. The plasma etching process of the dry etching process has the process temperature of 100-400 ℃, the etching gas of Cl2 and the pressure of an etching cavity of 0.1-10 Torr.

During the etching process, the thickness of the gate material layer covering the surface of the dielectric layer 110 is also decreased.

In this specific embodiment, the gate material is low-fluorine tungsten, and in order to further improve the conductivity of the control gate 301 and the conductive sidewall 303, between the wet etching step and the dry etching step, the gate material layer 302 is further subjected to a degassing treatment to remove F in the gate material. The degassing treatment is carried out at the temperature of 500-1000 ℃ for 5-30 min.

The conductive side walls 303 are connected with the control gates 301 of each layer, and the control gates 301 of each layer are in short circuit connection with the conductive side walls 303, so that all the control gates 301 are in short circuit.

In order to ensure that the conductive side walls 303 can form stable short-circuit connection with the control gates 301 and ensure that the control gates 301 are short-circuited, the thickness of the conductive side walls 303 cannot be too small; meanwhile, the thickness of the conductive sidewall 303 cannot be too large, so as to avoid difficulty in filling the source electrode in the common source trench 203 subsequently. In a specific embodiment of the present invention, the thickness of the conductive sidewall 303 ranges from 5nm to 50 nm.

Referring to fig. 19, an insulating spacer 304 is formed on the surface of the conductive spacer 303, and a common source 305 filling (i.e., the polysilicon deposition process in embodiment 1 or embodiment 2) the common source trench 203 is filled with the common source 305 (in the embodiment of the present invention, an implementation scheme of filling the ACS with only polysilicon is adopted, but a skilled person can also realize the common source by filling a part of polysilicon and then filling tungsten on the polysilicon, which is not described herein again).

The insulating side wall 304 is made of dielectric materials such as silicon oxide, silicon oxynitride, hafnium oxide, and the like. After forming a side wall material layer on the inner surface of the common source trench 203 and the surface of the gate material layer on the surface of the dielectric layer 110, removing the side wall material on the upper side of the dielectric layer 110 and the bottom of the common source trench 203 by using a side wall etching process to form an insulating side wall 304 covering the surface of the conductive side wall 303; then, the common source trench 203 is filled with a source material (i.e., during the polysilicon deposition process in embodiment 1 or embodiment 2), and the dielectric layer 110 is used as a stop layer for planarization, so as to form the common source 305. The method steps of example 1 or example 2 are then performed to complete the compensation of wafer warpage.

Referring to fig. 20, a peripheral circuit (not shown) is formed on the surface of the semiconductor substrate 100 and located at the periphery of the stacked structure 200, and the peripheral circuit is covered by the dielectric layer 110. After the common source 305 is formed, a peripheral circuit conductive contact 401 is formed through the dielectric layer 110 to a peripheral circuit contact region and a control gate conductive contact 402 is formed through the dielectric layer 110 to the top control gate 301.

The method of forming the peripheral circuit conductive contact 401 and the control gate conductive contact 402 comprises: forming a patterned mask layer on the surface of the dielectric layer 110, wherein the patterned mask layer defines a first through hole in a peripheral area and a second through hole above the control gate 301; etching the dielectric layer 110 by taking the patterned mask layer as a mask, and simultaneously forming a first through hole and a second through hole; and filling a metal material into the first through hole and the second through hole, and flattening to form the peripheral circuit conductive contact 401 and the control gate conductive contact 402.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A method for improving process stability in production, wherein the method is implemented after polysilicon is filled in a common source trench of a three-dimensional memory, and the method comprises the following steps:

2. The method for improving in-process stability according to claim 1, wherein when determining the polysilicon annealing strategy according to the warpage value by detecting the warpage value of the wafer, the annealing strategy comprises:

3. The method for improving in-production process stability according to claim 1, wherein when the corresponding polysilicon annealing strategy is obtained according to the processing technology type by determining the processing technology type of the current wafer, the annealing strategy is obtained according to wafer statistics of historical processing, wherein the statistical process comprises:

and determining that the wafer warpage value after the control parameter for adjusting the polysilicon stress is annealed belongs to a first interval, and taking the annealing control parameter for correspondingly adjusting the polysilicon stress as an annealing mode for adjusting the polysilicon stress corresponding to the processing technology type.

4. A method for improving process stability in production according to any one of claims 1to 3, wherein the detecting the warpage value of the wafer specifically comprises:

5. The method for improving process stability in production according to any one of claims 1to 3, wherein the annealing mode for solidifying the polysilicon specifically comprises:

6. The method for improving in-process stability according to claim 5, wherein the annealing temperature and time control curve in the annealing mode for solidifying the polysilicon is a peak curve, wherein the starting point of the peak curve corresponding to the annealing starting temperature is 900 ℃, the maximum temperature of the corresponding peak curve is 1100 ℃, and the annealing end point temperature is 900 ℃.

7. The method for improving process stability in production according to any one of claims 1to 3, wherein the annealing manner for adjusting the stress of the polysilicon specifically comprises:

8. The method for improving process stability in production according to claim 7, wherein an annealing recipe is determined according to the warpage value, specifically:

determining the proportion of crystal grains with the crystal orientation converted into (100) in the polycrystalline silicon and crystal grains with the crystal orientation converted into (110) in the polycrystalline silicon according to the warping value, and controlling the proportion between the annealing time with the annealing temperature of 625 +/-5 ℃ and the annealing time with the annealing temperature of 675 +/-5 ℃ in the annealing process; wherein the temperature 625 + -5 deg.C is an annealing temperature corresponding to formation of a (100) crystal orientation, and the temperature 675 + -5 deg.C is an annealing temperature corresponding to formation of a (110) crystal orientation.

9. The method for improving process stability in production according to claim 8, wherein the determining an annealing recipe specifically further comprises:

10. The method of claim 8, wherein the first interval is [ -30,0] um and the second interval is [ -80, -30) um, and wherein the method further comprises:

11. The method for improving in-process stability of claim 1, wherein prior to detecting a warp value of the wafer, the method further comprises: and doping the polysilicon.