CN118099097B - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- CN118099097B CN118099097B CN202410458342.1A CN202410458342A CN118099097B CN 118099097 B CN118099097 B CN 118099097B CN 202410458342 A CN202410458342 A CN 202410458342A CN 118099097 B CN118099097 B CN 118099097B
- Authority
- CN
- China
- Prior art keywords
- layer
- work function
- region
- metal work
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 90
- 239000002184 metal Substances 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 230000009467 reduction Effects 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 39
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 15
- 239000001257 hydrogen Substances 0.000 claims description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 9
- 239000011261 inert gas Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 253
- 230000006870 function Effects 0.000 description 60
- 230000008569 process Effects 0.000 description 21
- 150000004767 nitrides Chemical class 0.000 description 18
- 238000002955 isolation Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- -1 argon Chemical compound 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 238000011946 reduction process Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 2
- 229910021324 titanium aluminide Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910010348 TiF3 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- VZVQQBDFMNEUHK-UHFFFAOYSA-N [La].[Hf] Chemical compound [La].[Hf] VZVQQBDFMNEUHK-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- OJCDKHXKHLJDOT-UHFFFAOYSA-N fluoro hypofluorite;silicon Chemical compound [Si].FOF OJCDKHXKHLJDOT-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate comprising a first region for forming a PMOS transistor and a second region for forming an NMOS transistor; forming a plurality of dummy gates on the substrate, the dummy gates being disposed on the first region and the second region, respectively; forming a dielectric layer on the substrate, wherein the surface of the dielectric layer is flush with the surface of the pseudo grid electrode; removing the pseudo grid electrode to form a concave part; sequentially forming a first metal work function layer and a second metal work function layer on the dielectric layer, the bottom and the side wall of the concave part; reducing the second metal work function layer on the second region to form a reduction layer; removing the reduction layer; a metal conductive layer is formed on the second metal work function layer of the first region and on the first metal work function layer of the second region. The manufacturing method of the semiconductor device provided by the invention can improve the stability and balance of the semiconductor device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of a semiconductor device.
Background
With the development of semiconductor technology, the technology nodes of semiconductor devices are continuously reduced, the sizes of the devices are continuously reduced according to moore's law, and various process difficulties caused by the approach of the semiconductor devices to physical limits are also continuously presented. In the field of semiconductor device fabrication, how to solve the increase of transistor leakage current and power consumption becomes a challenging problem. The high-dielectric gate dielectric material is used for replacing the traditional gate dielectric material, and meanwhile, the metal gate is used for replacing the polysilicon gate, so that the leakage current and the power consumption of the transistor can be effectively reduced, and the electrical property of the semiconductor device is optimized. However, when the types of transistors on the substrate are different, the work function layers of the metal gates are different, and in the manufacturing process, the work function layers at the interfaces between the transistors are deviated, so that threshold voltage drift is caused, and the yield of the semiconductor device is poor.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which can reduce the threshold voltage drift of the semiconductor device and improve the stability and balance of the semiconductor device so as to improve the yield of the semiconductor device.
In order to solve the technical problems, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, wherein the substrate comprises a first region for forming a PMOS transistor and a second region for forming an NMOS transistor;
Forming a plurality of dummy gates on the substrate, the plurality of dummy gates being disposed on the first region and the second region;
forming a dielectric layer on the substrate, wherein the surface of the dielectric layer is flush with the surface of the dummy gate;
removing the dummy gate to form a concave part;
Sequentially forming a first metal work function layer and a second metal work function layer on the dielectric layer, the bottom and the side wall of the concave part;
Reducing the second metal work function layer on the second region to form a reduction layer;
removing the reduction layer; and
A metal conductive layer is formed on the second metal work function layer of the first region and on the first metal work function layer of the second region.
In one embodiment of the present invention, the first metal work function layer comprises tantalum nitride and the second metal work function layer comprises titanium nitride.
In an embodiment of the present invention, the step of forming the reduction layer includes:
Forming a photoresist layer on the first region;
And placing the substrate with the photoresist layer into a plasma cavity, and introducing mixed gas of hydrogen and inert gas.
In an embodiment of the present invention, a total flow rate of the hydrogen gas and the inert gas is 20L/min to 40L/min, and a gas ratio of the hydrogen gas to the inert gas is, for example, 0.3:1 to 0.6:1.
In one embodiment of the present invention, the dc bias voltage of the plasma chamber is 40v to 60v.
In an embodiment of the present invention, the reducing layer is removed by wet etching, and the etching solution of the wet etching includes dilute hydrofluoric acid.
In an embodiment of the present invention, the dilute hydrofluoric acid is a hydrofluoric acid solution and water according to a volume ratio of 1: 160-1: 220, wherein the mass fraction of the hydrofluoric acid solution is 37% -45%.
In an embodiment of the present invention, when the reducing layer is removed, an etching selectivity ratio of the reducing layer to the second metal work function layer is 120:1 to 150:1.
In an embodiment of the present invention, the manufacturing method further includes: and after removing the reduction layer, continuing to deposit at least one metal work function layer in the concave part, and then depositing a metal conductive layer.
In an embodiment of the present invention, a gate oxide layer, a first gate dielectric layer and a second gate dielectric layer are formed between the dummy gate and the substrate, the gate oxide layer is formed on the substrate, the first gate dielectric layer is formed on the gate oxide layer, and the second gate dielectric layer is formed on the first gate dielectric layer.
In summary, the application provides a method for manufacturing a semiconductor device, which has the unexpected technical effects that the range of a reduction layer can be accurately controlled in the reduction process, so that accurate etching is realized, the side etching problem of a metal work function layer is reduced, the threshold voltage drift of the semiconductor device is reduced, the stability and balance of the semiconductor device are improved, the yield of the semiconductor device is improved, and the production cost is reduced; different types of semiconductor devices can be formed on the same substrate, and metal grids of different semiconductor devices can be formed simultaneously, so that the process integration degree is improved, the process period is shortened, and the manufacturing cost is reduced.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the invention.
FIG. 2 is a schematic diagram illustrating formation of a first photoresist layer according to an embodiment of the invention.
Fig. 3 is a schematic diagram of forming a shallow trench isolation structure and a well region in an embodiment of the invention.
Fig. 4 is a schematic diagram illustrating formation of a dummy gate according to an embodiment of the invention.
FIG. 5 is a schematic diagram illustrating formation of lightly doped regions according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of a contact etch stop layer formed according to an embodiment of the present invention.
FIG. 7 is a schematic diagram illustrating formation of a dielectric layer according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of removing the dummy gate and forming a first metal work function layer and a second metal work function layer according to an embodiment of the invention.
FIG. 9 is a schematic diagram illustrating formation of a reduction layer according to an embodiment of the invention.
FIG. 10 is a schematic diagram illustrating removal of a reduction layer according to an embodiment of the invention.
Fig. 11 is a schematic view of a semiconductor device according to an embodiment of the invention.
Description of the reference numerals:
10. A substrate; 101. a first well region; 102. a second well region; 11. a pad oxide layer; 12. pad nitriding layer; 13. a first photoresist layer; 131. an opening; 14. shallow trench isolation structures; 15. a gate oxide layer; 16. a first gate dielectric layer; 17. a second gate dielectric layer; 181. a first dummy gate; 182. a second dummy gate; 19. a lightly doped region; 20. a side wall structure; 21. a heavily doped region; 22. a metal silicide layer; 23. a contact hole etching stop layer; 24. a dielectric layer; 25. a first metal work function layer; 26. a second metal work function layer; 261. a reduction layer; 27. a bottom anti-reflection layer; 28. a second photoresist layer; 29. a third work function layer; 30. a fourth work function layer; 31. a metal conductive layer; 201. a first concave portion; 202. a second concave portion; 100. a first region; 200. a second region.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In the description of the present specification, it should be understood that the directions or positional relationships indicated in terms such as "center", "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or component referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The manufacturing method of the semiconductor device provided by the invention can form transistors of different types on the same substrate, reduce the threshold voltage drift of the semiconductor device, improve the stability and balance of the semiconductor device and improve the yield of the semiconductor device. The semiconductor device prepared by the method can be widely applied to various fields such as optical communication, digital display, image receiving, optical integration, traffic, energy, medicine, household appliances, aerospace and the like.
Referring to fig. 1 and 2, in an embodiment of the present application, a substrate 10 is provided, the substrate 10 includes a first region 100 and a second region 200, wherein the first region 100 is used for forming a P-type metal oxide semiconductor field effect transistor (PMOS), the second region 200 is used for forming a N-type metal oxide semiconductor field effect transistor (NEGATIVE CHANNEL METAL Oxide Semiconductor, NMOS), and the first region 100 and the second region 200 are isolated by a shallow trench isolation structure 14. The present application is not limited to the types of devices including PMOS transistors and NMOS transistors, such as Static Random-Access Memory (SRAM), CMOS image sensor, power device, or the like. In this embodiment, the substrate 10 may be any material suitable for forming a semiconductor device, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compound, a stacked structure formed of these semiconductor materials, or a silicon on insulator, a stacked silicon on insulator, a silicon germanium on insulator, a germanium on insulator, or the like. In the present embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate. In other embodiments, the type of substrate 10 is selected depending on the semiconductor device being fabricated.
Referring to fig. 1, in an embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10, the pad oxide layer 11 is used as a buffer layer to improve stress between the substrate 10 and a pad nitride layer 12 formed later, the pad oxide layer 11 is made of a material such as dense silicon oxide, and the pad oxide layer 11 can be formed by any one of a dry oxygen oxidation method, a wet oxygen oxidation method, or an In situ vapor growth method (In-Situ Steam Generation, ISSG). In this embodiment, the pad oxide layer 11 is formed, for example, by a dry oxidation method, specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900 ℃ to 1150 ℃, oxygen is introduced, the surface of the substrate 10 reacts with oxygen at a high temperature to generate a dense pad oxide layer 11, and the quality of the generated pad oxide layer 11 is better. The pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, 10nm, 20nm, 30nm, 40nm, or the like.
Referring to fig. 1, in an embodiment of the present invention, a pad nitride layer 12 is formed on a pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In the present embodiment, the pad nitride layer 12 is, for example, silicon nitride, and may be formed by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or the like. Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and the pad nitride layer 12 is deposited by reacting at a pressure of, for example, 2t to 10t and a temperature of, for example, 700 ℃ to 900 ℃, and the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. The thickness of the pad nitride layer 12 is, for example, 50nm to 80nm, specifically, for example, 50nm, 60nm or 70nm, and by providing the pad nitride layer 12, the substrate 10 can be protected from planarization processes such as Chemical Mechanical Polishing (CMP) involved in the process of manufacturing the shallow trench isolation structure 14. And the pad nitride layer 12 can be used as a mask in the subsequent shallow trench isolation structure formation process to protect the substrate 10 from damage during etching of the substrate 10.
Referring to fig. 1 to 3, in an embodiment of the invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12, and a plurality of openings 131 are formed on the first photoresist layer 13 through an exposure and development process, wherein the openings 131 are used to define the positions of the shallow trench isolation structures 14. Etching is performed using the first photoresist layer 13 as a mask to remove the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the opening 131, so as to form a shallow trench (not shown). In this embodiment, for example, a shallow trench is formed by dry etching, and after the etching is completed, the first photoresist layer 13 is removed. After the shallow trenches are formed, an insulating medium is deposited in the shallow trenches until the insulating medium covers the surface of the pad nitride layer 12. The present invention is not limited to the deposition method of the insulating medium, and for example, high-quality insulating medium can be formed by high-density plasma chemical vapor deposition (HIGH DENSITY PLASMA CVD, HDP-CVD) or high-aspect Ratio chemical vapor deposition (HIGH ASPECT Ratio Process CVD, HARP-CVD) or the like. In this embodiment, the insulating medium is, for example, silicon oxide, and in other embodiments, the insulating medium may be another insulating material suitable for isolation.
Referring to fig. 1 to 3, in an embodiment of the invention, after the insulating medium is prepared, the insulating medium is planarized, for example, by chemical mechanical polishing (CHEMICAL MECHANICAL Polish, CMP). For example, polishing to remove part of the insulating medium and part of the pad nitride layer 12, and then removing the pad nitride layer 12 to obtain the shallow trench isolation structure 14, wherein the shallow trench isolation structure 14 is higher than the pad oxide layer 11 on two sides, for example. The present invention is not limited to the method of removing the pad nitride layer 12, and for example, dry etching, wet etching, or a combination of dry etching and wet etching is used. In this embodiment, for example, the pad nitride layer 12 is removed by hot phosphoric acid to form the shallow trench isolation structures 14, and the plurality of shallow trench isolation structures 14 divide the substrate 10 into a plurality of regions, so as to avoid the generation of leakage current in the device.
Referring to fig. 2 to 3, in an embodiment of the present invention, after the preparation of the shallow trench isolation structure 14 is completed, the pad oxide layer 11 is used as an ion implantation buffer layer, and the substrate 10 is step-by-step implanted with ions to form the first well region 101 and the second well region 102 with different doping types. In this embodiment, for example, a silicon wafer semiconductor substrate is selected As the substrate 10, N-type dopant ions, for example, phosphorus (P) or arsenic (As), are implanted into the substrate 10 in the first region 100, the first well region 101 is formed, the first well region 101 is used As a formation region of a PMOS transistor, P-type dopant ions, for example, boron (B) or gallium (Ga), are implanted into the substrate 10 in the second region 200, and the second well region 102 is formed, and the second well region 102 is used As a formation region of an NMOS transistor. After the ion implantation, a rapid thermal annealing process (RAPID THERMAL ANNEAL, RTA) is performed on the first well region 101 and the second well region 102, so that the ion implantation of the first region 100 and the second region 200 is diffused to a proper depth, and the avalanche breakdown resistance of the semiconductor device is improved. The pad oxide layer 11 is etched by wet etching, for example, and the etching liquid of the wet etching is hydrofluoric acid or buffered oxide etching liquid (Buffered Oxide Etch, BOE) or the like.
Referring to fig. 3 to 4, in an embodiment of the invention, after removing the pad oxide layer, a gate oxide layer 15 is formed on the substrate 10, wherein the gate oxide layer 15 is, for example, a silicon oxide layer, and the gate oxide layer 15 is, for example, formed by an in-situ vapor growth method, and the thickness of the gate oxide layer 15 is, for example, 8a to 15 a. After forming the gate oxide layer 15, a first gate dielectric layer 16 is deposited on the gate oxide layer 15 and the shallow trench isolation structure 14, where the first gate dielectric layer 16 is, for example, one or more of hafnium oxide (HfO 2), hafnium oxynitride (HfON), zirconium oxide (ZrO 2), zirconium oxynitride (ZrON), zirconium oxynitride silicate (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitride silicate (HfSiON), hafnium lanthanum oxynitride (HfLaON) or hafnium aluminum oxide (HfAlO), and the first gate dielectric layer 16 has a thickness of, for example, 12 a to 20 a. The first gate dielectric layer 16 may be formed by, for example, using an atomic layer deposition method (Atomic Layer Deposition, ALD), a Metal organic vapor deposition method (Metal-Organic Chemical Vapor Deposition, MOCVD), a Molecular beam epitaxy method (Molecular BeamEpitaxy, MBE), or a physical vapor deposition method (Physical Vapor Deposition, PVD). By forming the gate oxide layer 15, the problem of poor interface quality between the first gate dielectric layer 16 and the substrate 10 can be improved, and the performance of the semiconductor device can be improved.
Referring to fig. 3 and 4, in an embodiment of the invention, after forming the first gate dielectric layer 16, a second gate dielectric layer 17 is formed on the first gate dielectric layer 16, the second gate dielectric layer 17 is, for example, titanium nitride, and the second gate dielectric layer 17 is, for example, prepared by using a direct current magnetron sputtering or an atomic layer deposition method, and the thickness of the second gate dielectric layer 17 is, for example, 15 a to 25 a. By providing the second gate dielectric layer 17, the first gate dielectric layer 16 can be prevented from being polluted or damaged in the subsequent manufacturing process, and the performance of the subsequently manufactured metal gate can be improved. A gate material layer, such as polysilicon, is then formed on the second gate dielectric layer 17. The thickness of the gate material layer is, for example, 100nm to 300nm. After the gate material layer is formed, a photoresist layer (not shown) is formed on the gate material layer, and then the photoresist is exposed and developed to form a patterned photoresist layer. The gate material layer is then etched, for example, by a dry etching process, a wet etching process, or a combination of a dry and wet etching process, using the patterned photoresist layer as a mask, to form a dummy gate. In the etching process, the first gate dielectric layer 16 and the second gate dielectric layer 17 outside the dummy gate are etched by taking the gate oxide layer 15 as an etching stop layer. In the present embodiment, for example, the first dummy gate 181 is formed on the first region 100, and the second dummy gate 182 is formed on the second region 200.
Referring to fig. 4 to 5, in an embodiment of the present invention, after forming the dummy gate, lightly doped regions 19 are formed in the substrate 10 at both sides of the first dummy gate 181 and the second dummy gate 182, respectively. Wherein the doping ions of the lightly doped region 19 are formed, for example, by ion implantation, and the implanted ions are of the opposite type to the ions in the well region. In this embodiment, the lightly doped region 19 in the first region 100 is doped with P-type impurity such as boron or gallium, the lightly doped region 19 in the second region 200 is doped with N-type impurity such as phosphorus or arsenic, and the lightly doped region 19 is formed to partially overlap the dummy gate during the process of implanting the doped ions.
Referring to fig. 5 to fig. 6, in an embodiment of the invention, after forming the lightly doped region 19, sidewall structures 20 are formed on two sides of the dummy gate, wherein the sidewall structures 20 are, for example, stacked structures. In this embodiment, the sidewall structure is formed by a stacked structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide, for example, from the side close to the dummy gate, where the silicon nitride layers are disposed on the two sides of the dummy gate, so that stability of the sidewall structure 20 after the dummy gate is removed can be improved. In other embodiments, the sidewall structure 20 is, for example, another stacked structure. By setting the sidewall structure 20 to a stacked structure, uniformity of the dummy gate is improved, thereby improving stability of the threshold voltage of the semiconductor structure.
Referring to fig. 5 to fig. 6, in an embodiment of the invention, after forming the sidewall structure 20, heavily doped regions 21 are formed on both sides of the first dummy gate 181 and the second dummy gate 182, respectively. The doping ions of the heavily doped region 21 are formed by ion implantation, and the ion type of the implantation is opposite to that of the well region, i.e. the same as that of the lightly doped region 19, and the doping concentration of the heavily doped region 21 is greater than that of the lightly doped region 19. After formation of heavily doped region 21, heavily doped region 21 and lightly doped region 19 are activated, for example by rapid thermal annealing of substrate 10. By rapid thermal annealing, lattice defects and activated dopant ions generated during the fabrication process can be repaired, thereby activating the heavily doped region 21 and the lightly doped region 19. After the heavily doped region 21 is formed, the sidewall structure 20 and the gate oxide layer 15 in the region other than the dummy gate are removed, for example, by etching, and a metal silicide layer 22 is formed on the heavily doped region 21, so as to improve the contact resistance of conductive plugs formed on the source electrode and the drain electrode later. After the metal silicide layer 22 is formed, a contact hole etching stop layer 23 is formed on the substrate 10, and the contact hole etching stop layer 23 is, for example, silicon nitride or the like. The contact hole etching stop layer 23 covers the side wall structure 20, the dummy gate, the substrate 10 and the shallow trench isolation structure 14, for example, so as to avoid affecting the stability of the side wall structure 20 or damaging the substrate 10 in the subsequent manufacturing process, thereby improving the performance of the semiconductor device.
Referring to fig. 6 to 8, in an embodiment of the present invention, after forming the contact hole etching stop layer 23, a dielectric layer 24 is formed on the substrate 10, where the dielectric layer 24 covers all of the dummy gate, the sidewall structure 20, the shallow trench isolation structure 14 and the substrate 10, for example. The dielectric layer 24 is, for example, silicon oxide, and is obtained by a chemical vapor deposition method or the like. In other embodiments, the dielectric layer 24 is made of silicon fluoride (SiF), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF), which are not limited in the present invention. After forming the dielectric layer 24, the dielectric layer 24 is planarized, for example, by chemical mechanical polishing to planarize the dielectric layer 24. In the polishing process, the top of the dummy gate is used as a polishing stop layer, non-selective polishing is adopted, the polishing time is controlled, the dielectric layer 24 and the contact hole etching stop layer 23 on the dummy gate are removed, the surfaces of the first dummy gate 181 and the second dummy gate 182 are exposed, and the surface of the dielectric layer 24 is flush with the surface of the dummy gate.
Referring to fig. 7 to 8, in an embodiment of the present invention, after the dielectric layer 24 and the contact hole etching stop layer 23 are planarized, the gate material layer exposed by the first dummy gate 181 and the second dummy gate 182 is removed, so as to form a first recess 201 at the position of the first dummy gate 181 and a second recess 202 at the position of the second dummy gate 182. In removing the gate material layer, dry etching, wet etching, or a combination of dry etching and wet etching may be employed. When dry etching is adopted, chlorine, bromine gas, helium gas, hydrogen bromide or the like or mixed gas of at least one gas and oxygen can be selected, and the dry etching has good anisotropism, good selectivity and high etching efficiency so as to ensure that the grid material layer has no residue. In the etching process, after the second gate dielectric layer 17 is exposed, etching is stopped, and the sidewall structure 20 remains as a sidewall structure of the metal gate prepared later.
Referring to fig. 8, in an embodiment of the present invention, after removing the dummy gate, a plurality of metal work function layers are deposited on the dielectric layer 24 and on the bottom and the sidewalls of the recess, wherein the metal work function layers are made of one or a stack of materials such as tantalum nitride (TaN), titanium nitride (tin), titanium aluminide (TiAl), titanium aluminum nitride (TiAIN), or tungsten nitride (WN), and the metal work function layers are formed by methods such as plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition (PECVD), atomic layer Deposition (ald), or physical Vapor Deposition (pvd). In the present embodiment, the metal work function layer includes, for example, a first metal work function layer 25 and a second metal work function layer 26, wherein the first metal work function layer 25 is disposed on, for example, the dielectric layer 24 and the bottom and the sidewalls of the recess. In this embodiment, the first metal work function layer 25 is, for example, a tantalum nitride layer, and the deposition method and thickness of the first metal work function layer 25 are, for example, atomic layer deposition, and the thickness is, for example, 15 a-25 a. The second metal work function layer 26 is, for example, a titanium nitride layer, the deposition method and thickness of the second metal work function layer 26 are selected according to the manufacturing requirement, and, for example, atomic layer deposition is selected for deposition, and the thickness is, for example, 35 a to 50 a. Due to the different threshold voltage requirements of NMOS and PMOS transistors, the second metal work function layer 26 on the second region 200 needs to be removed to realize semiconductor devices with different threshold voltages on the same substrate.
Referring to fig. 8 to 9, in an embodiment of the present invention, after forming the metal work function layer, a bottom anti-reflection layer 27 is formed on the metal work function layer, and the bottom anti-reflection layer 27 completely fills the first recess 201 and the second recess 202 and covers the second metal work function layer 26 on the dielectric layer 24, and the surface of the bottom anti-reflection layer 27 is flat. In the present embodiment, the bottom anti-reflection layer 27 is formed by, for example, spin coating or the like, and the bottom anti-reflection layer 27 is, for example, an organic substance. After the bottom anti-reflection layer 27 is formed, a second photoresist layer 28 is formed on the bottom anti-reflection layer 27, the second photoresist layer 28 on the first region 100 is remained by exposure, development, etc., the bottom anti-reflection layer 27 on the second region 200 is exposed, the bottom anti-reflection layer 27 on the second region 200 is removed by dry etching with the second photoresist layer 28 as a mask, so as to ensure that lateral etching does not occur on the bottom anti-reflection layer 27 at the interface of the first region 100 and the second region 200.
Referring to fig. 8 to 9, in an embodiment of the invention, after removing the bottom anti-reflection layer 27 on the second region 200, the second metal work function layer 26 on the second region 200 is reduced to form a reduction layer 261. In this embodiment, the reduction layer 261 is formed by performing a reaction using, for example, hydrogen plasma. Specifically, the substrate 10 with the bottom anti-reflection layer 27 removed on the second area 200 is placed in a plasma chamber, a mixed gas of hydrogen and inert gas, such as argon, is introduced, the total flow rate of the hydrogen and the inert gas is, for example, 20L/min-40L/min, the flow rate ratio of the hydrogen to the inert gas is, for example, 0.3:1-0.6:1, the current of the plasma chamber is, for example, 110 a-150 a, the power is, for example, 11 kw-15 kw, and the direct current bias voltage is, for example, 40 v-60 v. In the reduction process, the second metal work function layer 26 can be reduced into the reduction layer 261, meanwhile, the reactivity of tantalum nitride in the first metal work function layer 25 to hydrogen plasma is low, and the hydrogen plasma can be effectively prevented from being excessively reduced to the second gate dielectric layer 17 and the first gate dielectric layer 16. By controlling the magnitude of the dc bias, the collimation of the hydrogen plasma can be controlled, and the area range of the reduced second metal work function layer 26 can be effectively controlled, so that the second metal work function layer 26 on the first area 100 is prevented from being reduced from the side.
Referring to fig. 9 to 10, in an embodiment of the invention, after the reducing layer 261 is formed, the reducing layer 261 is removed, for example, by wet etching. In this embodiment, the etching liquid of wet etching is, for example, dilute hydrofluoric acid, and the dilute hydrofluoric acid is, for example, hydrofluoric acid solution and water in a volume ratio of, for example, 1: 160-1: 220, wherein the mass fraction of the hydrofluoric acid solution is, for example, 37% -45%. The dilute hydrofluoric acid is adopted for etching, the etching selectivity of the reduction layer 261, the second metal work function layer 26 and the first metal work function layer 25 is relatively high, the reduction layer 261 can be removed, meanwhile, the side etching of the second metal work function layer 26 on the first area 100 under the second photoresist layer 28 is reduced, and the yield and reliability of the semiconductor device are improved. After removing the reduction layer 261, the etching solution is replaced again, and the second photoresist layer 28 and the bottom anti-reflection layer 27 are removed.
Referring to fig. 9 to 10, in an embodiment of the present invention, during the reduction and etching processes, the reaction equations mainly occur include:
H• + TiN → Ti/TiHx+ NH3；
Ti/TiHx+ HF → TiF3+ H2↑。
In this embodiment, the etching selectivity of the diluted hydrofluoric acid to the reducing layer 261 and the second metal work function layer 26 is, for example, 120:1-150:1, the etching selectivity of the diluted hydrofluoric acid to the reducing layer 261 and the first metal work function layer 25 is, for example, 1100:1-1300:1, and the etching rate of the diluted hydrofluoric acid to the reducing layer 261 is, for example, 90 nm/min-110 nm/min. By adopting hydrogen plasma for reduction, the titanium nitride layer is reduced into titanium or titanium hydrogen compound, and the reaction speed of the titanium or titanium hydrogen compound in dilute hydrofluoric acid is higher, so that accurate etching is realized, the side etching problem in wet etching is reduced, threshold voltage drift (Vt shift) of NMOS/PMOS boundary is prevented from being caused, performance degradation and even device failure are further caused, and therefore, the stability and balance of the semiconductor device are improved, and the yield of the semiconductor device is improved. Meanwhile, a special second photoresist layer and a bottom anti-reflection layer are not needed, so that the production cost is reduced.
Referring to fig. 9 to 10, in an embodiment of the present application, after removing the reduction layer 261, a metal conductive layer 31 is formed on the second metal work function layer 26 of the first region 100 and the first metal work function layer 25 of the second region 200 to form a metal gate. In this embodiment, before forming the metal conductive layer 31, for example, at least one metal work function layer is deposited, and for example, the third work function layer 29 and the fourth work function layer 30 are deposited in the first recess 201 and the second recess 202, that is, the number of layers of the metal work function layers is not specifically limited in the present application, and is set according to the manufacturing requirements of the transistor. The third work function layer 29 is formed on the second metal work function layer 26 of the first region 100 and on the first metal work function layer 25 of the second region 200, wherein the third work function layer 29 is, for example, titanium aluminum alloy, and the deposition method and thickness of the third work function layer 29 are selected according to the manufacturing requirement, for example, physical vapor deposition is selected, and the thickness is, for example, 60 a to 80 a. The fourth work function layer 30 is formed on the third work function layer 29, the fourth work function layer 30 is, for example, a stack of titanium and titanium nitride, the deposition method and thickness of the fourth work function layer 30 are selected according to the manufacturing requirements, for example, physical vapor deposition is selected, and the thickness is, for example, 80 a to 120 a. A metallic conductive layer 31 is deposited on the fourth work function layer 30 until the first recess 201 and the second recess 202 are completely filled. The metal conductive layer 31 is then planarized until the surface of the metal conductive layer 31 is flush with the surface of the dielectric layer 24 to form a metal gate. The metal conductive layer 31 is made of a metal material with good conductivity, such as aluminum, tungsten, copper, or silver, and the metal conductive layer 31 has a structure of a single-layer metal, a multi-layer metal, or a metal compound stack. After the metal conductive layer 31 is planarized, for example, conductive plugs, metal wiring layers, and the like are fabricated, which will not be described herein. By the manufacturing method, different types of semiconductor devices can be formed on the same substrate, and metal grids of different semiconductor devices can be formed simultaneously, so that the process integration degree is improved, the process period is shortened, and the manufacturing cost is reduced.
In summary, the application provides a method for manufacturing a semiconductor device, which improves the method for manufacturing the semiconductor device, and has the unexpected technical effects that the range of a reduction layer can be accurately controlled in the reduction process, so that the accurate etching is realized, the side etching problem is reduced, the threshold voltage drift of the semiconductor device is reduced, the stability and balance of the semiconductor device are improved, the yield of the semiconductor device is improved, and the production cost is reduced; different types of semiconductor devices can be formed on the same substrate, and metal grids of different semiconductor devices can be formed simultaneously, so that the process integration degree is improved, the process period is shortened, and the manufacturing cost is reduced.
The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications can be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The above description is only a preferred embodiment of the present application and the description of the technical principle applied, and it should be understood by those skilled in the art that the scope of the present application is not limited to the specific combination of the above technical features, but also covers other technical features formed by any combination of the above technical features or the equivalent features thereof without departing from the inventive concept, for example, the technical features disclosed in the present application (but not limited to) are replaced with technical features having similar functions. Other technical features besides those described in the specification are known to those skilled in the art, and are not described herein in detail to highlight the innovative features of the present application.
Claims (7)
1. A method of fabricating a semiconductor device, comprising the steps of:
providing a substrate, wherein the substrate comprises a first region for forming a PMOS transistor and a second region for forming an NMOS transistor;
Forming a plurality of dummy gates on the substrate, the plurality of dummy gates being disposed on the first region and the second region;
forming a dielectric layer on the substrate, wherein the surface of the dielectric layer is flush with the surface of the dummy gate;
removing the dummy gate to form a concave part;
Sequentially forming a first metal work function layer and a second metal work function layer on the dielectric layer, the bottom and the side wall of the concave part;
Reducing the second metal work function layer on the second region to form a reduction layer, wherein the second metal work function layer is reduced by hydrogen plasma, and the direct current bias voltage of a plasma chamber is 40-60V during reduction;
Removing the reduction layer, wherein the reduction layer is removed through wet etching, the etching liquid of the wet etching comprises dilute hydrofluoric acid, and when the reduction layer is removed, the etching selectivity ratio of the reduction layer to the second metal work function layer is 120:1-150:1, and the etching selectivity ratio of the dilute hydrofluoric acid to the reduction layer to the first metal work function layer is 1100:1-1300:1, for example; and
A metal conductive layer is formed on the second metal work function layer of the first region and on the first metal work function layer of the second region.
2. The method of manufacturing a semiconductor device of claim 1, wherein the first metal work function layer comprises tantalum nitride and the second metal work function layer comprises titanium nitride.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the reduction layer includes:
Forming a photoresist layer on the first region;
and placing the substrate with the photoresist layer into the plasma cavity, and introducing mixed gas of hydrogen and inert gas.
4. The method for manufacturing a semiconductor device according to claim 3, wherein a total flow rate of the hydrogen gas and the inert gas is 20L/min to 40L/min, and a gas ratio of the hydrogen gas and the inert gas is, for example, 0.3:1 to 0.6:1.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the diluted hydrofluoric acid is a hydrofluoric acid solution and water in a volume ratio of 1: 160-1: 220, wherein the mass fraction of the hydrofluoric acid solution is 37% -45%.
6. The method of manufacturing a semiconductor device according to claim 1, further comprising: and after removing the reduction layer, continuing to deposit at least one metal work function layer in the concave part, and then depositing a metal conductive layer.
7. The method of manufacturing a semiconductor device according to claim 1, wherein a gate oxide layer, a first gate dielectric layer, and a second gate dielectric layer are formed between the dummy gate and the substrate, the gate oxide layer is formed on the substrate, the first gate dielectric layer is formed on the gate oxide layer, and the second gate dielectric layer is formed on the first gate dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410458342.1A CN118099097B (en) | 2024-04-17 | 2024-04-17 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410458342.1A CN118099097B (en) | 2024-04-17 | 2024-04-17 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118099097A CN118099097A (en) | 2024-05-28 |
| CN118099097B true CN118099097B (en) | 2024-07-23 |
Family
ID=91147961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410458342.1A Active CN118099097B (en) | 2024-04-17 | 2024-04-17 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118099097B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826256A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of CMOS (Complementary Metal Oxide Semiconductor) transistor |
| CN113097136A (en) * | 2020-01-08 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN117855254A (en) * | 2024-03-08 | 2024-04-09 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100384774B1 (en) * | 2000-11-16 | 2003-05-22 | 주식회사 하이닉스반도체 | Method for manufacturing gate in semiconductor device |
| CN104916588A (en) * | 2014-03-11 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| US9548372B2 (en) * | 2015-01-29 | 2017-01-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with tunable work function |
| US11217487B2 (en) * | 2018-11-30 | 2022-01-04 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and method of manufacture |
-
2024
- 2024-04-17 CN CN202410458342.1A patent/CN118099097B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826256A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of CMOS (Complementary Metal Oxide Semiconductor) transistor |
| CN113097136A (en) * | 2020-01-08 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN117855254A (en) * | 2024-03-08 | 2024-04-09 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118099097A (en) | 2024-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI668744B (en) | Semiconductor devices and methods for forming the same | |
| TWI392030B (en) | Method for making a semiconductor device | |
| US20210082688A1 (en) | Method for Metal Gate Surface Clean | |
| US9136340B2 (en) | Doped protection layer for contact formation | |
| CN106328589A (en) | FinFET channel on oxide structures and related methods | |
| KR102293862B1 (en) | Method for manufacturing of a semiconductor device | |
| US20150255564A1 (en) | Method for manufacturing a semiconductor device | |
| TWI767686B (en) | Contact plug | |
| TWI776514B (en) | Semiconductor device and method | |
| CN118366929B (en) | Manufacturing method of semiconductor device | |
| TW201543679A (en) | Semiconductor device structure and method for forming the same | |
| JP2002094059A (en) | Manufacturing method of mosfet device | |
| CN108735671B (en) | Method for manufacturing semiconductor device | |
| KR20170128170A (en) | Semiconductor structure with insertion layer and method for manufacturing the same | |
| TW201830500A (en) | Method of manufacturing semiconductor device structure | |
| CN116799004B (en) | Semiconductor integrated device and manufacturing method thereof | |
| CN109671673B (en) | Semiconductor structure and forming method thereof | |
| TWI763033B (en) | Semiconductor structure and method of forming the same | |
| CN118099097B (en) | Manufacturing method of semiconductor device | |
| CN118099162B (en) | Semiconductor device and manufacturing method thereof | |
| US12080597B2 (en) | Semiconductor devices and methods of manufacture | |
| US20220231023A1 (en) | Finfet device and method | |
| TWI609430B (en) | Semiconductor device having metal gate and manufacturing method thereof | |
| US20230268223A1 (en) | Semiconductor devices and methods of manufacture | |
| CN118658780A (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |