CN110474819B - FC-ETH protocol conversion chip verification device and method based on packet count - Google Patents
FC-ETH protocol conversion chip verification device and method based on packet count Download PDFInfo
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/18—Protocol analysers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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Abstract
本发明提供了一种基于包计数的FC‑ETH协议转换芯片验证装置及方法，包括TX端、RX端以及PRE‑CALCULATE模块，所述TX端将源协议标准包发送至所述协议转换芯片后，所述协议转换芯片接收所述源协议标准包进行解析并封装生成目标协议数据包，发送到所述RX端，所述RX端接收所述目标协议数据包，所述源协议为FC协议时，所述目标协议对应为ETH协议，所述源协议为FC协议时，所述ETH协议对应为FC协议，所述PRE‑CALCULATE模块连接所述TX端和RX端，用于预计算包计数。本发明所述的基于包计数的FC‑ETH协议转换芯片验证装置及方法通过PRE‑CALCULATE模块验证FC协议与ETH协议互转芯片的转发功能，支持单向转发与双向转发同时验证，更大程度的给测试人员提供便利。
The present invention provides an FC-ETH protocol conversion chip verification device and method based on packet counting, including a TX end, an RX end and a PRE-CALCULATE module, wherein the TX end sends a source protocol standard packet to the protocol conversion chip after the , the protocol conversion chip receives the source protocol standard packet, parses and encapsulates it to generate a target protocol data packet, and sends it to the RX end, where the RX end receives the target protocol data packet, and when the source protocol is the FC protocol , the target protocol corresponds to the ETH protocol, when the source protocol is the FC protocol, the ETH protocol corresponds to the FC protocol, and the PRE-CALCULATE module is connected to the TX end and the RX end for pre-calculating packet counts. The FC-ETH protocol conversion chip verification device and method based on the packet count of the present invention verifies the forwarding function of the FC protocol and the ETH protocol inter-conversion chip through the PRE-CALCULATE module, supports simultaneous verification of one-way forwarding and two-way forwarding, and can be used to a greater extent. for the convenience of testers.
Description
Technical Field
The invention belongs to the technical field of chip verification, and particularly relates to a verification device and a verification method for an FC-ETH protocol conversion chip.
Background
Currently, the interconnection of servers and storage devices usually adopts FC (fiber channel) protocol, and FC technology is a backbone network technology capable of providing high-speed data transmission for storage devices, IP data networks, audio streams and other applications. The chip for converting the protocol from the fc (fiber channel) protocol to the eth (ethernet) protocol has a wide application range and a powerful function, and the successful development of the chip will bring great convenience in many fields.
UVM logic simulation verification is an effective means for verifying the function of a protocol conversion chip, but the simulation speed is in direct proportion to the logic scale, when the scale of a digital circuit is large, the logic simulation time is increased, the verification period of the whole project is lengthened, the lead period of the whole project is limited, and meanwhile, the UVM logic simulation is mostly a supplementary test considering that certain difference still exists between a UVM logic simulation experiment and an actual application scene.
In addition, in the prior art, a mode based on an FPGA is usually adopted for function verification, and the existing thought is to verify the function of a forwarding chip by counting and comparing packet counts at the transmitting end and the receiving end, and when the function of a protocol conversion chip is verified, it is impossible to directly compare whether the packet counts are equal to judge whether the protocol conversion function is normal. Or the correctness of the protocol conversion cannot be determined by checking the CRC check bits alone, since there may be cases where the entire packet is lost. Or a single protocol forwarding function verification scheme such as a scheme of performing accumulation counting on the packet itself is not suitable for the function verification of the protocol conversion chip. In the test, the effective load payload of the sending end and the receiving end can be considered to be checked for manual comparison, but the test is time-consuming and labor-consuming and does not support the test of the line rate.
Considering that in the process of converting the FC protocol and the ETH protocol, the length of the data packets supported by different protocols is different due to protocol conversion during the transmission process of the data packets, and at this time, the number of the data packets is liable to change, and it is desired to compare whether the number of the data packets at the receiving end and the sending end conforms to the protocol conversion rule, and only by analyzing the conversion rule between different protocols by a tester, the change of the number of the packets before and after protocol conversion is calculated, and further, the number of the data packets is compared whether to be correct, which consumes a large amount of human resources, and considering that the number of the packets sent in a test scene is large, the real-time verification of the line.
Disclosure of Invention
In view of the above, the present invention is directed to a device and a method for verifying an FC-ETH protocol conversion chip based on packet counting, so as to solve the problems of great waste of human resources, error proneness, and inability of performing line rate verification due to the fact that the conventional forwarding chip function verification device only depends on manual comparison verification of packet counting.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the FC-ETH protocol conversion chip verification device based on the packet count comprises a TX end, an RX end and a PRE-CALCULATE module, wherein the TX end sends a source protocol standard packet to the protocol conversion chip, the protocol conversion chip receives the source protocol standard packet, analyzes and encapsulates the source protocol standard packet to generate a target protocol data packet, the RX end receives the target protocol data packet, the target protocol corresponds to an ETH protocol when the source protocol is an FC protocol, the ETH protocol corresponds to an FC protocol when the source protocol is an FC protocol, and the PRE-CALCULATE module is connected with the TX end and the RX end and used for PRE-calculating the packet count.
Further, the TX end includes a PAYLOAD _ GEN module, a PKT _ GEN module, and a TX _ PKT _ CNT module, which are connected in sequence, where the PAYLOAD _ GEN module is configured to generate a PAYLOAD in the source protocol packet, the PKT _ GEN module is configured to encapsulate the PAYLOAD into a source protocol standard packet, and the TX _ PKT _ CNT module is configured to calculate the number of the source protocol standard packets.
Further, the RX end includes an RX _ PKT _ CNT module, a PKT _ GET module, and a PAYLOAD _ GET module that are connected in sequence, where the RX _ PKT _ CNT module is used to calculate the number of the target protocol data packets, the PKT _ GET module is used to analyze the target protocol data packets, and the PAYLOAD _ GET module is used to obtain PAYLOAD in the target protocol data packets.
Further, the PRE-calibration module includes a packet counting unit, configured to generate a packet counting result and verify a function of the protocol conversion chip.
A verification method of an FC-ETH protocol conversion chip based on packet counting by applying the verification device comprises the following steps:
step 1: the TX end generates an effective load payload, encapsulates the effective load payload into a source protocol standard packet and sends the source protocol standard packet to a protocol conversion chip;
step 2: the protocol conversion chip receives the source protocol standard packet, analyzes and packages the source protocol standard packet to generate a target protocol data packet;
and step 3: and the RX end receives the target protocol data packet and analyzes the target protocol data packet to generate a payload.
And 4, step 4: comparing the length TX _ P _ L of a source protocol standard packet with the maximum packet length RX _ MAX _ L of a receiving end through the PRE-CALCULATE module, and outputting a PRE-calculation packet counting result Pre _ C _ Cnt;
and 5: and (4) comparing the pre-calculation packet counting result in the step (4) with the number of the target protocol data packets, wherein if the pre-calculation packet counting result is equal to the number of the target protocol data packets, the performance of the protocol conversion chip is good, and otherwise, the performance is lost.
Further, the step 1 further includes recording the number of source protocol standard packets by the TX _ PKT _ CNT module.
Further, the step 3 further includes recording, by the RX _ PKT _ CNT module, the number of target protocol packets received by the RX end.
Further, in step 1, the PAYLOAD _ GEN module generates a PAYLOAD in a source protocol packet, and encapsulates the source protocol standard packet through the PKT _ GEN module.
Further, in step 3, the PKT _ GET module parses the target protocol data packet, and obtains the PAYLOAD in the target protocol data packet through the PAYLOAD _ GET module.
Further, the step 4 comprises: comparing TX _ P _ L and RX _ MAX _ L, when TX _ P _ L > RX _ MAX _ L, Pre-calculated packet count Pre _ C _ Cnt is equal to (TX _ P _ L/RX _ MAX _ L) + X, X is equal to or larger than 1, when TX _ P _ L is equal to or smaller than RX _ MAX _ L, Pre-calculated packet count Pre _ C _ Cnt is equal to GEN _ Cnt, wherein GEN _ Cnt is the number of source protocol standard packets.
Compared with the prior art, the FC-ETH protocol conversion chip verification device and method based on packet counting have the following advantages: the invention comprises a PRE-CALCULATE module, records the counting of a transmitting end and a receiving end by extracting protocol information of the transmitting end and the receiving end, analyzes the PAYLOAD characteristic, compares the received actual counting value with the counting value obtained by a PRE-calculation module so as to verify the protocol forwarding function, and supports the simultaneous verification of the unidirectional protocol forwarding and the bidirectional protocol forwarding.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a verification apparatus when a TX end is an FC protocol device and an RX end is an ETH protocol device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a verification method according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating an algorithm of the PRE-CALCULATE module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a verification apparatus when a TX end is an ETH protocol device and an RX end is an FC protocol device according to the embodiment of the present invention;
fig. 5 is a schematic structural diagram of a verification apparatus for simultaneously verifying an ETH protocol to an FC protocol and an FC protocol to an ETH protocol according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention will be described in detail below with reference to the following examples with reference to the attached drawings:
a verification device of an FC-ETH protocol conversion chip based on packet counting comprises a TX end, an RX end and a PRE-CALCULATE module, wherein the TX end sends a source protocol standard packet to the protocol conversion chip, the protocol conversion chip receives the source protocol standard packet, analyzes and encapsulates the source protocol standard packet to generate a target protocol data packet, the RX end receives the target protocol data packet, the target protocol corresponds to an ETH protocol when the source protocol is an FC protocol, the ETH protocol corresponds to an FC protocol when the source protocol is an FC protocol, and the PRE-CALCULATE module is connected with the TX end and the RX end and used for PRE-calculating packet counting.
The TX end comprises a PAYLLOAD _ GEN module, a PKT _ GEN module and a TX _ PKT _ CNT module which are connected in sequence, wherein the PAYLLOAD _ GEN module is used for generating PAYLOAD in the source protocol packet, the PKT _ GEN module is used for packaging the PAYLOAD into a source protocol standard packet, and the TX _ PKT _ CNT module is used for calculating the number of the source protocol standard packets.
The RX end includes an RX _ PKT _ CNT module, a PKT _ GET module, and a PAYLOAD _ GET module that are connected in sequence, where the RX _ PKT _ CNT module is used to calculate the number of the target protocol data packets, the PKT _ GET module is used to analyze the target protocol data packets, and the PAYLOAD _ GET module is used to obtain PAYLOAD in the target protocol data packets.
The PRE-CALCULATITE module comprises a packet counting unit and is used for generating a packet counting result and verifying the function of the protocol conversion chip.
As shown in FIG. 2, the present invention also provides a packet counting based FC-ETH protocol conversion chip verification method using the verification device, comprising
Step 1: the TX end generates an effective load payload, encapsulates the effective load payload into a source protocol standard packet and sends the source protocol standard packet to a protocol conversion chip;
step 2: the protocol conversion chip receives the source protocol standard packet, analyzes and packages the source protocol standard packet to generate a target protocol data packet;
and step 3: and the RX end receives the target protocol data packet and analyzes the target protocol data packet to generate a payload.
And 4, step 4: comparing the length TX _ P _ L of a source protocol standard packet with the maximum packet length RX _ MAX _ L of a receiving end through the PRE-CALCULATE module, and outputting a PRE-calculation packet counting result Pre _ C _ Cnt;
and 5: and (4) comparing the pre-calculation packet counting result in the step (4) with the number of the target protocol data packets, wherein if the pre-calculation packet counting result is equal to the number of the target protocol data packets, the performance of the protocol conversion chip is good, and otherwise, the performance is lost.
The step 1 further comprises recording the number of source protocol standard packets through the TX _ PKT _ CNT module.
The step 3 further includes recording, by the RX _ PKT _ CNT module, the number of target protocol packets received by the RX end.
In the step 1, the PAYLOAD _ GEN module generates PAYLOAD in a source protocol packet, and encapsulates the source protocol standard packet through the PKT _ GEN module.
In the step 3, the PKT _ GET module analyzes the target protocol data packet, and obtains the PAYLOAD in the target protocol data packet through the PAYLOAD _ GET module.
Preferably, the step 4 comprises: comparing TX _ P _ L and RX _ MAX _ L, when TX _ P _ L > RX _ MAX _ L, Pre-calculated packet count Pre _ C _ Cnt is equal to (TX _ P _ L/RX _ MAX _ L) + X, X is equal to or larger than 1, when TX _ P _ L is equal to or smaller than RX _ MAX _ L, Pre-calculated packet count Pre _ C _ Cnt is equal to GEN _ Cnt, wherein GEN _ Cnt is the number of source protocol standard packets.
As shown in fig. 1, in the case that the TX end is an FC protocol device, and the RX end is an ETH protocol device, the protocol conversion chip is a DUT module in the drawing, where the TX end includes a PAYLOAD _ GEN module, a PKT _ GEN module, and a TX _ PKT _ CNT module, the PAYLOAD _ GEN module is used to generate a PAYLOAD in an FC protocol packet, the PKT _ GEN module is used to encapsulate an FC protocol standard packet, and the TX _ PKT _ CNT module is used to calculate the number of packets sent by the TX end.
The DUT module comprises a Parser unit, a DE-Parser unit, a PKT _ Segment unit and a Head _ Maper unit, wherein the DUT module receives an FC protocol standard packet, analyzes the FC protocol standard packet through the Parser unit, extracts a payload in the received standard packet, judges whether the packet needs to be divided through the PKT _ Segment unit, reads a target protocol encapsulation packet rule through the Head _ Maper unit, encapsulates the target protocol encapsulation packet rule through the DE-Parser unit, generates an ETH protocol data packet and routes the ETH protocol data packet to a Port of the RX end.
The RX end comprises a PAYLOAD _ GET module, a PKT _ GET module and an RX _ PKT _ CNT module, wherein the RX _ PKT _ CNT module is used for calculating the number of received packets, the PKT _ GET module is used for analyzing an ETH protocol data packet, and the PAYLOAD _ GET module obtains a PAYLOAD in the ETH protocol data packet.
After the protocol conversion chip completes the protocol conversion, considering that the maximum number of bytes supported by different protocol data packets is different, and the packet count of the receiving end and the sending end is not in a 1:1 relationship, in the device, the payload is segmented by the PKT _ Segment module, the standard FC format data packet supports 2112 bytes at most, and the standard ETH format packet supports 1472 bytes at most, so that real-time packet cutting processing needs to be performed according to the PCIE format data packet, and the part which is less than 1472 bytes can be split according to a specific unpacking rule, so that the PRE-call module needs to complete comparison of the packet counts at the receiving end and the sending end.
The PRE-calculation module includes a packet counting unit, where the packet counting unit is configured to determine sizes of the TX end transmission packet length TX _ P _ L and the RX end reception maximum packet length RX _ MAX _ L, and determine a PRE-calculation packet count: when TX _ P _ L > RX _ MAX _ L, the Pre-calculated packet count Pre _ C _ Cnt is (TX _ P _ L/RX _ MAX _ L) + X, X is greater than or equal to 1, and when TX _ P _ L is less than or equal to RX _ MAX _ L, the Pre-calculated packet count Pre _ C _ Cnt is GEN _ Cnt, where GEN _ Cnt is the TX-side packet count, and in general, the portion exceeding the maximum packet length received by RX-side is directly encapsulated into 1 packet, and the value of X is 1 at this time, but considering the unpacking rule of the fraction remainder portion may be split into a length of 2 raised to an integer power, or adopting the unpacking rule applicable to a specific scenario, where X is greater than or equal to 1, the Pre-call block algorithm flowchart is as shown in fig. 3.
The PRE-CALCULATE module is provided with four inputs, a TX-end protocol information PKT _ GEN-FC protocol, a TX _ P _ L protocol, a sending-end packet count TX _ PKT _ CNT, an RX-end packet count RX _ PKT _ CNT and an RX-end protocol information PKT _ GET-ETH protocol are respectively extracted, the result of PRE-calculation packet count of the PRE-CALCULATE module operation rule is compared with the RX-end packet count, and if the two values are equal, the protocol conversion chip is indicated to have no abnormity in the packet level function, and verification is completed.
As shown in fig. 4, in the case where the TX end is an ETH protocol device and the RX end is an FC protocol device, because the payload length of the ETH can be directly encapsulated as a single packet in the FC format, the case where the packet in the FC format is converted into a split packet in the ETH format does not occur, but considering that packet counts may not be in a one-to-one correspondence relationship in some special scenarios, the packet number calculation module is still reserved, and in general, the packet count of the ETH sending device should be equal to the packet count value of the FC receiving device.
The verification device of the present invention also supports two-way simultaneous data packet transmission and verification, as shown in fig. 5, can simultaneously verify an ETH protocol to FC protocol and an FC protocol to ETH protocol, and combine the TX end and the RX end, in which case the two endpoint devices need to simultaneously assume the functions of the transmitting device and the verifying device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
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