CN112330456B - Ultra-low-delay hardware acceleration market data stream analysis system - Google Patents

Abstract

The present invention discloses an ultra-low latency hardware accelerated market data stream parsing system, including a bus interface, an FPGA acceleration card and a main server, wherein the FPGA acceleration card is used to obtain market data information from the bus interface and transmit the market data information to the main server after parsing; the FPGA acceleration card includes a PHY physical module, a MAC module, a UDP/IP parsing module and a corresponding storage area, wherein the PHY physical module is used to receive the market data information transmitted by the bus interface within a specified period and transmit the market data information to the MAC module, wherein the MAC module is used to perform a CRC32 check on the acquired market data information and transmit it to the UDP/IP parsing module. The present invention provides an ultra-low latency hardware accelerated market data stream parsing system, which migrates the heavy load parsing tasks of the CPU to the FPGA dedicated hardware processing, performs circuit-level parallel operation optimization, reduces the CPU load, and realizes the overall acceleration of market communication and decoding.

Description

An ultra-low latency hardware-accelerated market data stream analysis system

Technical Field

The present invention relates to the field of information processing technology, and in particular to an ultra-low latency hardware accelerated market data stream parsing system.

Background Art

For the ever-changing securities trading market, real-time market information is the foundation of the trading system. Rapid acquisition of market information can provide market participants with a more ample time window for trading decisions. The lower the latency of market information obtained by traders, the more trading opportunities and the greater the decision-making space. In traditional software-based market information systems, information analysis generally goes through processes such as network layer data acquisition, protocol layer data analysis, and application layer data processing. At the operating system and protocol level, there are millisecond-level context switching and software processing delays. Due to the operating system's process scheduling and the dynamic adjustment mechanism of the CPU main frequency, this delay also has a certain degree of uncertainty.

FAST (FIX Adapted for Streaming) is a compression, encoding and transmission method for message streams proposed by FPL, a global financial enterprise alliance organization, in 2005. It mainly uses the logical connection between the field data of the messages transmitted successively in the message stream to compress the data content to be transmitted, and performs efficient binary encoding for different types of binary fields to improve the compression rate and reduce the size of the transmitted data. However, for downstream users, it is difficult to develop a decoding program. The current market analysis mainly relies on the soft analysis mode based on the traditional server CPU, and decodes the FAST code stream by calling mFAST and openFAST. Due to the streaming arrangement characteristics of FAST data, the data has a large correlation before and after, and it is difficult to use the multi-threading of the CPU to achieve parallel processing. At the same time, the relatively fixed processing mode of the CPU cannot provide a more fine-grained operation scheduling at the bottom layer, so the soft decoding delay of FAST is high, and the CPU load is large, which is the pain point of the existing market analysis system.

For the quotation publishing system of the Shanghai Stock Exchange, the quotation data stream needs to cross multiple layers of protocols to reach the physical communication port. These layers are mainly composed of network communication and STEP-FAST data stream exchange protocol. The exchange quotation data of my country's financial information industry currently mainly adopts the STEP (Securities Trading Exchange Protocol) protocol, and is based on the FIX (Financial Information eXchange protocol) protocol, which is the international mainstream financial information exchange standard. According to the streaming processing characteristics of the quotation data, FAST (FIX Adapted For Streaming) encoding compression is performed. On the one hand, the protocol defines various fields and operators for identifying specific stocks and their pricing. On the other hand, the streaming data compression mechanism brought by FAST encoding can greatly reduce bandwidth, but it also significantly increases the complexity of data parsing.

Summary of the invention

The purpose of the present invention is to provide an ultra-low latency hardware accelerated market data stream parsing system, which migrates the heavy-load parsing tasks of the CPU to FPGA dedicated hardware processing, optimizes parallel operations at the circuit level, reduces the CPU load, and achieves overall acceleration of market communication and decoding.

To achieve the above object, the present invention provides the following technical solutions: an ultra-low latency hardware accelerated market data stream parsing system, comprising a bus interface, an FPGA accelerator card and a main server, wherein the FPGA accelerator card is used to obtain market data information from the bus interface and transmit the market data information to the main server after parsing;

The FPGA acceleration card includes a PHY physical module, a MAC module, a UDP/IP parsing module and a corresponding storage area, wherein the PHY physical module is used to receive the market data information transmitted by the bus interface within a specified period and transmit the market data information to the MAC module, wherein the MAC module is used to perform CRC32 verification on the acquired market data information and transmit it to the UDP/IP parsing module, wherein the UDP/IP parsing module performs communication parsing processing on the verified market data information and generates original data;

The FPGA accelerator card further includes a STEP hardware parser, a FAST hardware parser and a CPU module, wherein the CPU module is used to send control instructions to the STEP hardware parser and the FAST hardware parser, and the STEP hardware parser is used to obtain the original data and perform segmentation and encoding processing on the original data to generate transmission fields to be sent to corresponding storage areas for caching;

The FAST hardware parser is used to call the transmission fields from the corresponding storage area in parallel and perform parallel FAST protocol parsing and reorganization parsing on the transmission fields to generate parsed market information, so as to send the parsed market information to the main server.

Preferably, the STEP hardware parser comprises a first processing circuit, wherein the first processing circuit comprises a stop bit detection unit and a field segmentation unit;

The stop bit detection unit is used to identify the stop byte and transmit the bit sequence of several stop bytes in the original data to the field segmentation unit;

The field segmentation unit is used to segment the original data into a plurality of fields according to the position sequence of the plurality of stop bytes.

Preferably, the first processing circuit further comprises a specific character detection unit and a coding processing unit, and the coding processing unit comprises a plurality of coding processing sub-units;

The specific character detection unit sequentially receives a plurality of fields transmitted by the field segmentation unit, and is used to detect whether there is an identification character in the field, and sends the field containing the corresponding identification character to the corresponding encoding processing subunit;

The encoding processing subunit is used to perform encoding processing on the corresponding fields to reduce the storage occupation of the corresponding fields.

Preferably, the specific character detection unit is also used to send the identification characters contained in the received field to the CPU module in chronological order, and the CPU module is configured with a reconstruction strategy, which constructs a field reconstruction sequence according to the chronological order of the identification characters received.

Preferably, the encoding processing subunit performs encoding processing on the corresponding fields according to the first processing instruction sent by the CPU module to reduce the storage occupancy of the corresponding fields and generates several transmission fields and sends them to the corresponding buffer area for caching.

Preferably, the first processing instruction comprises deleting the stop byte and the identification character contained in the field.

Preferably, the FAST hardware parser includes a second processing circuit, the second processing circuit includes a FSAT protocol decoding processing unit and a reorganization decoding processing unit, the FSAT protocol decoding processing unit includes a plurality of decoding operator units respectively connected to corresponding storage areas, the plurality of decoding operator units obtain the transmission fields from a plurality of corresponding storage areas in parallel and perform FAST protocol parsing processing on the transmission fields to generate a plurality of reorganization fields, the reorganization decoding processing unit receives a plurality of the reorganized fields in parallel, and according to a second processing instruction sent by the CPU module, sequentially reorganizes the plurality of the reorganized fields according to the field reconstruction sequence to generate parsed market information.

Preferably, the second processing instruction includes sequentially adding a stop bit and a corresponding identification bit at the first position of the plurality of reorganized fields to generate a decoding field, and sorting the plurality of decoding fields according to the field reconstruction sequence.

Preferably, the market data information includes transaction-by-transaction information, and the stop bit detection unit detects the original data in 1 byte as the detection unit, and completes the highest bit detection in each detection unit in a single clock cycle. When the highest bit is 1, the byte to which it belongs is a stop byte.

Preferably, the market data information includes market snapshot information, and the stop bit detection unit detects the original data with 4 bytes as the detection unit, completes the highest bit detection in each detection unit in a single clock cycle, and when the highest bit is 1, the byte is the stop byte. After data investigation, each field in the market snapshot information in the market release system of the Shanghai Stock Exchange is a multiple of 4 bytes, so the detection unit in this embodiment is set to 4 bytes, which can improve the processing speed.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention designs a hardware system for parsing the STEP-FAST data stream exchange protocol based on FPGA. The STEP hardware parser divides the fields according to different field types. After the fields are divided, it is convenient to classify the fields of the same type, and then centralized and efficient parsing processing is performed through hardware circuit design. The FAST hardware parser decodes the divided data in parallel, migrates the heavy-load parsing tasks of the CPU to the FPGA dedicated hardware processing, optimizes the parallel operation at the circuit level, reduces the CPU load, and the decoding delay can be as low as 33ns, realizing the overall acceleration of market communication and decoding.

The FAST hardware parser of the present invention includes a plurality of decoding operator units matching corresponding fields, which are used to perform FAST protocol parsing processing on the corresponding fields; and the FPGA accelerator card also includes a CPU module, which is used to send control instructions to the STEP hardware parser and the FAST hardware parser, and the encoding processing subunit of the STEP hardware parser encodes the corresponding fields according to the first processing instruction sent by the CPU module to reduce the storage occupation of the corresponding fields. The CPU module is configured with a reconstruction strategy, which is to construct a field reconstruction sequence according to the time sequence of the identification characters received by it, and the reorganization decoding processing unit of the FAST hardware parser receives the reorganized fields in parallel, and according to the second processing instruction sent by the CPU module, sequentially reorganizes the plurality of reorganized fields according to the field reconstruction sequence to generate parsed market information.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a circuit connection block diagram of an ultra-low latency hardware accelerated market data stream analysis system according to the present invention;

FIG2 is a connection diagram of a PHY physical module and a MAC module in an ultra-low latency hardware accelerated market data stream analysis system of the present invention;

3 is a schematic diagram of the internal circuit connections of a STEP hardware parser in an ultra-low latency hardware accelerated market data stream parsing system according to the present invention;

4 is a schematic diagram of the internal circuit connections of a FAST hardware parser in an ultra-low latency hardware accelerated market data stream parsing system according to the present invention;

FIG5 is a diagram showing the encoding characteristic structure of a FAST data stream in an ultra-low latency hardware accelerated market data stream parsing system according to the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

As shown in FIG1 , the first embodiment provided by the present invention is an ultra-low latency hardware accelerated market data stream parsing system, comprising a bus interface, an FPGA acceleration card and a main server, wherein the FPGA acceleration card is used to obtain market data information from the bus interface and transmit the market data information to the main server after parsing; the FPGA acceleration card comprises a PHY physical module, a MAC module, a UDP/IP parsing module and a corresponding storage area, wherein the PHY physical module is used to receive the market data information transmitted by the bus interface within a specified period and transmit the market data information to the MAC module, wherein the MAC module is used to perform CRC32 check on the obtained market data information and transmit it to the UDP/IP parsing module, wherein the UDP/IP parsing module performs communication parsing on the verified market data information and generates original data.

In the present invention, a high-speed 10 Gigabit Ethernet interface QSFP bus interface is connected to an FPGA acceleration card, a PHY IP provided by Xilinx is used in the physical layer, and a 10 Gigabit Ethernet MAC IP of Xilinx is used in the MAC layer to implement the filling and detection of the CRC32 check code of the transmission protocol, and a UDP/IP protocol parsing circuit is customized and designed through Verilog; the FPGA acceleration card also includes a STEP hardware parser, a FAST hardware parser and a CPU module, the CPU module is used to send control instructions to the STEP hardware parser and the FAST hardware parser, and the STEP hardware parser is used to obtain the original data and generate a transmission field after segmenting and encoding the original data to send it to a corresponding storage area for caching;

The FAST hardware parser is used to call the transmission fields from the corresponding storage area in parallel and perform parallel FAST protocol parsing and reorganization parsing on the transmission fields to generate parsed market information, so as to send the parsed market information to the main server.

As shown in Figure 2, the data stream simulation circuit signal is transmitted through the high-speed serial interface SERDES, in conjunction with the PHY IP, to achieve the receiving end clock recovery/transmission pre-emphasis, encoding and decoding, channel bonding, data caching, etc. of the electrical signal. The parsed digital signal data will be transmitted through the XGMII interface and the MAC module to encode the transmitted data frame. The Ethernet high-speed communication circuit designed in the present invention adopts a 64-bit single-rate XGMII bus interface and a full-duplex 10Gbit/s Ethernet media controller, supports the preamble filtering and addition of 10 Gigabit Ethernet data, and the filling and verification of the CRC check code. The minimum Ethernet data frame length is 64 bytes and the maximum is 1518 bytes. Before the transmitting end transmits data, the MAC controller will first send a 7-byte synchronization code and a 1-byte frame delimiter, and fill a 4-byte CRC32 check code at the end of 1 frame transmission. If the data length is less than 46 bytes, the PAD character will be automatically filled in the data field, that is, 0 is filled. At the receiving end, the MAC layer removes the preamble and frame delimiter, and performs a CRC32 check on the frame. The data obtained by the MAC layer will be further parsed by the UDP/IP parsing module and finally converted into actual Raw Data. However, the Raw Data obtained by the communication interface is still not market information that can be directly read. It must be parsed in accordance with the market information encoding and decoding specifications. The present invention implements the corresponding hardware parser on the FPGA.

As shown in Figure 3, the STEP hardware parser includes a first processing circuit, which includes a stop bit detection unit and a field segmentation unit; the stop bit detection unit is used to identify the stop byte and transmit the position sequence of several stop bytes in the original data to the field segmentation unit; the field segmentation unit is used to segment the original data into several fields according to the position sequence of several stop bytes. The first processing circuit also includes a specific character detection unit and an encoding processing unit, and the encoding processing unit includes a plurality of encoding processing sub-units; the specific character detection unit sequentially receives a plurality of fields transmitted by the field segmentation unit, and the specific character detection unit is used to detect whether there is an identification character in the field, and send the field containing the corresponding identification character to the corresponding encoding processing sub-unit; the encoding processing sub-unit is used to encode the corresponding field to reduce the storage occupancy of the corresponding field; the specific character detection unit is also used to send the identification characters contained in the received field to the CPU module in chronological order, and the CPU module is configured with a reconstruction strategy, and the reconstruction strategy is to construct a field reconstruction sequence according to the chronological order of the identification characters received; the encoding processing sub-unit encodes the corresponding field according to the first processing instruction sent by the CPU module to reduce the storage occupancy of the corresponding field and sends the generated plurality of transmission fields to the corresponding cache area for caching. The STEP hardware parser divides the fields according to the different field types. After the fields are divided, it is convenient to classify the fields of the same type and perform subsequent decoding processing. Then, centralized and efficient parsing processing is performed through hardware circuit design. In addition, the corresponding fields are encoded by setting the encoding processing subunit to reduce the storage occupancy of the corresponding fields, reduce the amount of data operations in the subsequent parsing process, and improve the parsing speed; the FAST hardware parser decodes the segmented data in parallel, migrates the heavy-load parsing tasks of the CPU to the FPGA dedicated hardware processing, optimizes parallel operations at the circuit level, reduces the CPU load, and the decoding delay can be as low as 33ns, realizing the overall acceleration of market communication and decoding.

In the first embodiment of the STEP hardware parser provided by the present invention, the STEP protocol uses tag=value to encapsulate the FAST-encoded data stream with additional information, which can provide business session information other than trading market information. In order to minimize the delay of market data parsing, a hardware parser of the STEP protocol is custom designed using Verilog. The parser module obtains a 64-bit data segment transmitted from the AXI bus via the network port in each cycle. The 64-bit data segment will be processed in units of 8-bit. By detecting the ASCII code of "=" and SOH, the tag or value attribute of the current data segment is automatically determined, and sent to the specified cache space for subsequent information reading or further FAST decoding.

In the present invention, the encoding processing subunit performs encoding processing on the corresponding field according to the first processing instruction sent by the CPU module, including but not limited to the following three processing encoding compression methods:

1) Define templates to reduce repeated Tag data. Specific categories of data often have relatively fixed formats and are generally composed of a group of relatively common Tags, such as market snapshots, tick-by-tick, index and other information. Therefore, a specific group of Tags can be converted into a set of templates agreed upon by both the sender and the receiver to parse the data. When both parties obtain the data parsing template, the code stream no longer needs to save the Tag information, but only needs to organize the data according to the field order and operation defined by the template, thereby eliminating the need to transmit the Tag data.

2) Data operations and data type definitions increase the storage overhead of Value data. This method mainly uses the relevance of data context to reduce unnecessary data storage, including but not limited to the following situations that may exist in Value data: the current value of the data remains unchanged from the previous value, the difference between the current value and the previous value is small, and there is data of indefinite length. According to the previous and subsequent associations of the data and the actual length of the Value, it is only necessary to record relatively concise information such as historical data, changes, and valid data, and the original data can be restored through inversion operations, which can greatly reduce the storage overhead of the data code stream.

3) Use a single stop bit instead of the <SOH> delimiter. The use of the <SOH> delimiter in FIX will inevitably cause each field to take up 1 byte of storage. FAST encoding changes the field separation to the highest bit of the byte data, which can further optimize the compression ratio of the code stream.

Preferably, the first processing instruction comprises deleting the stop byte and the identification character contained in the field.

As shown in FIG4 , the FAST hardware parser includes a second processing circuit, the second processing circuit includes a FSAT protocol decoding processing unit and a reorganization decoding processing unit, the FSAT protocol decoding processing unit includes a number of decoding operator units respectively connected to corresponding storage areas, the number of decoding operator units obtain the transmission fields from the number of corresponding storage areas in parallel and perform FAST protocol parsing processing on the transmission fields to generate a number of reorganized fields, the reorganization decoding processing unit receives the number of reorganized fields in parallel, and according to the second processing instruction sent by the CPU module, the number of reorganized fields are sequentially reorganized according to the field reconstruction sequence to generate parsed market information. The second processing instruction includes sequentially adding stop bits and corresponding identification bits to the first positions of the number of reorganized fields to generate decoding fields, and sorting the number of decoding fields according to the field reconstruction sequence.

The hardware-implemented operators are key components of FAST decoding. These operators include, but are not limited to, field selection, data shifting, calculation, copying, tail update, byte vector counting, sequence field loop control, etc. The decoding operator unit can run at a higher clock frequency and complete the corresponding operator operation within 1-2 clock cycles (except counting and loop control operations). The control signals of all operator modules can be uniformly integrated and controlled by microinstructions, providing sufficient hardware scheduling flexibility for decoding.

The CPU module is configured with a reconstruction strategy, which builds a field reconstruction sequence according to the chronological order of the identification characters it receives. On the one hand, it ensures the order of the parsing process, and on the other hand, it still improves the parallelism of hardware operator processing, which can further improve the hardware parsing performance.

Preferably, the market data information includes transaction-by-transaction information, and the stop bit detection unit detects the original data with 1 byte as the detection unit, and completes the highest bit detection in each detection unit in a single clock cycle. When the highest bit is 1, the byte to which it belongs is the stop byte. Transaction-by-transaction information is also called tick information, which is transaction-by-transaction data on the entire market. For example, a new order from an investor will form a market, and a new transaction matched by an exchange will also form a market. The tick market records the data of every event in the market, which is the most detailed and complete data. Therefore, the detection unit of the transaction-by-transaction information must be detected in a minimum unit of 1 byte to ensure accuracy.

Preferably, the market data information includes market snapshot information, and the stop bit detection unit detects the original data with 4 bytes as the detection unit, completes the highest bit detection in each detection unit in a single clock cycle, and when the highest bit is 1, the byte is the stop byte. After data investigation, each field in the market snapshot information in the market release system of the Shanghai Stock Exchange is a multiple of 4 bytes, so the detection unit in this embodiment is set to 4 bytes, which can ensure accuracy while improving processing speed.

Overall market analysis delay test:

The test data takes a step data of Shanghai Stock Exchange level 1 quotation as an example. The length of the STEP packet data tested is 1515 bytes, including a 98-byte STEP header, a 181-byte FIX header, 1221-byte 20 FAST messages, and an 8-byte FIX tail and a 7-byte Step tail. VDE repeatedly sends the STEP packet, and the average decoding delay of software and hardware decoding is shown in Table 1:

Table 1: FAST decoding software and hardware solution processing performance comparison

Software decoding Hardware decoding Sample STEP data average: 217us Sample STEP data average: 14us

The delay of the software decoding part is 150us-250us, and the time fluctuates depending on the CPU load; the hardware decoding delay is shortened by more than 10 times compared to software decoding.

Penetration delay test:

The penetration delay of network communication and market flow decoding implemented on the FPGA accelerator card was evaluated and tested. The penetration delay is calculated from the time when the data arrives at the Ethernet port on the FPGA side and ends when the Ethernet port on the FPGA side starts to send the market data obtained through STEP-FAST decoding. It includes three parts: Ethernet reception, data decoding, and Ethernet transmission implemented by the hardware on the FPGA side. The specific delay test results of each part are shown in Table 2. The test results show that the market penetration delay on the FPGA side can be as low as 847ns.

Table 2: FPGA-based hardware market analysis solution penetration delay test

Working principle: The present invention designs a hardware system for parsing and processing the STEP-FAST data stream exchange protocol based on FPGA. The STEP hardware parser divides the fields according to the different field types. After the fields are divided, it is convenient to classify the fields of the same type, and then the hardware circuit design is used for centralized and efficient parsing and processing. The FAST hardware parser decodes the divided data in parallel, migrates the heavy-load parsing task of the CPU to the FPGA dedicated hardware processing, optimizes the parallel operation at the circuit level, reduces the CPU load, and the decoding delay can be as low as 33ns, realizing the overall acceleration of market communication and decoding. The FAST hardware parser also includes a number of decoding operator units that match the corresponding fields, which are used to perform FAST protocol parsing and processing on the corresponding fields; and the FPGA acceleration card also includes a CPU module, which is used to send control instructions to the STEP hardware parser and the FAST hardware parser. The encoding processing subunit of the STEP hardware parser encodes the corresponding fields according to the first processing instruction sent by the CPU module to reduce the storage occupancy of the corresponding fields. The CPU module is configured with a reconstruction strategy, which is to construct a field reconstruction sequence according to the chronological order of the identification characters it receives. The reorganization decoding processing unit of the FAST hardware parser receives the reorganized fields in parallel, and according to the second processing instruction sent by the CPU module, sequentially reorganizes several reorganized fields according to the field reconstruction sequence to generate parsed market information and transmit it to the main server to complete the market data parsing process within the specified period.

It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims (7)

1. The ultra-low-delay hardware acceleration quotation data flow analysis system is characterized by comprising a bus interface, an FPGA acceleration card and a main server, wherein the FPGA acceleration card is used for acquiring quotation data information from the bus interface and transmitting the quotation data information to the main server after analysis processing;

The FPGA acceleration card comprises a PHY physical module, an MAC module, a UDP/IP analysis module and a corresponding storage area, wherein the PHY physical module is used for receiving market data information transmitted by the bus interface in a specified period and transmitting the market data information to the MAC module, the MAC module is used for performing CRC32 check on the acquired market data information and transmitting the acquired market data information to the UDP/IP analysis module, and the UDP/IP analysis module is used for performing communication analysis processing on the checked market data information to generate original data;

The FPGA acceleration card further comprises an STEP hardware analyzer, a FAST hardware analyzer and a CPU module, wherein the CPU module is used for sending control instructions to the STEP hardware analyzer and the FAST hardware analyzer, and the STEP hardware analyzer is used for acquiring the original data, performing segmentation processing and encoding processing on the original data, generating a transmission field, and sending the transmission field to a corresponding storage area for caching;

The FAST hardware parser is configured to call the transmission field in parallel from a corresponding storage area, and generate parsing market information after performing parallel FAST protocol parsing and reorganization parsing on the transmission field, so as to send the parsing market information to the main server;

the STEP hardware analyzer comprises a first processing circuit, wherein the first processing circuit comprises a stop bit detection unit and a field segmentation unit;

The stop bit detection unit is used for identifying stop bytes and transmitting the bit sequences of a plurality of stop bytes in the original data to the field segmentation unit;

The field segmentation unit is used for segmenting the original data into a plurality of fields according to the bit sequences of a plurality of stop bytes;

The first processing circuit further comprises a specific character detection unit and an encoding processing unit, wherein the encoding processing unit comprises a plurality of encoding processing subunits;

the specific character detection unit sequentially receives the fields transmitted by the field segmentation unit, and is used for detecting whether identification characters exist in the fields or not and transmitting the fields containing the corresponding identification characters to the corresponding coding processing subunit;

The coding processing subunit is used for coding the corresponding field so as to reduce the memory occupation of the corresponding field;

The specific character detection unit is further configured to sequentially send the identification characters contained in the received fields to the CPU module according to the time sequence, and the CPU module is configured with a reconstruction policy, where the reconstruction policy constructs a field reconstruction sequence according to the time sequence of the received identification characters.

2. The ultra-low latency hardware accelerated market data stream parsing system according to claim 1, wherein: the encoding processing subunit encodes the corresponding fields according to the first processing instruction sent by the CPU module so as to reduce the memory occupation of the corresponding fields and send the generated transmission fields to the corresponding buffer areas for buffering.

3. The ultra-low latency hardware accelerated market data stream parsing system according to claim 2, wherein: the first processing instruction includes a stop byte and an identification character contained in a delete field.

4. An ultra-low latency hardware accelerated market data stream parsing system according to claim 3, wherein: the FAST hardware parser comprises a second processing circuit, the second processing circuit comprises an FSAT protocol decoding processing unit and a reorganization decoding processing unit, the FSAT protocol decoding processing unit comprises a plurality of decoding operator units which are respectively connected with corresponding storage areas, the decoding operator units acquire transmission fields from the corresponding storage areas in parallel and carry out FAST protocol parsing processing on the transmission fields to generate a plurality of reorganization fields, the reorganization decoding processing unit receives the reorganization fields in parallel and reorganizes the reorganization fields in sequence according to a second processing instruction sent by the CPU module to generate analysis quotation information.

5. The ultra-low latency hardware accelerated market data stream parsing system according to claim 4, wherein: the second processing instruction comprises the steps of sequentially adding stop bit bits and corresponding identification bit bits to a plurality of reorganization fields at the first bit position to generate decoding fields, and sequencing the plurality of decoding fields according to the field reorganization sequence.

6. An ultra-low latency hardware accelerated market data flow resolution system according to any of claims 1-5, wherein: the market data information comprises the information of each stroke, the stop bit detection unit detects the original data by taking 1byte as a detection unit, the detection of the highest bit in each detection unit is completed in a single clock period, and when the highest bit is 1, the byte is the stop byte.

7. An ultra-low latency hardware accelerated market data flow resolution system according to any of claims 1-5, wherein: the market data information comprises market snapshot information, the stop bit detection unit detects original data by taking 4byte as a detection unit, the detection of the highest bit in each detection unit is completed in a single clock period, and when the highest bit is 1, the byte is a stop byte.