CN110148623A - Thin film transistor (TFT) and its manufacturing method, device, display base plate and device - Google Patents
Thin film transistor (TFT) and its manufacturing method, device, display base plate and device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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Abstract
This application discloses a kind of thin film transistor (TFT) and its manufacturing method, device, display base plate and devices, belong to technical field of semiconductors.The active layer (012) of thin film transistor (TFT) (01) includes: the source region (0121) successively arranged, channel region (0122) and drain region (0123).Source region (012) includes the polysilicon doped with the first ion, and channel region (0122) includes the polysilicon doped with the second ion, and drain region (0123) includes the polysilicon doped with third ion.Wherein, the first ion and third ion are P-type ion, and the second ion is N-type ion；Alternatively, the first ion and third ion are N-type ion, and the second ion is P-type ion.The application reduces the leakage current of thin film transistor (TFT), improves the display effect of display device.
Description
Technical field
This application involves technical field of semiconductors, in particular to a kind of thin film transistor (TFT) and its manufacturing method, device, display
Substrate and device.
Background technique
Thin film transistor (TFT) is widely used in display device, significantly improves the performance of display device.Film crystal
Pipe includes: grid and active layer, wherein active layer includes: source region, drain region and channel region, and N-type is contained in source region and drain region
Or p-type dopant, and channel region is in eigenstate.
By applying different electrical signals to grid, the turn-on and turn-off of active layer can be controlled, it is thin to reach opening and closing
The purpose of film transistor.Wherein, when applying conducting electric signal to grid, form channel in the channel region of active layer, source region and
Drain region is electrically connected by channel, and active layer is switched on, and thin film transistor (TFT) is in the open state at this time.It is electric when applying shutdown to grid
When signal, the channel in channel region disappears, and source region and drain region can not be electrically connected, and active layer shutdown, thin film transistor (TFT) is at this time
Closed state.
But in the related technology, when applying shutdown electric signal to grid, source region still is able to pass by channel region with drain region
Transmission of electricity stream (electric current is known as leakage current), causes thin-film transistor performance to reduce, influences product characteristic.
Summary of the invention
This application provides a kind of thin film transistor (TFT) and its manufacturing method, device, display base plate and device, can solve existing
Have in technology due to there are leakage current, cause thin film transistor (TFT) can not normal switching-off the problem of, the technical solution is as follows:
In a first aspect, providing a kind of structure of thin film transistor (TFT), the active layer of the thin film transistor (TFT) includes: successively to arrange
Source region, channel region and drain region.
Source region includes the polysilicon doped with the first ion, and channel region includes the polysilicon doped with the second ion, drain region
Including the polysilicon doped with third ion；
Wherein, the first ion and third ion are P-type ion, and the second ion is N-type ion；Alternatively, the first ion
It is N-type ion with third ion, and the second ion is P-type ion.
Optionally, thin film transistor (TFT) further include: gate pattern；Orthographic projection region and channel of the gate pattern on active layer
Area is all overlapped.
Active layer further include: source bonding pad and leakage bonding pad；
Between source region and channel region, source bonding pad includes polysilicon for source bonding pad, alternatively, source bonding pad includes doping
There is the polysilicon of the 4th ion；
Bonding pad is leaked between channel region and drain region, and leakage bonding pad includes polysilicon, alternatively, leakage bonding pad includes doping
There is the polysilicon of the 5th ion；
Wherein, when there is at least one bonding pad doped with ion in source bonding pad and leakage bonding pad, at least
Each bonding pad in one bonding pad, the ion doping that the ion doping concentration of bonding pad is less than reference area in active layer are dense
Degree, reference area is adjacent with bonding pad, and the ion adulterated in reference area and the ion adulterated in bonding pad are P-type ion or N
Type ion.
Second aspect provides a kind of manufacturing method of thin film transistor (TFT), which includes:
Form polysilicon layer；
Different kinds of ions is adulterated into polysilicon layer, obtains active layer；
Wherein, different kinds of ions includes: the first ion, the second ion and third ion；
First ion and third ion are P-type ion, and the second ion is N-type ion；Alternatively, the first ion and third
Ion is N-type ion, and the second ion is P-type ion；
Active layer includes: the source region successively arranged, channel region and drain region；Source region includes the polycrystalline doped with the first ion
Silicon, channel region include the polysilicon doped with the second ion, and drain region includes the polysilicon doped with third ion.
Wherein, different kinds of ions is adulterated into polysilicon layer, obtains active layer, comprising:
The second ion is adulterated into polysilicon layer, obtains channel region；
The first ion and third ion are adulterated into the polysilicon layer doped with the second ion, obtain source region and drain region.
After adulterating the second ion into polysilicon layer, method further include: in the polysilicon layer doped with the second ion
Upper formation gate pattern, and the orthographic projection region of gate pattern on the polysilicon layer is all overlapped with channel region；
The first ion and third ion are adulterated into the polysilicon layer doped with the second ion, comprising: be with gate pattern
Exposure mask adulterates the first ion and third ion into the polysilicon layer doped with the second ion.
It should be noted that different kinds of ions further include: at least one of the 4th ion and the 5th ion ion, active layer
Further include: the corresponding bonding pad of every kind of ion at least one ion；Wherein, the corresponding source bonding pad of the 4th ion is located at source region
Between channel region, source bonding pad includes: the polysilicon doped with the 4th ion；The corresponding leakage bonding pad of 5th ion is located at ditch
Between road area and drain region, leakage bonding pad includes: the polysilicon doped with the 5th ion；For in source bonding pad and leakage bonding pad
Each bonding pad, the ion doping concentration of bonding pad are less than the ion doping concentration of reference area in active layer, reference area with connect
Area is adjacent, and the ion adulterated in reference area and the ion adulterated in bonding pad are P-type ion or N-type ion；
Different kinds of ions is adulterated into polysilicon layer, obtains active layer, further includes:
After adulterating the first ion and third ion into the polysilicon layer doped with the second ion, to doped with first
At least one ion is adulterated in the polysilicon layer of ion, the second ion and third ion, obtain at least one ion every kind from
The corresponding bonding pad of son.
After adulterating the second ion into polysilicon layer, method further include:
Conductive material layer and photoetching agent pattern are sequentially formed on the polysilicon layer doped with the second ion, channel region is located at
In the orthographic projection region of photoetching agent pattern on the polysilicon layer, and the area of channel region is less than photoetching agent pattern on the polysilicon layer
Orthographic projection region area；
Conductive material layer is exposed, developed and solidified using photoetching agent pattern as exposure mask, obtains gate pattern, and grid
The orthographic projection region of pattern on the polysilicon layer is all overlapped with channel region；
Remove photoetching agent pattern；
The first ion and third ion are adulterated into the polysilicon layer doped with the second ion, comprising: in removal photoresist
Before pattern, using photoetching agent pattern as exposure mask, adulterated into the polysilicon layer doped with the second ion the first ion and third from
Son；
At least one ion is adulterated into the polysilicon layer doped with the first ion, the second ion and third ion, comprising:
After removing photoetching agent pattern, using gate pattern as exposure mask, to doped with the first ion, the second ion and third from
At least one ion is adulterated in the polysilicon layer of son.
The third aspect provides a kind of film transistor device, which includes described in first aspect
Thin film transistor (TFT).
Fourth aspect provides a kind of display base plate, which includes thin film transistor (TFT) described in first aspect.
5th aspect, provides a kind of display device, display device includes display base plate described in fourth aspect.
Technical solution bring beneficial effect provided by the present application includes at least:
In the active layer of thin film transistor (TFT) provided in an embodiment of the present invention, channel region doping ion type and source region and
The type of the ion of drain region doping is different, therefore, between channel region and source region is capable of forming a PN junction, channel region and drain region
Between be also capable of forming a PN junction, also, the conducting direction of the two PN junctions is opposite.In the two PN junctions when a conducting,
There is the PN junction of another shutdown, shutdown high potential barrier electronics can not be passed through, at this point, not having electric current transmission, source in channel region
Area can not be electrically connected with drain region.So, leakage current is essentially eliminated, the mesh for improving the display effect of display device is realized
's.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the structural schematic diagram of active layer in a kind of thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic diagram of space-charge region provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of PN junction provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of diode provided in an embodiment of the present invention；
Fig. 5 is the relation curve schematic diagram of the voltage and current of PN junction provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram of thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 7 is a kind of course of work schematic diagram of thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 8 is the course of work schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 9 is the course of work schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 10 is the voltage-current curve schematic diagram of thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 11 is the structural schematic diagram of active layer in another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 12 is the structural schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 13 is a kind of flow chart of the manufacturing method of thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 14 is the flow chart of the manufacturing method of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 15 is a kind of manufacturing process schematic diagram of thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 16 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 17 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 18 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 19 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 20 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 21 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 22 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 23 is the flow chart of the manufacturing method of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 24 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 25 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 26 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 27 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 28 is the manufacturing process schematic diagram of another thin film transistor (TFT) provided in an embodiment of the present invention.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with attached drawing to the application embodiment party
Formula is described in further detail.
In the related technology, the channel region of active layer is in eigenstate in thin film transistor (TFT), turns off electric signal when applying to grid
When, source region and drain region still are able to transmit leakage current by channel region, and thin-film transistor performance is caused to reduce, and influence product spy
Property.The embodiment of the invention provides a kind of thin film transistor (TFT)s, can reduce the leakage current of thin film transistor (TFT).
Illustratively, Fig. 1 is the structural schematic diagram of active layer in a kind of thin film transistor (TFT) provided in an embodiment of the present invention, this is thin
The active layer 012 of film transistor includes: the source region 0121 successively arranged, channel region 0122 and drain region 0123.Source region 0121 includes
Doped with the polysilicon of the first ion, channel region 0122 includes the polysilicon doped with the second ion, and drain region 0123 includes doping
There is the polysilicon of third ion.
Wherein, the first ion and third ion are P-type ion, and the second ion is N-type ion；Alternatively, the first ion
It is N-type ion with third ion, and the second ion is P-type ion.It should be noted that P-type ion is positive ion (such as boron
Ion or arsenic ion or other ions etc.)；N-type ion be negative valency ion (such as phosphonium ion or gallium ion or other from
Son etc.).First ion and third ion can be the same or different, as long as the type of the first ion and third ion is identical
It can.It with the first ion and third ion is boron ion (P-type ion) in the embodiment of the present invention, and the second ion is phosphonium ion (N
Type ion) for.
It should be noted that the semiconductor of doped p-type ion is known as P-type semiconductor, and have in P-type semiconductor a large amount of empty
Cave；It is known as N-type semiconductor doped with the semiconductor of N-type ion, and there are a large amount of electronics in N-type semiconductor.The embodiment of the present invention
Using channel region as P-type semiconductor, and source region and drain region is for N-type semiconductors.When P-type semiconductor is adjacent with N-type semiconductor,
Due to the intersection of P-type semiconductor and N-type semiconductor have electrons and holes concentration difference, electronics from N-type semiconductor to
P-type semiconductor diffusion, so that the region in N-type semiconductor close to intersection loses electronics, and leaves positively charged foreign ion,
The region that electronics is lost in N-type semiconductor is known as the area N；Hole is spread from P-type semiconductor to N-type semiconductor, in P-type semiconductor
Region close to intersection loses hole, and leaves electronegative foreign ion, and the region that hole is lost in P-type semiconductor is claimed
For the area P.At this point, foreign ion positively charged in electronegative foreign ion and the area N in the area P forms space electricity as shown in Figure 2
He Qu, internal electric field is formd in the space-charge region, and the area P is directed toward by the area N in the direction of internal electric field.
The internal electric field formed in the space-charge region can prevent carrier (electrons and holes) from spreading, and enable to N
The hole of type semiconductor region drifts about to P-type semiconductor area, and the electronics in P-type semiconductor area drifts about to N-type semiconductor area, and the sky
Between charged region can change with the diffusion and drift of carrier.When the carrier in P-type semiconductor area and N-type semiconductor area
When drift reaches dynamic equilibrium with diffusion, in the space-charge region that P-type semiconductor area and N-type semiconductor area intersection are formed namely
PN junction shown in Fig. 3.
P-type semiconductor area is directed toward by N-type semiconductor area in internal electric field direction in PN junction, and the conducting direction of PN junction is by p-type half
Conductor is directed toward N-type semiconductor.Structure shown in Fig. 3 including PN junction can be diode shown in Fig. 4, have one-way conduction
Property.Fig. 5 is the relation curve schematic diagram of the voltage and current of PN junction shown in Fig. 3.Abscissa in Fig. 5 is the voltage at PN junction both ends
Ordinate in U (unit can be volt), Fig. 5 is electric current I in PN junction (unit can be ampere), the U in Fig. 5(BR)For PN
The breakdown reverse voltage of knot, when the absolute value of the backward voltage on PN junction is greater than the absolute value of breakdown reverse voltage, PN junction is lost
Go one-way conduction characteristic.As shown in figure 5, applying forward voltage (i.e. current potential of the current potential in the area P higher than the area N) to PN junction both ends
When, PN junction conducting, and there is electric current to pass through in PN junction；Backward voltage (i.e. electricity of the current potential in the area P lower than the area N is applied to PN junction both ends
Position) when, since the breakdown reverse voltage U of PN junction is not achieved in backward voltage(BR), and PN junction has high potential barrier, the load in PN junction
Stream can not overcome the potential barrier mobile, therefore PN junction turns off, and does not have electric current to pass through in PN junction.
As shown in Figure 1, the type for the ion that source region and the drain region of active layer are adulterated is identical in the embodiment of the present invention, and with
The type of the ion adulterated in channel region is different.It can be determined based on the relative theory of PN junction: channel region 0122 and source region 0121
Between be capable of forming the first PN junction, the second PN junction, also, the two PN are also capable of forming between channel region 0122 and drain region 0123
The conducting direction of knot is opposite.When the current potential that source region 0121 is applied is greater than the current potential that drain region 0123 is applied, the first PN junction is led
Logical and the second PN junction turns off；When the current potential that source region 0121 is applied is less than the current potential that drain region 0123 is applied, the first PN junction is closed
Disconnected and the second PN junction is connected.
Optionally, in the active layer 012 in thin film transistor (TFT) provided in an embodiment of the present invention, the ion of source region 0121 is mixed
The ion doping concentration of miscellaneous concentration, the ion doping concentration of channel region 0122 and drain region 0123 can be the same or different, this
Inventive embodiments are without limitation.The embodiment of the present invention is mixed with the ion of the ion doping concentration of source region 0121 and drain region 0123
Miscellaneous concentration is identical, and the ion doping concentration of source region 0121 is greater than for the ion doping concentration of channel region 0122.Certainly, may be used
Ion doping concentration to be source region 0121 is different from the ion doping concentration in drain region 0123, and the ion doping of source region 0121 is dense
The ion doping concentration in degree and drain region 0123 is all larger than the ion doping concentration of channel region 0122.
It should be noted that the potential barrier that usually PN junction is formed when being applied backward voltage is partly led with P-type semiconductor and N-type
Ion doping concentration in body is positively correlated, i.e. the doping concentration of P-type semiconductor or N-type semiconductor is higher, and PN junction is being applied
The potential barrier formed when backward voltage is bigger.So, in embodiments of the present invention N-type semiconductor (i.e. source region and drain region) from
When sub- doping concentration is greater than the ion doping concentration of P-type semiconductor (i.e. channel region), the PN junction of formation is being applied backward voltage
When with sufficiently large potential barrier, which can prevent electronics from passing through, achieve the purpose that substantially eliminate leakage current in channel region.
In conclusion in the active layer of thin film transistor (TFT) provided in an embodiment of the present invention, the class of the ion of channel region doping
Type and the type for the ion that source region and drain region are adulterated are different, therefore, between channel region and source region are capable of forming a PN junction, ditch
Also a PN junction is capable of forming between road area and drain region, also, the conducting direction of the two PN junctions is opposite.One in the two PN junctions
When a conducting, there is the PN junction of another shutdown, shutdown high potential barrier electronics can not be passed through, at this point, without electricity in channel region
Spread defeated, source region can not be electrically connected with drain region.So, leakage current is essentially eliminated, realizes and improves the aobvious of display device
Show the purpose of effect.
Fig. 6 is a kind of structural schematic diagram of thin film transistor (TFT) provided in an embodiment of the present invention.As shown in fig. 6, the film is brilliant
Body pipe includes: active layer 012 and gate pattern 014 in Fig. 1.Orthographic projection region of the gate pattern 014 on active layer 012 with
Channel region 0122 is all overlapped.
It should be noted that when orthographic projection region of the gate pattern 014 on active layer 012 and channel region 0122 are all heavy
It can be that exposure mask is doped polysilicon layer with gate pattern 014 when conjunction, to obtain the source region 0121 and leakage of active layer 012
Area 0123.Without using other exposure masks to be doped polysilicon to obtain the source region 0121 and drain region 0123, simplify thin
The manufacturing process of film transistor.Optionally, orthographic projection region of the gate pattern 014 on active layer 012 and channel region 0122
It can not exclusively be overlapped, the embodiment of the present invention is not construed as limiting this.
With continued reference to FIG. 6, thin film transistor (TFT) can also include gate insulation layer 013, source and drain insulating layer 015 and source and drain pole figure
Case 016.Wherein, gate insulation layer 013, gate pattern 014, source and drain insulating layer 015 and source-drain electrode pattern 016 are along far from active layer
It successively arranges in 012 direction.Source-drain electrode pattern 016 may include: source electrode 0161 and drain electrode 0162, and source electrode 0161 is by running through source
First via hole K1 of source/drain insulation layer 015 and gate insulation layer 013 is electrically connected to source region 0121, and drain electrode 0162 through source and drain by insulating
Second via hole K2 of layer 015 and gate insulation layer 013 is electrically connected to drain region 0123.
Below by the ion adulterated using channel region in thin film transistor (TFT) as P-type ion, and the ion of source region and drain region doping
For N-type ion, the specific work process of thin film transistor (TFT) provided in an embodiment of the present invention is illustrated.
Illustratively, when the grid not into thin film transistor (TFT) applies electric signal, the first PN junction for being formed in active layer and
Second PN junction is as shown in Figure 7.In the case where source region is applied positive potential and drain region is applied negative potential, electric current is flowed to from source region
Drain region, the first PN junction are turned off due to being applied backward voltage (current potential that the current potential in the area P is lower than the area N)；Second PN junction is due to quilt
Apply forward voltage (current potential that the current potential in the area P is higher than the area N) and is connected.Due to the effect of the first PN junction, source region can not be with drain region
Electrical connection, thin film transistor (TFT) is off state.
When applying conducting electric signal (i.e. threshold voltage of the gate source voltage greater than thin film transistor (TFT)) to grid, channel region is leaned on
The regional Electronic concentration of nearly grid increases to form channel, as shown in Figure 8.At this point, empty due to electron concentration height in channel
Cave concentration is low, can not form PN junction with source region or drain region, therefore, source region can pass through the channel formed in channel region and drain region
Electrical connection, thin film transistor (TFT) are opened.
When applying shutdown electric signal (i.e. gate source voltage is less than threshold voltage) to grid, channel region is close to the region of grid
Assemble a large amount of holes, as shown in Figure 9.Since the intersection electron concentration in source region and drain region is high and hole concentration is higher, formation
First PN junction has higher potential barrier, and therefore, under the action of backward voltage, the first PN junction is turned off, and does not leak electricity in channel region
Spread defeated, source region can not be electrically connected with drain region, at this point, thin film transistor (TFT) turns off.
Applying when conducting perhaps turns off electric signal thin film transistor (TFT) to grid can be with to the conducting or shutdown of electric current effect
It is intuitively showed by voltage-current curve figure as shown in Figure 10, abscissa is that (unit can be volt to gate source voltage V in Figure 10
It is special), ordinate is electric current I in channel region (unit can be ampere).Also, with the threshold voltage of thin film transistor (TFT) in Figure 10
For (referred to as: Vth) is 1 volt.
As shown in Figure 10, when applying conducting electric signal to grid, gate source voltage (referred to as: Vgs) is greater than threshold voltage 1
Volt, thin film transistor (TFT) are connected, and the electric current in channel region significantly increases, and as gate source voltage continues to increase, the electricity in channel region
Stream quickly increases.When applying shutdown electric signal to grid, gate source voltage is less than 1 volt of threshold voltage, and thin film transistor (TFT) turns off, this
When channel region in electric current as low as 10-11A can be ignored.It can be seen that thin film transistor (TFT) provided by the present application is turning off
When leakage current is substantially not present, the shutdown effect of thin film transistor (TFT) is preferable.
In addition, when the ion of channel region doping in thin film transistor (TFT) is P-type ion, and source region and the ion of drain region doping are
When N-type ion, the course of work of thin film transistor (TFT) is similar with above situation, and this will not be repeated here for the embodiment of the present invention.
Optionally, the active layer in above-described embodiment in thin film transistor (TFT) be active layer shown in FIG. 1 for, it is certainly, thin
Active layer in film transistor can also be different from the structure of the active layer in Fig. 1.
Illustratively, Figure 11 is the structural schematic diagram of active layer in another thin film transistor (TFT) provided in an embodiment of the present invention.
As shown in figure 11, on the basis of Fig. 1, active layer 012 can also include: source bonding pad 0124 and leakage bonding pad 0125.Source connects
Area 0124 is met between source region 0121 and channel region 0122.Leakage bonding pad 0125 be located at channel region 0122 and drain region 0123 it
Between.
Source bonding pad 0124 may include polysilicon, alternatively, source bonding pad 0124 includes the polycrystalline doped with the 4th ion
Silicon.Leaking bonding pad 0125 includes polysilicon, alternatively, leakage bonding pad 0125 includes the polysilicon doped with the 5th ion.
It should be noted that assuming source bonding pad and leaking at least one (such as one existed in bonding pad doped with ion
Or multiple) bonding pad, for example source bonding pad is doped with the 4th ion and leakage bonding pad undopes, or leakage bonding pad doping the 5th
Ion and source bonding pad undope or the 4th ion is adulterated in source bonding pad and the 5th ion is adulterated in leakage bonding pad.At this point, for
Each bonding pad at least one bonding pad, the ion that the ion doping concentration of bonding pad is less than reference area in active layer are mixed
Miscellaneous concentration, reference area is adjacent with bonding pad, and the ion adulterated in reference area and the ion adulterated in bonding pad are P-type ion
Or N-type ion.
For example, if active layer includes source bonding pad, and source bonding pad is doped with the 4th ion, then the reference area of source bonding pad
It can be the source region or channel region in active layer.Wherein, when source region doped p-type ion and channel region doped N-type ion, the
Four ions can be P-type ion, and its ion doping concentration is less than source region intermediate ion doping concentration；Or the 4th ion can be
N-type ion, and its ion doping concentration is less than channel region intermediate ion doping concentration.When source region doped N-type ion and channel region is mixed
When miscellaneous P-type ion, the 4th ion can be N-type ion, and its ion doping concentration is less than source region intermediate ion doping concentration, or
4th ion can be P-type ion, and its ion doping concentration is less than channel region ion doping concentration.
If active layer includes leakage bonding pad, and bonding pad is leaked doped with the 5th ion, then the reference area for leaking bonding pad can be with
For in active layer channel region or drain region.Wherein, when channel region doped p-type ion and drain region doped N-type ion, the 5th from
Son can be P-type ion, and its ion doping concentration is less than channel region intermediate ion doping concentration；Or the 5th ion can be N
Type ion, and its ion doping concentration is less than drain region intermediate ion doping concentration.When channel region doped N-type ion and P is adulterated in drain region
When type ion, the 5th ion can be for N-type ion and its ion doping concentration is less than channel region intermediate ion doping concentration.Or the
Five ions can be P-type ion, and its ion doping concentration is less than drain region intermediate ion doping concentration.
To have source bonding pad and leakage bonding pad, and source bonding pad and leakage bonding pad in active layer in the embodiment of the present invention
Reference area is channel region, for the ion of source bonding pad, leakage bonding pad and channel region doping is P-type ion.
It should be noted that being equivalent to when source bonding pad is added between source region and channel region in source region and channel region
It joined the area I (intrinsic region) between the area P and the area N of the PN junction of formation, so as to form a PIN junction.When in drain region and channel
When leakage bonding pad being added between area, being equivalent between the area P and the area N of the PN junction formed between drain region and channel region joined I
Area, so as to form a PIN junction.There is one-way conduction since PIN junction is same as PN junction, when active layer has source
When bonding pad and leakage bonding pad, thin film transistor (TFT) is in the off case in channel region substantially without leakage current.Simultaneously because intrinsic
The increase in area also can be reduced the compound of electron hole pair (electronics comes from the area N, and hole comes from the area P), exist to increase transistor
The number of the carrier flowed in active layer under ON state promotes transistor in on-state current.
The structure of thin film transistor (TFT) where active layer shown in Figure 11 is shown in Fig.12.As shown in figure 12, this is thin
Film transistor further includes gate insulation layer 013, source and drain insulating layer 015 and source-drain electrode pattern 016.Gate insulation layer 013, source and drain insulating layer
015 and the arrangement mode of source-drain electrode pattern 016 can be with reference to gate insulation layer in Fig. 6, source and drain insulating layer and source-drain electrode pattern structure
Arrangement mode, this will not be repeated here for the embodiment of the present invention.
In addition, in the embodiment of the present invention by taking the structure of thin film transistor (TFT) is top gate structure shown in Fig. 6 and Figure 12 as an example, it can
The structure of selection of land, thin film transistor (TFT) can also be different from top gate structure shown in Fig. 6 or Figure 12, as the structure of thin film transistor (TFT) can
Think bottom grating structure.
In conclusion active layer has source bonding pad and leakage bonding pad in thin film transistor (TFT) provided in an embodiment of the present invention.
So, it will form PIN junction in bonding pad.Also, PIN junction one-way conduction and potential barrier linearly increases, can turn off
Shi Youxiao prevents electronics from passing through, and substantially eliminates leakage current, improves the display effect of display device.PIN junction can be fine simultaneously
Control on-state current decaying, the damage of thin film transistor (TFT) is reduced, the service life of thin film transistor (TFT) is improved.
Illustratively, Figure 13 is a kind of flow chart of the manufacturing method of thin film transistor (TFT) provided in an embodiment of the present invention, the system
The method of making can be used to manufacture thin film transistor (TFT) provided in an embodiment of the present invention, the thin film transistor (TFT) as shown in Fig. 6 or Figure 12.Such as
Shown in Figure 13, which includes:
Step 1301 forms polysilicon layer.
Step 1302 adulterates different kinds of ions into polysilicon layer, obtains active layer.
Wherein, different kinds of ions includes: the first ion, the second ion and third ion.First ion and third ion are P
Type ion, and the second ion is N-type ion；Alternatively, the first ion and third ion are N-type ion, and the second ion is p-type
Ion.Active layer includes: the source region successively arranged, channel region and drain region；Source region includes the polysilicon doped with the first ion, ditch
Road area includes the polysilicon doped with the second ion, and drain region includes the polysilicon doped with third ion.
In conclusion in thin film transistor (TFT) manufactured by method provided in an embodiment of the present invention, the ion of channel region doping
Type and source region and drain region doping ion type it is different, therefore, between channel region and source region be capable of forming the first PN
Knot, is also capable of forming the second PN junction, also, the first PN junction is opposite with the conducting direction of the second PN junction between channel region and drain region.
In the two PN junctions when a conducting, there is the PN junction of another shutdown, shutdown high potential barrier electronics can not be passed through, at this point,
There is no electric current transmission in channel region, source region can not be electrically connected with drain region.So, leakage current is essentially eliminated, realizes and mentions
The purpose of the display effect of high display device.
Figure 14 is the flow chart of the manufacturing method of another thin film transistor (TFT) provided in an embodiment of the present invention, and this method can be with
For manufacturing thin film transistor (TFT) shown in fig. 6, as shown in figure 14, this method may include:
Step 1401 forms polysilicon layer.
When forming polysilicon layer, amorphous silicon material layers can be formed first on underlay substrate, later to the amorphous silicon
Material layers are handled to obtain polysilicon material layers.Polysilicon material layers are handled using a patterning processes again later
Obtain polysilicon layer 110 as shown in figure 15.
Wherein, on underlay substrate formed amorphous silicon material layers when, can using coating, physical vapour deposition (PVD) (English:
Physical Vapor Deposition；Referred to as: PVD) or chemical vapor deposition is (English: Chemical Vapor
Deposition；One layer of amorphous silicon material is formed the methods of referred to as: CVD) on underlay substrate, obtains amorphous silicon material layers.Its
In, PVD includes: the physical deposition methods such as magnetron sputtering or thermal evaporation, and CVD includes gas ions enhancing chemical vapour deposition technique (English
Text: Plasma Enhanced Chemical Vapor Deposition；The chemical depositions such as referred to as: PECVD).
Step 1402 forms the first pattern on the polysilicon layer, and the first pattern has hollowed out area.
After a polysilicon layer is formed, the first pattern 210 as shown in figure 16 can be formed on the polysilicon layer.Also,
First pattern 210 has hollowed out area 2101, and the intermediate region in polysilicon layer can pass through the hollowed out area in the first pattern
2101 is exposed.
Illustratively, the material of first pattern can be photoresist, metal or other materials.
On the one hand, it if the material of the first pattern is photoresist, can be applied on the polysilicon layer first in step 1402
Cover photoresist layer.Later, the photoresist layer is exposed using mask plate, then the photoresist layer after exposure is shown
Shadow, to obtain the first pattern.
It on the other hand, can shape on the polysilicon layer first in step 1402 if the material of the first pattern is metal
At metal material layer.And then metal material layer is handled using a patterning processes, to obtain the first pattern.
It should be noted that if the first pattern is above-mentioned other materials, then the process of the first pattern of other materials is formed
Can be with reference to the process for the first pattern for forming metal material, this will not be repeated here for the embodiment of the present invention.
Step 1403, using the first pattern as exposure mask, into polysilicon layer not by the first pattern cover part doping second
Ion obtains channel region.
After forming the first pattern, there is the region not covered by the first pattern in polysilicon layer.At this point, in step 1403
In the region in polysilicon layer can be doped using the first pattern as exposure mask, obtain channel region 0122 as shown in figure 17.
There is also the regions (region 01221 in such as Figure 17) not covered by the first pattern in polysilicon layer, in step 1403, polycrystalline
The region in silicon layer is simultaneously undoped.
Optionally, the second ion can be P-type ion (such as boron ion or arsenic ion or other ions) or N-type
Ion (such as phosphonium ion or gallium ion or other ions).In the embodiment of the present invention by taking the second ion is P-type ion as an example.
Step 1404, the first pattern of removal.
After obtaining channel region, the first pattern can be removed using the method for removing, obtained structure is as shown in figure 18.
Step 1405 sequentially forms gate insulator material layers and grid figure on the polysilicon layer doped with the second ion
Case.
Illustratively, gate insulator material layers and conductive material layer can be sequentially formed on the polysilicon layer first；And then
Conductive material layer is handled using a patterning processes, to obtain gate pattern.
Wherein, the material of gate insulator material layers can be the composite etc. of silica, nitrogen oxide or both, lead
The material of body material layers may include metal or graphene etc..
The method for forming gate insulator material layers and conductive material layer can be with reference to formation amorphous silicon material in step 1401
The method of layer；The process for forming gate pattern using a patterning processes to conductive material layer, can refer to and adopt in step 1401
Polysilicon material layers are handled to obtain the process of polysilicon layer with a patterning processes.
Available gate insulator material layers 111 and gate pattern 014 as shown in figure 19 in step 1405.Grid is exhausted
Edge material layers 111 cover polysilicon layer, and the orthographic projection region of gate pattern 014 on the polysilicon layer and channel region 0122 are all heavy
It closes.
In practical manufacturing process, the orthographic projection region of grid on the polysilicon layer can also not be complete weight with channel region
It closes.For example, the size in the orthographic projection region of grid on the polysilicon layer can exist less times greater than the size or grid of channel region
The size in the orthographic projection region on polysilicon layer can be slightly less than the size etc. of channel region, and the embodiment of the present invention is no longer done excessively
Explanation.Illustratively, the size of grid orthographic projection region on the polysilicon layer and channel region difference may range from 0 micron~1
Micron or 0.6 micron to 0.8 micron etc..Wherein, the size of any region are as follows: the external diameter of a circle in the region.
Step 1406, using gate pattern as exposure mask, adulterated into the polysilicon layer doped with the second ion the first ion and
Third ion, obtains source region and drain region.
Since in step 1405, the orthographic projection of the gate pattern of formation on the polysilicon layer covers channel region, therefore, right
When region in polysilicon layer other than channel region is doped, channel region can be blocked with gate pattern and be doped.In step
In 1406, using the gate pattern as mask, the first ion and third ion are adulterated into the polysilicon layer doped with the second ion,
Obtain source region 0121 and drain region 0123 as shown in figure 20.Also, as shown in figure 20, source region 0121, channel region in active layer 012
0122 and drain region 0123 successively arrange.
It should be noted that when the second ion adulterated in step 1403 is P-type ion, adulterate in step 1406 the
One ion and third ion are N-type ion；When the second ion adulterated in step 1403 is N-type ion, in step 1406
The first ion and third ion of doping are P-type ion.
Step 1407 forms source and drain isolation material layer on the underlay substrate for be formed with gate pattern.
The process for forming source and drain isolation material layer can be with reference to the process for forming non-polycrystalline silicon material layer in step 1401, this
This will not be repeated here for inventive embodiments.The source and drain isolation material layer 112 formed in step 1407 can be as shown in figure 21, the source
It leaks isolation material layer 112 and covers active layer 012.
Step 1408 forms the first via hole and the second via hole in gate insulation material layers and source and drain isolation material layer, obtains
Gate insulation layer and source and drain insulating layer.
After forming source and drain isolation material layer, such as Figure 22 need to be also formed in gate insulation material layers and source and drain isolation material layer
Shown in the first via hole K1 and the second via hole K2, obtain gate insulation layer 013 and source and drain insulating layer 015.Wherein, the first via hole K1 and
Second via hole K2 runs through gate insulation layer 013 and source and drain insulating layer 015, and the source region in the first via hole K1 connection active layer 012
0121, the second via hole K2 are connected to the drain region 0123 in active layer 012.
Step 1409 forms source-drain electrode pattern on source and drain insulating layer.
After obtaining gate insulation layer and source and drain insulating layer, source-drain electrode pattern can be formed on source and drain insulating layer.In step
Available thin film transistor (TFT) 01 as shown in FIG. 6 after 1409, the source-drain electrode pattern in the thin film transistor (TFT) 01 includes: source electrode figure
Case 0161 and drain pattern 0162.Wherein, source electrode pattern 0161 is electrically connected by the first via hole K1 with source region 0121, drain pattern
0162 is electrically connected by the second via hole K2 with drain region 0123.
It should be noted that adulterated into polysilicon layer in the embodiment of the present invention using gate pattern as mask the first ion and
(details please refer to step 1406) to third ion.Alternatively it is also possible to not adulterated using gate pattern as exposure mask into polysilicon layer
First ion and third ion, and the step of adulterating into polysilicon layer the first ion and third ion, can not be located at step
1406。
For example, step 1406 can not be executed and between step 1404 and step 1405, can doped with second from
Mask is formed on the polysilicon layer of son, and is gone again later by the exposure mask to the first ion of doping polycrystalline silicon layer and third ion
Except the exposure mask.
For another example, step 1406 can not be executed, and after forming gate insulator material layers and is forming grid
Before pattern, mask can be formed in gate insulator material layers, and by the exposure mask to the first ion of doping polycrystalline silicon layer and
Third ion removes the exposure mask again later.
For another example, step 1406 can not be executed, and between step 1407 and step 1408, can insulated in source and drain
Mask is formed in material layers, and is removed this again later to the first ion of doping polycrystalline silicon layer and third ion by the exposure mask and covered
Film.
In conclusion in thin film transistor (TFT) manufactured by method provided in an embodiment of the present invention, the ion of channel region doping
Type and source region and drain region doping ion type it is different, therefore, between channel region and source region be capable of forming the first PN
Knot, is also capable of forming the second PN junction, also, the first PN junction is opposite with the conducting direction of the second PN junction between channel region and drain region.
In the two PN junctions when a conducting, there is the PN junction of another shutdown, shutdown high potential barrier electronics can not be passed through, at this point,
There is no electric current transmission in channel region, source region can not be electrically connected with drain region.So, leakage current is essentially eliminated, realizes and mentions
The purpose of the display effect of high display device.
Figure 23 is the flow chart of the manufacturing method of another thin film transistor (TFT) provided in an embodiment of the present invention, for manufacturing figure
Thin film transistor (TFT) shown in 12, as shown in figure 23, which includes:
Step 2301 forms polysilicon layer.
Step 2301 can be with reference to the step 1401 in Figure 14, and this will not be repeated here for the embodiment of the present invention.
Step 2302 forms the first pattern on the polysilicon layer, and the first pattern has hollowed out area.
Step 2302 can be with reference to the step 1402 in Figure 14, and this will not be repeated here for the embodiment of the present invention.
Step 2303, using the first pattern as exposure mask, into polysilicon layer not by the first pattern cover part doping second
Ion obtains channel region.
Step 2303 can be with reference to the step 1403 in Figure 14, and this will not be repeated here for the embodiment of the present invention.
Step 2304, the first pattern of removal.
Step 2304 can be with reference to the step 1404 in Figure 14, and this will not be repeated here for the embodiment of the present invention.
Step 2305 sequentially forms gate insulation material layers, conductive material layer on the polysilicon layer doped with the second ion
And photoetching agent pattern.
In step 2305, gate insulation material layers, conduction material are sequentially formed on the polysilicon layer doped with the second ion
Matter layer and photoresist layer.And then the photoresist layer is exposed and is developed, to obtain photoetching agent pattern.Wherein, grid are formed
The method of isolation material layer, conductive material layer and photoresist layer can form amorphous silicon material layers with reference to step 1401 in Figure 14
Method.
Gate insulation material layers 111, conductive material layer 121 and the photoetching agent pattern 211 formed in step 2305 can be such as figure
Shown in 24.Wherein, the photoetching agent pattern 211 of formation covers the partial region of conductive material layer 121, at this point, conductive material layer 121
In have be photo-etched glue pattern 211 covering the area of coverage 1211, and be not photo-etched glue pattern 211 covering uncovering area
1212.In addition, the orthographic projection region of photoetching agent pattern 211 on the polysilicon layer is the partial region in polysilicon layer, channel region
0122 is located in the orthographic projection region of photoetching agent pattern 211 on the polysilicon layer, and the area of channel region 0122 is less than photoresist
The area in the orthographic projection region of pattern 211 on the polysilicon layer.
Step 2306, using photoetching agent pattern as exposure mask, conductive material layer is exposed, developed and solidified, grid is obtained
Pattern, and the orthographic projection region of gate pattern on the polysilicon layer is all overlapped with channel region.
In step 2305, conductive material layer can be exposed and be developed using photoetching agent pattern as mask first, with
The uncovering area (uncovering area 1212 in such as Figure 24) of glue pattern covering is not photo-etched in removal conductive material layer.Also, it leads
The area of coverage (area of coverage 1211 in such as Figure 24) that the covering of glue pattern is photo-etched in body material layers is retained.
Later, the area of coverage 1211 in conductive material layer can be solidified, so that the size of the area of coverage 1211 reduces
And gate pattern 014 as shown in figure 25 is formed, and orthographic projection region of the gate pattern 014 on crystal silicon layer and channel region 0122
All it is overlapped.
Step 2307, using photoetching agent pattern as exposure mask, the first ion is adulterated into the polysilicon layer doped with the second ion
With third ion, source region and drain region are obtained.
Gate pattern is formd in step 2306, later using photoresist as mask, to the polycrystalline doped with the second ion
The first ion and third ion are adulterated in silicon layer, obtain source region and drain region as shown in figure 26.At this point, polysilicon layer include: according to
Source region 0121, channel region 0122 and the drain region 0123 of minor tick arrangement.Also, have one between source region 0121 and channel region 0122
A undoped area 01211 has another undoped with area 01231 between drain region 0123 and channel region 0122.
Step 2308, removal photoetching agent pattern.
After obtaining source region and drain region, photoetching agent pattern is removed, obtained structure is as shown in figure 27.
Step 2309, using gate pattern as exposure mask, to the polysilicon doped with the first ion, the second ion and third ion
The second ion is adulterated in layer, obtains the source bonding pad doped with the second ion, and the leakage bonding pad doped with the second ion.
Before step 2309, polysilicon layer includes: source region, drain region, channel region and two undoped with areas, also, grid figure
Case only covers channel region.In step 2309, can using gate pattern as mask, to two undoped with areas adulterate second from
Son, available source bonding pad 0124 as shown in figure 28 and leakage bonding pad 0125.
Step 2310 forms source and drain isolation material layer on the underlay substrate for be formed with gate pattern.
Step 2310 can be with reference to the step 1406 in Figure 14, and this will not be repeated here for the embodiment of the present invention.
Step 2311 forms the first via hole and the second via hole in gate insulation material layers and source and drain isolation material layer, obtains
Gate insulation layer and source and drain insulating layer.
Step 2311 can be with reference to the step 1407 in Figure 14, and this will not be repeated here for the embodiment of the present invention.
Step 2312 forms source-drain electrode pattern on source and drain insulating layer.
Step 2312 can be with reference to the step 1408 in Figure 14, and this will not be repeated here for the embodiment of the present invention.In step 2312
Later, thin film transistor (TFT) as shown in figure 12 can be obtained.
Further, photoetching agent pattern can not also be removed in step 2308, but by photoetching in step 2308
Glue pattern carries out ashing processing, so that being reduced in size to for photoetching agent pattern just covers gate pattern.Later, in step 2309
In can be using ashing treated the photoetching agent pattern as mask, into the polysilicon layer after the first ion of doping and the second ion
One or more bonding pad Doped ions.And then removal ashing treated photoetching agent pattern.
It should be noted that in embodiment shown in Figure 23 by source bonding pad and leakage bonding pad doped with ion for,
At this point, needing to two in step 2309 undoped with the equal Doped ions in area.Alternatively it is also possible to source bonding pad or leakage connection
Area is doped with ion, at this point, in step 2309, it is only necessary to one in two undoped areas undoped with area's Doped ions to obtain
Another to a bonding pad in source bonding pad and leakage bonding pad, and in two undoped areas is undoped with the bonding pad Qu Weiyuan
With another bonding pad in leakage bonding pad.Again alternatively it is also possible to which source bonding pad and leakage bonding pad are undoped ion, this
When, without executing above-mentioned steps 2309, and two formed in step 2308, undoped in area, one connects undoped with Qu Weiyuan
Area is met, another is leakage bonding pad undoped with area.
In embodiment shown in Figure 23 also by taking the reference area of source bonding pad and leakage bonding pad is channel region as an example, at this point,
It to the ion that each undoped area is adulterated is the second ion in step 2309.Optionally, when source bonding pad is doped with ion
When, the reference area of source bonding pad may not be channel region (for example reference area is source region), at this point, the Xiang Yuanlian in step 2309
The ion for connecing the corresponding undoped area's doping in area is the first ion.When leaking bonding pad doped with ion, the reference of bonding pad is leaked
Area may not be channel region (for example reference area is drain region), at this point, corresponding undoped to leakage bonding pad in step 2309
The ion of area's doping is third ion.
In addition, in embodiment shown in Figure 23 by taking active layer includes source bonding pad and leakage bonding pad as an example, it is of course also possible to
It is that active layer only includes source bonding pad and leaks a bonding pad in bonding pad, the embodiment of the present invention is not construed as limiting this.
It should be noted that the step of adulterating the first ion and third ion in the embodiment of the present invention into polysilicon layer,
Step 2307 can not be located at.
For example, step 2307 can not be executed and between step 2304 and step 2305, can doped with second from
Mask is formed on the polysilicon layer of son, and is gone again later by the exposure mask to the first ion of doping polycrystalline silicon layer and third ion
Except the exposure mask.
For another example, step 2307 can not be executed, and after forming gate insulator material layers and is forming conduction
Before material layers, mask can be formed in gate insulator material layers, and passes through the exposure mask to the first ion of doping polycrystalline silicon layer
With third ion, the exposure mask is removed again later.
For another example, step 2307 can not be executed, and between step 2310 and step 2311, can insulated in source and drain
Mask is formed in material layers, and is removed this again later to the first ion of doping polycrystalline silicon layer and third ion by the exposure mask and covered
Film.
In conclusion active layer has active connection in thin film transistor (TFT) manufactured by method provided in an embodiment of the present invention
Area and leakage bonding pad.So, it will form PIN junction in bonding pad.Also, PIN junction one-way conduction and potential barrier linearly increases
It is long, effectively electronics can be prevented to pass through when off, substantially eliminate leakage current, improve the display effect of display device.Simultaneously
PIN junction can be good at controlling the decaying of on-state current, reduces to the damage of thin film transistor (TFT), improves making for thin film transistor (TFT)
Use the service life.
The embodiment of the invention provides a kind of film transistor device, film transistor device includes that the embodiment of the present invention mentions
The thin film transistor (TFT) (thin film transistor (TFT) as shown in Fig. 6 or 12) of confession.The film transistor device can for electronic component or
Chip etc..
The embodiment of the invention provides a kind of display base plate, display base plate includes film crystal provided in an embodiment of the present invention
It manages (thin film transistor (TFT) as shown in Fig. 6 or 12).
The embodiment of the invention provides a kind of display device, display device includes display base provided in an embodiment of the present invention
Plate.
Display device can be with are as follows: liquid crystal display panel, Electronic Paper, organic LED panel, light-emitting-diode panel, hand
Any product having a display function such as machine, tablet computer, television set, display, laptop, Digital Frame, navigator
Or component.
It should be pointed out that in the accompanying drawings, for the size that clearly may be exaggerated layer and region of diagram.And it can be with
Understand, when element or layer be referred in another element or layer "upper", it can be directly in other elements, or may exist
Intermediate layer.Additionally, it is appreciated that it can be directly at other when element or layer be referred in another element or layer "lower"
Under element, or there may be the layer of more than one centre or elements.In addition, it is to be appreciated that when layer or element are referred to as
Two layers or two elements " between " when, the layer that it can be only between two layers or two elements, or there may also be one
Above middle layer or element.Similar reference marker indicates similar element in the whole text.
In the disclosure, term " first ", " second ", " third " and " the 4th " are used for description purposes only, and cannot understand
For indication or suggestion relative importance.Term " multiple " refers to two or more, unless otherwise restricted clearly.
It should be noted that embodiment of the method provided in an embodiment of the present invention can be with corresponding TFT embodiment
Mutually reference, it is not limited in the embodiment of the present invention.The sequencing of embodiment of the method step provided in an embodiment of the present invention
It is able to carry out appropriate adjustment, step also according to circumstances can accordingly be increased and decreased, anyone skilled in the art
In the technical scope disclosed by the present invention, the method that can readily occur in variation, should be covered by the protection scope of the present invention,
Therefore it repeats no more.
The foregoing is merely the alternative embodiments of the application, not to limit the application, it is all in spirit herein and
Within principle, any modification, equivalent replacement, improvement and so on be should be included within the scope of protection of this application.
Claims (11)
1. a kind of thin film transistor (TFT), which is characterized in that the active layer (012) of the thin film transistor (TFT) (01) includes: successively to arrange
Source region (0121), channel region (0122) and drain region (0123)；
The source region (0121) includes the polysilicon doped with the first ion, the channel region (0122) include doped with second from
The polysilicon of son, the drain region (0123) includes the polysilicon doped with third ion；
Wherein, first ion and the third ion are P-type ion, and second ion is N-type ion；Alternatively,
First ion and the third ion are N-type ion, and second ion is P-type ion.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the thin film transistor (TFT) further include: gate pattern
(014)；The orthographic projection region of the gate pattern (014) on the active layer is all overlapped with the channel region (0122).
3. thin film transistor (TFT) according to claim 1 or 2, which is characterized in that the active layer further include: source bonding pad
(0124) and bonding pad (0125) is leaked；
The source bonding pad (0124) is between the source region (0121) and the channel region (0122), the source bonding pad
It (0124) include polysilicon, alternatively, the source bonding pad (0124) includes the polysilicon doped with the 4th ion；
The leakage bonding pad (0125) is between the channel region (0122) and the drain region (0123), the leakage bonding pad
It (0125) include polysilicon, alternatively, leakage bonding pad (0125) includes the polysilicon doped with the 5th ion；
Wherein, when the source bonding pad (0124) and middle at least one company existed doped with ion of leakage bonding pad (0125)
When meeting area, for each bonding pad at least one described bonding pad, the ion doping concentration of the bonding pad is less than described
The ion doping concentration of reference area in active layer, the reference area is adjacent with the bonding pad, and adulterated in the reference area
The ion adulterated in ion and the bonding pad is P-type ion or N-type ion.
4. a kind of manufacturing method of thin film transistor (TFT), which is characterized in that for any film of manufacturing claims 1 to 3
Transistor, which comprises
Form polysilicon layer；
Different kinds of ions is adulterated into the polysilicon layer, obtains active layer；
Wherein, the different kinds of ions includes: the first ion, the second ion and third ion；
First ion and the third ion are P-type ion, and second ion is N-type ion；Alternatively, described
One ion and the third ion are N-type ion, and second ion is P-type ion；
The active layer includes: the source region successively arranged, channel region and drain region；The source region includes doped with first ion
Polysilicon, the channel region includes the polysilicon doped with second ion, and the drain region includes doped with the third
The polysilicon of ion.
5. according to the method described in claim 4, being had it is characterized in that, adulterating different kinds of ions into the polysilicon layer
Active layer, comprising:
Second ion is adulterated into the polysilicon layer, obtains the channel region；
First ion and the third ion are adulterated into the polysilicon layer doped with second ion, obtain institute
State source region and the drain region.
6. according to the method described in claim 5, it is characterized in that, adulterated into the polysilicon layer second ion it
Afterwards, the method also includes: gate pattern, and the gate pattern are formed on the polysilicon layer doped with second ion
Orthographic projection region on the polysilicon layer is all overlapped with the channel region；
First ion and the third ion are adulterated in the polysilicon layer to doped with second ion, are wrapped
It includes: using the gate pattern as exposure mask, first ion is adulterated into the polysilicon layer doped with second ion
With the third ion.
7. according to the method described in claim 5, it is characterized in that, the different kinds of ions further include: the 4th ion and the 5th from
At least one of son ion, the active layer further include: the corresponding bonding pad of every kind of ion in at least one ion；Its
In, for the corresponding source bonding pad of the 4th ion between the source region and the channel region, the source bonding pad includes: to mix
The miscellaneous polysilicon for having the 4th ion；The corresponding leakage bonding pad of 5th ion be located at the channel region and the drain region it
Between, the leakage bonding pad includes: the polysilicon doped with the 5th ion；For the source bonding pad and the leakage bonding pad
In each bonding pad, the ion doping concentration of the bonding pad is less than the ion doping concentration of reference area in the active layer,
The reference area is adjacent with the bonding pad, and the ion adulterated in the reference area and the ion adulterated in the bonding pad are equal
For P-type ion or N-type ion；
Different kinds of ions is adulterated into the polysilicon layer, obtains active layer, further includes:
After adulterating first ion and the third ion into the polysilicon layer doped with second ion,
Adulterated into the polysilicon layer doped with first ion, second ion and the third ion it is described it is at least one from
Son obtains the corresponding bonding pad of every kind of ion at least one ion.
8. the method according to the description of claim 7 is characterized in that adulterated into the polysilicon layer second ion it
Afterwards, the method also includes:
Conductive material layer and photoetching agent pattern, the channel region are sequentially formed on the polysilicon layer doped with second ion
Positioned at the photoetching agent pattern in the orthographic projection region on the polysilicon layer, and the area of the channel region is less than the light
The area in orthographic projection region of the photoresist pattern on the polysilicon layer；
The conductive material layer is exposed, developed and solidified using the photoetching agent pattern as exposure mask, obtains gate pattern, and
Orthographic projection region of the gate pattern on the polysilicon layer is all overlapped with the channel region；
Remove the photoetching agent pattern；
First ion and the third ion are adulterated in the polysilicon layer to doped with second ion, are wrapped
It includes: before removing the photoetching agent pattern, using the photoetching agent pattern as exposure mask, to doped with described in second ion
First ion and the third ion are adulterated in polysilicon layer；
Described at least one is adulterated into the polysilicon layer doped with first ion, second ion and the third ion
Kind ion, comprising:
After removing the photoetching agent pattern, using the gate pattern as exposure mask, to doped with first ion, described second
At least one ion is adulterated in the polysilicon layer of ion and the third ion.
9. a kind of film transistor device, which is characterized in that the film transistor device includes any institute of claims 1 to 3
The thin film transistor (TFT) stated.
10. a kind of display base plate, which is characterized in that the display base plate includes any film crystal of claims 1 to 3
Pipe.
11. a kind of display device, which is characterized in that the display device includes display base plate described in any one of claim 10.
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| CN201910464787.XA CN110148623A (en) | 2019-05-30 | 2019-05-30 | Thin film transistor (TFT) and its manufacturing method, device, display base plate and device |
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| CN201910464787.XA CN110148623A (en) | 2019-05-30 | 2019-05-30 | Thin film transistor (TFT) and its manufacturing method, device, display base plate and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900210A (en) * | 2020-08-11 | 2020-11-06 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and display device |
| CN113113354A (en) * | 2021-03-18 | 2021-07-13 | 武汉华星光电技术有限公司 | Optical device, preparation method thereof and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5659183A (en) * | 1995-12-06 | 1997-08-19 | Micron Technology, Inc. | Thin film transistor having a drain offset region |
| CN101236904A (en) * | 2008-02-29 | 2008-08-06 | 上海广电光电子有限公司 | Making method for multi-crystal silicon film transistor with the slight adulterated leakage pole area |
| US20110198607A1 (en) * | 2010-02-15 | 2011-08-18 | Nec Lcd Technologies, Ltd. | Thin-film transistor, method of manufacturing the same, display device, and electronic apparatus |
| CN107275390A (en) * | 2017-06-30 | 2017-10-20 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
-
2019
- 2019-05-30 CN CN201910464787.XA patent/CN110148623A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5659183A (en) * | 1995-12-06 | 1997-08-19 | Micron Technology, Inc. | Thin film transistor having a drain offset region |
| CN101236904A (en) * | 2008-02-29 | 2008-08-06 | 上海广电光电子有限公司 | Making method for multi-crystal silicon film transistor with the slight adulterated leakage pole area |
| US20110198607A1 (en) * | 2010-02-15 | 2011-08-18 | Nec Lcd Technologies, Ltd. | Thin-film transistor, method of manufacturing the same, display device, and electronic apparatus |
| CN107275390A (en) * | 2017-06-30 | 2017-10-20 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900210A (en) * | 2020-08-11 | 2020-11-06 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and display device |
| CN113113354A (en) * | 2021-03-18 | 2021-07-13 | 武汉华星光电技术有限公司 | Optical device, preparation method thereof and display panel |
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Application publication date: 20190820 |