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CN110060984A - 包括多芯片层叠物的半导体封装及其制造方法 - Google Patents

包括多芯片层叠物的半导体封装及其制造方法 Download PDF

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Publication number
CN110060984A
CN110060984A CN201811351968.3A CN201811351968A CN110060984A CN 110060984 A CN110060984 A CN 110060984A CN 201811351968 A CN201811351968 A CN 201811351968A CN 110060984 A CN110060984 A CN 110060984A
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CN
China
Prior art keywords
semiconductor chip
semiconductor
chip
projection block
bonding pad
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CN201811351968.3A
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English (en)
Inventor
成基俊
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication of CN110060984A publication Critical patent/CN110060984A/zh
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Abstract

包括多芯片层叠物的半导体封装及其制造方法。提供了半导体封装。所述半导体封装包括：第一半导体芯片，其连接有第一高架柱状凸块；第二半导体芯片，其层叠在第一半导体芯片上以保留第一高架柱状凸块露出，并且被配置为包括设置在第二半导体芯片的中心区域上的第一芯片焊盘；第三半导体芯片，其偏移并层叠在第二半导体芯片上以保留第一芯片焊盘露出；以及芯片支撑件，其支撑第三半导体芯片的突出部。

Description

包括多芯片层叠物的半导体封装及其制造方法
技术领域
本公开涉及半导体封装技术，更具体地讲，涉及包括多芯片层叠物的半导体封装及其制造方法。
背景技术
最近，在各种电子系统中需要具有高密度和高性能的半导体封装。另外，由于移动系统需要紧凑的半导体封装，所以已开发出具有相对小的形状因子的半导体封装。作为用于实现高性能半导体封装的封装技术，倒装芯片层叠技术可有吸引力。已提出一般倒装芯片层叠技术以提供包括在基板上层叠的一对芯片或一对晶片的双晶片层叠结构。因此，可能有必要开发一种封装技术以用于增加嵌入在封装中的半导体芯片的数量而不会增加封装的厚度。
发明内容
根据实施方式，提供了一种半导体封装。该半导体封装包括：第一半导体芯片，其连接有第一高架柱状凸块；以及第二半导体芯片，其层叠在第一半导体芯片上以保留第一高架柱状凸块露出，并且被配置为包括设置在第二半导体芯片的中心区域中的第一芯片焊盘。第二半导体芯片的中心区域与第二半导体芯片的边缘区域间隔开。第三半导体芯片层叠在第二半导体芯片上以相对于第二半导体芯片横向偏移以保留第一芯片焊盘露出。第三半导体芯片包括比第二半导体芯片的侧表面进一步横向突出的突出部(overhang)。提供芯片支撑件以支撑第三半导体芯片的突出部。设置包封层以包封第一半导体芯片、第二半导体芯片和第三半导体芯片的层叠结构。电路互连图案设置在包封层上并电连接到第一高架柱状凸块和第一芯片焊盘。
根据另一实施方式，提供了一种半导体封装。该半导体封装包括：第一半导体芯片，其连接有第一高架柱状凸块；第二半导体芯片，其层叠在第一半导体芯片上以保留第一高架柱状凸块露出，并且被配置为包括第一芯片焊盘；包封层，其包封第一半导体芯片和第二半导体芯片的层叠结构；开孔，其基本上穿透包封层以暴露第一高架柱状凸块和第一芯片焊盘；以及电路互连图案，其被配置为包括通孔部分和延伸部分。通孔部分通过开孔连接到第一高架柱状凸块和第一芯片焊盘，并且延伸部分从通孔部分延伸到包封层上。
根据另一实施方式，提供了一种制造半导体封装的方法。该方法包括以下步骤：提供连接有第一高架柱状凸块的第一半导体芯片并且将第二半导体芯片层叠在第一半导体芯片上以保留第一高架柱状凸块露出。第二半导体芯片具有设置在第二半导体芯片的与第二半导体芯片的边缘区域间隔开的中心区域中的第一芯片焊盘。将第三半导体芯片层叠在第二半导体芯片上以相对于第二半导体芯片横向偏移并保留第一芯片焊盘露出。形成包封层以包封第一半导体芯片、第二半导体芯片和第三半导体芯片的层叠结构。在包封层上形成电连接到第一高架柱状凸块和第一芯片焊盘的电路互连图案。
附图说明
图1至图9是示出根据实施方式的半导体封装的制造方法的横截面图。
图10是示出根据实施方式的半导体封装的横截面图。
图11是示出采用包括根据实施方式的半导体封装的存储卡的电子系统的框图。
图12是示出包括根据实施方式的半导体封装的另一电子系统的框图。
具体实施方式
本文所使用的术语可对应于考虑其在实施方式中的功能而选择的词语，术语的含义可被解释为根据实施方式所属领域的普通技术人员而不同。如果详细定义，则可根据定义来解释术语。除非另外定义，否则本文所使用的术语(包括技术术语和科学术语)具有实施方式所属领域的普通技术人员通常理解的相同含义。
将理解，尽管本文中可使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一元件相区分，而非用于仅限定元件本身或者意指特定顺序。
还将理解，当元件或层被称为在另一元件或层“上”、“上方”、“下面”、“下方”或“外侧”时，该元件或层可与另一元件或层直接接触，或者可存在中间元件或层。用于描述元件或层之间的关系的其它词语应该以类似的方式解释(例如，“在...之间”与“直接在...之间”或者“相邻”与“直接相邻”之间)。
诸如“在...之下”、“在...下面”、“下”、“上面”、“上”、“顶部”、“底部”等的空间相对术语可用于描述元件和/或特征与另一元件和/或特征的关系(例如，如图中所示)。将理解，除了附图中所描绘的取向之外，空间相对术语旨在涵盖装置在使用和/或操作中的不同取向。例如，当附图中的装置翻转时，被描述为在其它元件或特征下面和/或之下的元件将被取向为在其它元件或特征上面。装置可按照其它方式取向(旋转90度或处于其它取向)并且相应地解释本文中所使用的空间相对描述符。
半导体封装可包括诸如半导体芯片或半导体晶片的电子器件。半导体芯片或半导体晶片可通过使用划片工艺将诸如晶圆的半导体基板分离成多片来获得。半导体芯片可对应于存储器芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或系统芯片(SoC)。存储器芯片可包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可包括集成在半导体基板上的逻辑电路。半导体封装可用在诸如移动电话的通信系统、与生物技术或保健关联的电子系统或可穿戴电子系统中。
贯穿说明书，相同的标号表示相同的元件。即使标号未参照一幅图提及或描述，该标号也可参照另一幅图提及或描述。另外，即使标号未在一幅图中示出，其也可参照另一幅图提及或描述。
图1是示出在盖晶圆100上的第一半导体芯片301以及相对于第一半导体芯片301偏移层叠的第二半导体芯片302的横截面图。图2是示出第一半导体芯片301的横截面图。在本说明书中，术语“第一半导体芯片”、“第二半导体芯片”、“第三半导体芯片”、“第四半导体芯片”等仅用于将一个半导体芯片与另一半导体芯片相区分，而非用于意指特定顺序。
参照图1，盖晶圆100可以是没有任何集成电路的虚拟晶圆。用作盖晶圆100的虚拟晶圆可以是硅晶圆。用作盖晶圆100的虚拟晶圆可以是半导体晶圆、金属晶圆或介电晶圆。盖晶圆100可充当支撑在盖晶圆100上层叠的第一半导体芯片301和第二半导体芯片302的基础构件。盖晶圆100的一部分可用作保护半导体封装中的第一半导体芯片301和第二半导体芯片302的保护构件。
第一半导体芯片301可使用第一粘合层210附接到盖晶圆100的第一表面101。盖晶圆100可具有与第一半导体芯片301相反的第二表面102和第一表面101。第一粘合层210可将第一半导体芯片301的第三表面309结合到盖晶圆100的第一表面101。
第一半导体芯片301可包括提供第三表面309的芯片主体310。芯片主体310还可提供与盖晶圆100相反的第四表面308。第一芯片焊盘330可在芯片主体310的第四表面308处暴露。参照图2，芯片主体310可包括第一集成电路元件313。第一集成电路元件313可被集成在第一半导体层311中或第一半导体层311上。第一半导体层311可以是硅层。第一层间绝缘层312可设置在第一半导体层311上以覆盖第一集成电路元件313，并且第一内部互连结构314可被设置在第一层间绝缘层312中。第一层间绝缘层312可包括垂直层叠的多个介电层，并且可提供芯片主体310的第四表面308。第一内部互连结构314可将第一芯片焊盘330电连接到设置在芯片主体310中的第一集成电路元件313。
第一芯片焊盘330可对应于位于芯片主体310的中心区域301C的表面上的中心焊盘。中心区域301C可以是与芯片主体310的第一边缘区域301E间隔开的区域。第一半导体芯片301可包括从位于中心区域301C中的第一芯片焊盘330朝着第一边缘区域301E延伸的再分配互连线350。第一高架柱状凸块390可被设置在多个第一边缘区域301E中的一个上并与该第一边缘区域301E连接。各个再分配互连线350可包括连接部分351，并且第一高架柱状凸块390可设置在再分配互连线350的连接部分351上。第一高架柱状凸块390可电连接到再分配互连线350的连接部分351。介电层370可形成在芯片主体310的第四表面308上以覆盖再分配互连线350。介电层370可形成为空出并暴露再分配互连线350的连接部分351。第一高架柱状凸块390可连接到通过介电层370暴露的连接部分351。
参照图1和图2，第一高架柱状凸块390可充当具有垂直长度H1的连接构件。第一高架柱状凸块390的长度H1可对应于从芯片主体310向上突出的第一高架柱状凸块390的高度。第一高架柱状凸块390可被设置为显著提高再分配互连线350的连接部分351的位置。第一高架柱状凸块390可由金属材料(例如，铜材料)形成。第一高架柱状凸块390可形成为具有大约几十微米至大约一百几十微米的长度H1。第一高架柱状凸块390的长度H1可基本上等于第一半导体芯片301的厚度H2。第一高架柱状凸块390的长度H1可大于第一半导体芯片301的厚度H2。第一半导体芯片301的厚度H2可对应于第一半导体芯片301的第三表面309与介电层370的与第一层间绝缘层312相反的表面之间的距离。
再参照图1，第二半导体芯片302可层叠在第一半导体芯片301上以通过第一半导体芯片301横向偏移。第二半导体芯片302可使用第二粘合层230附接到第一半导体芯片301。第二半导体芯片302可以是具有与第一半导体芯片301基本上相同的配置的半导体芯片。例如，第二半导体芯片302可包括与中心焊盘对应的第二芯片焊盘332以及设置在第二半导体芯片302的第二边缘区域302E上的第二高架柱状凸块392。
第二半导体芯片302可相对于第一半导体芯片301横向偏移以保留第一半导体芯片301的第一边缘区域301E露出。因此，第一半导体芯片301和第二半导体芯片302可在盖晶圆100上垂直层叠以提供台阶结构。第二半导体芯片302可被设置为使得第二边缘区域302E与第一半导体芯片301的第一边缘区域301E相邻。因此，第二高架柱状凸块392可与第一高架柱状凸块390相邻。
第二半导体芯片302的侧表面可被设置为在横向方向上面向第一高架柱状凸块390。第一高架柱状凸块390可与第二半导体芯片302横向间隔开特定距离。第一高架柱状凸块390的长度H1可大于第二半导体芯片302的垂直厚度H3。因此，第一高架柱状凸块390的顶表面390S可位于比第二半导体芯片302的顶表面高的水平处。更具体地讲，第一高架柱状凸块390的顶表面390S可位于比第二芯片焊盘332高的水平处。第二芯片焊盘332可被设置在第二半导体芯片302的中心区域中。
第二高架柱状凸块392可形成为具有与第一高架柱状凸块390基本上相同的形状。例如，第二高架柱状凸块392的垂直长度H4可基本上等于第一高架柱状凸块390的长度H1。第二高架柱状凸块392的长度H4可大于第二半导体芯片302的厚度H3。第二高架柱状凸块392的长度H4可大于第一半导体芯片301的厚度H2。
在一些实施方式中，第二高架柱状凸块392的长度H4可小于第一高架柱状凸块390的长度H1。
图3是示出层叠在第二半导体芯片302上并相对于第二半导体芯片302横向偏移的第三半导体芯片401的横截面图。图4是示出第三半导体芯片401的横截面图。
参照图3，第三半导体芯片401可相对于第二半导体芯片302横向偏移。第三半导体芯片401可使用第三粘合层240附接到第二半导体芯片302。第三半导体芯片401可相对于第二半导体芯片302横向偏移以保留第二半导体芯片302的第二边缘区域302E露出。第二半导体芯片302和第三半导体芯片401可垂直层叠在第一半导体芯片301上以提供台阶结构。因此，第三半导体芯片401可设置在第二半导体芯片302上，使得第二半导体芯片302的侧表面可在横向方向上面向第二高架柱状凸块392。第二高架柱状凸块392的长度H4可大于第三半导体芯片401的垂直厚度H5。因此，第二高架柱状凸块392的顶表面392S可位于比第三半导体芯片401的与第二半导体芯片302相反的第五表面409高的水平处。在一些实施方式中，第二高架柱状凸块392可从第二半导体芯片302向上突出以具有基本上等于第三半导体芯片401的厚度的垂直长度H4。
参照图3和图4，与第一半导体芯片301和第二半导体芯片302不同，第三半导体芯片401可未配置有任何高架柱状凸块。第三半导体芯片401可包括在与第三半导体芯片401的顶表面对应的第五表面409上保持暴露的第三芯片焊盘430。第三半导体芯片401可包括第二集成电路元件413。第二集成电路元件413可被集成在第二半导体层411中或第二半导体层411上。第二半导体层411可以是硅层。第二层间绝缘层412可设置在第二半导体层411上以覆盖第二集成电路元件413，并且第二内部互连结构414可被设置在第二层间绝缘层412中。第二层间绝缘层412可包括垂直层叠的多个介电层，并且可提供第五表面409。第二内部互连结构414可将第三芯片焊盘430电连接到设置在第三半导体芯片401中的第二集成电路元件413。
第二集成电路元件413可包括构成存储器装置的单元晶体管。第一集成电路元件(图2的313)也可包括构成存储器装置的单元晶体管。第三半导体芯片401可以是存储器芯片，并且第一半导体芯片301和第二半导体芯片302也可以是存储器芯片。
第三芯片焊盘430可对应于位于第三半导体芯片401的中心区域401C中的中心焊盘。与第一半导体芯片301和第二半导体芯片302不同，第三半导体芯片401可被配置为不包括任何再分配互连线以及覆盖再分配互连线的任何介电层。
再参照图3，芯片支撑件500可设置在盖晶圆100上以与第三半导体芯片401间隔开。芯片支撑件500可使用第四粘合层260附接到盖晶圆100的第一表面101。盖晶圆100可支撑芯片支撑件500。芯片支撑件500可被设置为具有垂直厚度H7，该垂直厚度H7基本上等于第一半导体芯片301、第二半导体芯片302和第三半导体芯片401的总高度H6。例如，芯片支撑件500的厚度H7可对应于从第一半导体芯片301、第二半导体芯片302和第三半导体芯片401的总高度H6减去第四粘合层260的厚度后所余的值。因此，芯片支撑件500的顶表面509可位于与第五表面409(对应于第三半导体芯片401的顶表面)基本上相同的水平。
图5是示出层叠在第三半导体芯片401上以横向偏移的第四半导体芯片402的横截面图。
参照图5，第四半导体芯片402可通过第三半导体芯片401层叠以横向偏移。第二半导体芯片302、第三半导体芯片401和第四半导体芯片402可依次层叠在第一半导体芯片301上以在基本上相同的偏移方向上相对于第一半导体芯片301偏移。第四半导体芯片402相对于第三半导体芯片401的偏移距离454可大于第三半导体芯片401相对于第二半导体芯片302的偏移距离453。
第三芯片焊盘430所在的中心区域401C可保持未被第四半导体芯片402覆盖。第三半导体芯片401的中心区域401C可与第三半导体芯片401的边缘区域间隔开。第四半导体芯片402可偏移，使得第三半导体芯片401的第三芯片焊盘430保持暴露，并且第四半导体芯片402可与第三半导体芯片401部分地交叠。因此，第四半导体芯片402的一部分可横向突出超过第三半导体芯片401的侧表面以提供突出部402P。第四半导体芯片402的突出部402P的宽度可大于第四半导体芯片402的与第三半导体芯片401交叠的交叠部分402L的宽度。
芯片支撑件500可支撑第四半导体芯片402的突出部402P。芯片支撑件500可防止第四半导体芯片402的突出部402P向下翘曲。即，芯片支撑件500可防止第四半导体芯片402的突出部402P的翘曲或变形，以防止在第四半导体芯片402中形成裂缝。第四半导体芯片402可使用第五粘合层250附接到第三半导体芯片401和芯片支撑件500二者。
芯片支撑件500可以是虚拟晶片。芯片支撑件500可被设置为具有与第四半导体芯片402相同的材料。例如，芯片支撑件500可以是硅晶片。芯片支撑件500的宽度可为第四半导体芯片402的宽度的一半。另选地，芯片支撑件500的宽度可小于第四半导体芯片402的宽度的一半。
第四半导体芯片402可以是具有与第三半导体芯片401基本上相同的功能和形状的半导体芯片。第四半导体芯片402可被设置为具有中心区域402C以及设置在中心区域402C上的第四芯片焊盘431。
图6是示出包封第一半导体芯片301、第二半导体芯片302、第三半导体芯片401和第四半导体芯片402的光敏材料层600的横截面图。
参照图6，光敏材料层600可形成在盖晶圆100的第一表面101上以覆盖第一半导体芯片301、第二半导体芯片302、第三半导体芯片401和第四半导体芯片402。光敏材料层600可通过在盖晶圆100的第一表面101上层压光敏介电膜来形成。光敏材料层600可充当覆盖、包封并保护第一半导体芯片301、第二半导体芯片302、第三半导体芯片401和第四半导体芯片402的包封层。
光敏材料层600可包括诸如光敏聚酰亚胺材料或光敏聚苯并恶唑材料的光敏聚合物材料。由于光敏材料层600包括光敏剂，所以光敏材料层600的溶解度可取决于施加于光敏材料层600的曝光工艺。例如，曝露于诸如紫外(UV)线的光的光敏材料层600的溶解度可不同于未曝露于诸如紫外(UV)线的光的光敏材料层600的溶解度。
图7是示出将光敏材料层600部分地曝光的步骤的横截面图。
参照图7，可使用光刻设备将光敏材料层600的一些部分选择性地曝露于光。具体地讲，光掩模700可被设置在光敏材料层600上方，并且曝光光790可被照射到光掩模700上。曝光光790的一部分可被光掩模700的光阻挡区域710阻挡，并且曝光光790的剩余部分791可穿过光掩模700的光穿透区域720以到达光敏材料层600的预定部分。因此，曝光光790可改变光敏材料层600的预定部分的化学性质，并且可改变光敏材料层600的预定部分的溶解度。
曝光光790可渗入到光敏材料层600中以形成光敏材料层600的曝光区域609。曝光区域609可对应于对齐以与第一高架柱状凸块390和第二高架柱状凸块392以及第三芯片焊盘430和第四芯片焊盘431交叠的区域。曝光光790能够有效地传播到光敏材料层600中的曝光临界深度D可被限制为特定深度。曝光临界深度D指示通过曝光光790正常曝光的光敏材料层600的有效深度。即，足够强烈以对光敏材料层600正常曝光的曝光光790可能未达到光敏材料层600的低于曝光临界深度D的部分。因此，曝光区域609不应形成为比曝光临界深度D深。
在本公开中，第一高架柱状凸块390和第二高架柱状凸块392可形成为使得第一高架柱状凸块390和第二高架柱状凸块392的顶表面位于曝光临界深度D的范围内。因此，曝光区域609可形成为接触第一高架柱状凸块390和第二高架柱状凸块392的顶表面。
图8是示出在光敏材料层600中形成开孔605的步骤的横截面图。
参照图8，可通过对光敏材料层600进行显影来选择性地去除曝光区域(图7的609)。结果，可形成基本上穿透光敏材料层600的开孔605。可使用单个曝光步骤和单个显影步骤来形成开孔605。开孔605可包括第一至第四开孔601、602、603和604。第一开孔601可与第一高架柱状凸块390对齐并且可形成为暴露第一高架柱状凸块390的顶表面。第二开孔602可与第二高架柱状凸块392对齐并且可形成为暴露第二高架柱状凸块392的顶表面。第三开孔603可与第三芯片焊盘430对齐并且可形成为暴露第三芯片焊盘430的顶表面。第四开孔604可与第四芯片焊盘431对齐并且可形成为暴露第四芯片焊盘431的顶表面。即使开孔605形成在不同的位置处并且形成为具有不同的深度，也可使用包括单个曝光步骤和单个显影步骤的单个光刻步骤来同时形成所有开孔605。
参照图7和图8，第一半导体芯片301和第二半导体芯片302可位于曝光临界深度D的范围之外。因此，可能难以形成直接延伸到第一半导体芯片301和第二半导体芯片302的表面的曝光区域609。即，可能难以形成直接暴露第一半导体芯片301和第二半导体芯片302的表面的第一开孔601和第二开孔602。由于第一高架柱状凸块390和第二高架柱状凸块392向上延伸以使得第一高架柱状凸块390和第二高架柱状凸块392的顶表面位于曝光临界深度D的范围内，所以可通过第一开孔601和第二开孔602直接暴露第一高架柱状凸块390和第二高架柱状凸块392的至少顶表面。因此，第一高架柱状凸块390和第二高架柱状凸块392可充当将第一半导体芯片301和第二半导体芯片302连接到第一开孔601和第二开孔602的连接器。
第四芯片焊盘431可与第三芯片焊盘430间隔开偏移距离(图5的454)。因此，第四开孔604也可与第三开孔603间隔开偏移距离(图5的454)。第三芯片焊盘430可与第二高架柱状凸块392间隔开第三半导体芯片401的宽度的至少一半。因此，第三开孔603也可与第二开孔602间隔开第三半导体芯片401的宽度的至少一半。因此，由于第二开孔602、第三开孔603和第四开孔604彼此间隔开相对长的距离，所以可防止第二开孔602、第三开孔603和第四开孔604彼此连接。
图9是示出形成电路互连图案800的步骤的横截面图。
参照图9，可在光敏材料层600上形成电路互连图案800。各个电路互连图案800可形成为包括填充多个开孔605中的任一个的通孔部分810以及从通孔部分810延伸到光敏材料层600的表面606上的延伸部分830。电路互连图案800的通孔部分810可分别直接接触第一高架柱状凸块390和第二高架柱状凸块392以及第三芯片焊盘430和第四芯片焊盘431。电路互连图案800的通孔部分810可分别直接连接到第一高架柱状凸块390和第二高架柱状凸块392以及第三芯片焊盘430和第四芯片焊盘431。电路互连图案800的通孔部分810可通过开孔605直接地分别连接到第一高架柱状凸块390和第二高架柱状凸块392以及第三芯片焊盘430和第四芯片焊盘431。
由于第一开孔601可延伸得比第三半导体芯片401的下部更深，所以填充第一开孔601的通孔部分810的垂直长度可大于第三半导体芯片401的厚度。由于第三开孔603可形成为比第四半导体芯片402的下部更深，所以填充第三开孔603的通孔部分810的垂直长度可大于第四半导体芯片402的厚度。相比之下，由于第四开孔604形成为比第四半导体芯片402的厚度浅，所以填充第四开孔604的通孔部分810的垂直长度可小于第四半导体芯片402的厚度。
可在光敏材料层600的表面606上形成介电层910以保留电路互连图案800的延伸部分830的部分露出。可在电路互连图案800的延伸部分830的保持露出的部分上形成外连接器900。外连接器900可由凸块或焊球形成。在这种情况下，一些延伸部分830可形成为延伸到光敏材料层600的边缘区域上以不与第一至第四半导体芯片301、302、401和402交叠。因此，一些外连接器900可形成为不与第一至第四半导体芯片301、302、401和402交叠。
可使用分割工艺(例如，划片工艺)来切割形成有外连接器900的盖晶圆100以提供多个分立半导体封装10，其中之一示出于图10中。在执行分割工艺之前，可对盖晶圆100的第二表面102应用凹陷工艺以减小盖晶圆100的厚度。
参照图10，分立半导体封装10可包括层叠在通过切割盖晶圆100而制造的多个盖晶片100D中的任一个上的第一至第四半导体芯片301、302、401和402。盖晶片100D可以是硅晶片。芯片支撑件500可由盖晶片100D支撑。第一高架柱状凸块390可被设置在第一半导体芯片301的第一边缘区域301E上，并且第二高架柱状凸块392可被设置在第二半导体芯片302的第二边缘区域302E上。第四半导体芯片402的突出部402P可由芯片支撑件500支撑。
第一至第四半导体芯片301、302、401和402的层叠物可被光敏材料层600覆盖和包封。可使用包括单个曝光步骤和单个显影步骤的单个光刻步骤来形成开孔605以基本上穿透光敏材料层600。可利用通孔部分810填充开孔605，并且通孔部分810可延伸到光敏材料层600上以提供延伸部分830。通孔部分810和延伸部分830可构成电路互连图案800。电路互连图案800可被设置在充当包封层的光敏材料层600上并且可电连接到第一高架柱状凸块390和第二高架柱状凸块392以及第三芯片焊盘430和第四芯片焊盘431。可在电路互连图案800上设置介电层910以保留电路互连图案800的部分露出，并且外连接器900可附接并连接到电路互连图案800的露出的部分。
图11是示出包括采用根据实施方式的半导体封装的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置的存储器7810以及存储控制器7820。存储器7810和存储控制器7820可存储数据或者读出所存储的数据。存储器7810和存储控制器7820中的至少一个可包括根据实施方式的半导体封装。
存储器7810可包括应用了本公开的实施方式的技术的非易失性存储器装置。存储控制器7820可控制存储器7810，使得响应于来自主机7830的读/写请求，读出所存储的数据或者存储数据。
图12是示出包括根据实施方式的半导体封装的电子系统8710的框图。电子系统8710可包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可通过提供数据移动的路径的总线8715彼此联接。
在实施方式中，控制器8711可包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同的功能的逻辑器件。控制器8711或存储器8713可包括根据本公开的实施方式的多个半导体封装中的一个或更多个。输入/输出装置8712可包括选自键区、键盘、显示装置、触摸屏等中的至少一个。存储器8713是用于存储数据的装置。存储器8713可存储要由控制器8711执行的数据和/或命令等。
存储器8713可包括诸如DRAM的易失性存储器装置和/或诸如闪存的非易失性存储器装置。例如，闪存可被安装到诸如移动终端或台式计算机的信息处理系统。闪存可构成固态盘(SSD)。在这种情况下，电子系统8710可在闪存系统中稳定地存储大量数据。
电子系统8710还可包括被配置为向通信网络发送数据以及从通信网络接收数据的接口8714。接口8714可为有线或无线型。例如，接口8714可包括天线或者有线或无线收发器。
电子系统8710可被实现为移动系统、个人计算机、工业计算机或者执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任一个。
如果电子系统8710是能够执行无线通信的设备，则电子系统8710可用在使用诸如CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDAM(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中。
出于例示性目的公开了本公开的实施方式。本领域技术人员将理解，在不脱离本公开和所附权利要求的范围和精神的情况下，可进行各种修改、添加和替换。
相关申请的交叉引用
本申请要求2018年1月18日提交的韩国申请No.10-2018-0006508的优先权，其整体通过引用并入本文。

Claims (31)

1.一种半导体封装，该半导体封装包括：
第一半导体芯片，第一高架柱状凸块连接到该第一半导体芯片；
第二半导体芯片，该第二半导体芯片层叠在所述第一半导体芯片上以保留所述第一高架柱状凸块露出，并且被配置为包括设置在所述第二半导体芯片的中心区域中的第一芯片焊盘，其中，所述第二半导体芯片的所述中心区域与所述第二半导体芯片的边缘区域间隔开；
第三半导体芯片，该第三半导体芯片层叠在所述第二半导体芯片上以相对于所述第二半导体芯片横向偏移以保留所述第一芯片焊盘露出，并且被配置为包括比所述第二半导体芯片的侧表面进一步横向突出的突出部；
芯片支撑件，该芯片支撑件支撑所述第三半导体芯片的所述突出部；
包封层，该包封层包封所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片的层叠结构；以及
电路互连图案，所述电路互连图案被设置在所述包封层上并且电连接到所述第一高架柱状凸块和所述第一芯片焊盘。
2.根据权利要求1所述的半导体封装，
其中，所述包封层包括分别暴露所述第一高架柱状凸块和所述第一芯片焊盘的开孔，并且
其中，各个所述电路互连图案填充所述开孔中的任一个并且延伸到所述包封层上。
3.根据权利要求1所述的半导体封装，其中，所述包封层包括光敏材料层。
4.根据权利要求1所述的半导体封装，其中，所述第一高架柱状凸块连接到所述第一半导体芯片的边缘区域。
5.根据权利要求4所述的半导体封装，其中，所述第一半导体芯片包括：
第二芯片焊盘，该第二芯片焊盘被设置在所述第一半导体芯片的中心区域中，其中，所述第一半导体芯片的所述中心区域与所述第一半导体芯片的边缘区域间隔开；以及
再分配互连线，该再分配互连线从所述第二芯片焊盘延伸以接触所述第一高架柱状凸块。
6.根据权利要求1所述的半导体封装，其中，所述第一高架柱状凸块从所述第一半导体芯片向上突出以具有基本上等于所述第二半导体芯片的厚度的垂直长度。
7.根据权利要求1所述的半导体封装，其中，所述第一高架柱状凸块从所述第一半导体芯片向上突出以具有大于所述第二半导体芯片的厚度的垂直长度。
8.根据权利要求1所述的半导体封装，其中，所述第二半导体芯片层叠在所述第一半导体芯片上以提供台阶结构。
9.根据权利要求1所述的半导体封装，该半导体封装还包括层叠在所述第一半导体芯片的与所述第二半导体芯片相反的底表面上的第四半导体芯片，
其中，第二高架柱状凸块连接到所述第四半导体芯片，并且
其中，所述第一半导体芯片偏移层叠在所述第四半导体芯片上以保留所述第二高架柱状凸块露出。
10.根据权利要求9所述的半导体封装，该半导体封装还包括支撑所述第四半导体芯片的盖晶片。
11.根据权利要求10所述的半导体封装，其中，所述芯片支撑件由所述盖晶片支撑。
12.根据权利要求11所述的半导体封装，其中，所述芯片支撑件被设置在所述盖晶片上以具有基本上等于所述第四半导体芯片、所述第一半导体芯片和所述第二半导体芯片的总高度的高度。
13.根据权利要求12所述的半导体封装，其中，所述芯片支撑件是硅晶片。
14.根据权利要求9所述的半导体封装，其中，所述第三半导体芯片相对于所述第二半导体芯片的偏移距离大于所述第一半导体芯片相对于所述第四半导体芯片的偏移距离。
15.根据权利要求9所述的半导体封装，其中，所述第一半导体芯片、所述第二半导体芯片、所述第三半导体芯片和所述第四半导体芯片在基本上相同的偏移方向上偏移层叠。
16.根据权利要求9所述的半导体封装，
其中，所述第一半导体芯片和所述第四半导体芯片具有基本上相同的形状，并且
其中，所述第二半导体芯片和所述第三半导体芯片具有基本上相同的形状。
17.一种半导体封装，该半导体封装包括：
第一半导体芯片，第一高架柱状凸块连接到该第一半导体芯片；
第二半导体芯片，该第二半导体芯片层叠在所述第一半导体芯片上以保留所述第一高架柱状凸块露出，并且被配置为包括第一芯片焊盘；
包封层，该包封层包封所述第一半导体芯片和所述第二半导体芯片的层叠结构；
开孔，所述开孔基本上穿透所述包封层以暴露所述第一高架柱状凸块和所述第一芯片焊盘；以及
电路互连图案，所述电路互连图案被配置为包括通过所述开孔连接到所述第一高架柱状凸块和所述第一芯片焊盘的通孔部分以及从所述通孔部分延伸到所述包封层上的延伸部分。
18.根据权利要求17所述的半导体封装，其中，所述通孔部分分别直接接触所述第一高架柱状凸块和所述第一芯片焊盘。
19.根据权利要求17所述的半导体封装，其中，所述第一芯片焊盘被设置在所述第二半导体芯片的与所述第二半导体芯片的边缘区域间隔开的中心区域中。
20.根据权利要求19所述的半导体封装，该半导体封装还包括偏移层叠在所述第二半导体芯片上以保留所述第一芯片焊盘露出的第三半导体芯片，
其中，所述第三半导体芯片具有从所述第二半导体芯片的侧表面横向突出的突出部。
21.根据权利要求20所述的半导体封装，其中，连接到所述第一芯片焊盘的所述通孔部分具有大于所述第三半导体芯片的厚度的垂直长度。
22.根据权利要求17所述的半导体封装，该半导体封装还包括层叠在所述第一半导体芯片的与所述第二半导体芯片相反的底表面上的第四半导体芯片，
其中，第二高架柱状凸块连接到所述第四半导体芯片，并且
其中，所述第一半导体芯片偏移层叠在所述第四半导体芯片上以保留所述第二高架柱状凸块露出。
23.根据权利要求22所述的半导体封装，
其中，所述电路互连图案还包括连接到所述第二高架柱状凸块的附加通孔部分，并且
其中，所述附加通孔部分具有大于所述第二半导体芯片的厚度的垂直长度。
24.一种制造半导体封装的方法，该方法包括以下步骤：
提供连接有第一高架柱状凸块的第一半导体芯片；
将第二半导体芯片层叠在所述第一半导体芯片上以保留所述第一高架柱状凸块露出，其中，所述第二半导体芯片具有设置在所述第二半导体芯片的与所述第二半导体芯片的边缘区域间隔开的中心区域中的第一芯片焊盘；
将第三半导体芯片层叠在所述第二半导体芯片上以相对于所述第二半导体芯片横向偏移并保留所述第一芯片焊盘露出；
利用包封层包封所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片的层叠结构；以及
在所述包封层上形成电连接到所述第一高架柱状凸块和所述第一芯片焊盘的电路互连图案。
25.根据权利要求24所述的方法，其中，所述包封层被形成为包括光敏材料层，
其中，形成所述电路互连图案的步骤包括以下步骤：
在所述光敏材料层中形成开孔，其中，所述开孔分别暴露所述第一高架柱状凸块和所述第一芯片焊盘；以及
形成填充所述开孔并延伸到所述光敏材料层上的所述电路互连图案，并且
其中，通过对所述光敏材料层进行曝光和显影来同时形成所述开孔。
26.根据权利要求24所述的方法，该方法还包括以下步骤：设置层叠在所述第一半导体芯片的与所述第二半导体芯片相反的底表面上的第四半导体芯片，
其中，第二高架柱状凸块连接到所述第四半导体芯片，并且
其中，所述第一半导体芯片偏移层叠在所述第四半导体芯片上以保留所述第二高架柱状凸块露出。
27.根据权利要求26所述的方法，其中，所述第四半导体芯片被设置在盖晶圆上，并且
该方法还包括以下步骤：在所述盖晶圆上设置芯片支撑件以与所述第四半导体芯片、所述第一半导体芯片和所述第二半导体芯片间隔开，
其中，所述芯片支撑件支撑所述第三半导体芯片的从所述第二半导体芯片的侧表面突出的突出部，并且
其中，所述芯片支撑件被设置在所述盖晶圆上以具有基本上等于所述第四半导体芯片、所述第一半导体芯片和所述第二半导体芯片的总高度的高度。
28.根据权利要求27所述的方法，其中，通过在所述盖晶圆上层压光敏介电层来形成所述包封层。
29.根据权利要求25所述的方法，其中，所述电路互连图案被形成为包括：
通过所述开孔连接到所述第一高架柱状凸块和所述第一芯片焊盘的通孔部分；以及
从所述通孔部分延伸到所述包封层上的延伸部分。
30.根据权利要求29所述的方法，其中，所述通孔部分被形成为分别直接接触所述第一高架柱状凸块和所述第一芯片焊盘。
31.根据权利要求24所述的方法，该方法还包括以下步骤：设置用于支撑所述第三半导体芯片的从所述第二半导体芯片的侧表面突出的突出部的芯片支撑件。
CN201811351968.3A 2018-01-18 2018-11-14 包括多芯片层叠物的半导体封装及其制造方法 Pending CN110060984A (zh)

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