CN118511216A - Nitride-based semiconductor device and method of manufacturing the same - Google Patents
Nitride-based semiconductor device and method of manufacturing the same Download PDFInfo
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- CN118511216A CN118511216A CN202280087493.XA CN202280087493A CN118511216A CN 118511216 A CN118511216 A CN 118511216A CN 202280087493 A CN202280087493 A CN 202280087493A CN 118511216 A CN118511216 A CN 118511216A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 236
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 209
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 10
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- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- 238000007792 addition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- Junction Field-Effect Transistors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a doped nitride-based semiconductor layer. The second nitride-based semiconductor layer has a plurality of concave portions separated from each other and a plurality of flat portions alternately arranged in the first direction. The doped nitride-based semiconductor layer conformally covers the second nitride-based semiconductor layer and has a plurality of first portions and a plurality of second portions. The first portions cover the concave portions, respectively, and the second portions cover the flat portions, respectively. The doped nitride-based semiconductor layer has a first profile in a first vertical cross-sectional view of the nitride-based semiconductor device through a first portion thereof. The doped nitride-based semiconductor layer has a second profile in a second vertical cross-sectional view through a second portion thereof. The second profile is different from the first profile.
Description
Technical Field
In general, the present invention relates to nitride-based semiconductor devices. More particularly, the present invention relates to nitride-based semiconductor devices having doped nitride-based semiconductor layers with different profiles in different vertical cross-sectional views of the nitride-based semiconductor device.
Background
In recent years, research into High Electron Mobility Transistors (HEMTs) has been increasingly popular, particularly for high power switches and high frequency applications. Group III nitride based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2 DEG) region to meet the needs of high power/frequency devices. Examples of devices having a heterostructure include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs) and modulation doped FETs (MODFETs) in addition to HEMTs.
Disclosure of Invention
In one aspect, the present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a doped nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a larger band gap than the first nitride-based semiconductor layer, thereby forming a heterojunction and a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. The second nitride-based semiconductor layer has a plurality of concave portions separated from each other and a plurality of flat portions alternately arranged in the first direction. The doped nitride-based semiconductor layer conformally covers the second nitride-based semiconductor layer and has a plurality of first portions and a plurality of second portions. The first portions cover the concave portions, respectively, and the second portions cover the flat portions, respectively. The doped nitride-based semiconductor layer has a first profile in a first vertical cross-sectional view of the nitride-based semiconductor device through a first portion thereof. The doped nitride-based semiconductor layer has a second profile in a second vertical cross-sectional view through a second portion thereof. The second profile is different from the first profile.
In another aspect, the present invention provides a method for manufacturing a semiconductor device. The method comprises the following steps. A first nitride-based semiconductor layer is formed. An intermediate nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer, wherein a band gap of the intermediate nitride-based semiconductor layer is greater than a band gap of the first nitride-based semiconductor layer. Portions of the intermediate nitride-based semiconductor layer are removed to form a second nitride-based semiconductor layer having a plurality of concave portions separated from each other and a plurality of flat portions alternately arranged in the first direction. The doped nitride-based semiconductor layer is formed to cover at least the concave portions and the flat portions such that the doped nitride-based semiconductor layer has a plurality of first portions and a plurality of second portions, wherein the first portions cover the concave portions, respectively, and the second portions cover the flat portions, respectively. The doped nitride-based semiconductor layer has a first profile in a first vertical cross-sectional view through a first portion thereof. The doped nitride-based semiconductor layer has a second profile in a second vertical cross-sectional view through a second portion thereof. The first profile is different from the second profile.
In yet another aspect, the present invention provides a semiconductor device. The semiconductor device includes a channel layer, a barrier layer, and a doped semiconductor layer. The barrier layer is disposed on the channel layer and has a plurality of concave portions and a plurality of flat portions separated from each other. Each flat portion is located between two adjacent concave portions. The doped semiconductor layer is conformally disposed on the recessed portion and the planar portion such that the doped semiconductor layer has a plurality of first portions respectively received by the recessed portion and a plurality of second portions respectively disposed on the planar portion. In a first vertical cross-sectional view of the semiconductor device through the first portion and the recessed portion therebelow, the doped semiconductor layer has an uneven top surface. In a second vertical cross-sectional view of the semiconductor device through the second portion and the underlying planar portion, the doped semiconductor layer has a planar top surface.
With the above configuration, in the present invention, the barrier layer is formed to have a plurality of concave portions and a plurality of flat portions alternately arranged in one direction. Then, a doped nitride-based semiconductor layer is formed to extend in the direction to cover the recessed portion and the flat portion of the barrier layer. Thus, the doped nitride-based semiconductor layer has different profiles in different vertical cross-sectional views of the semiconductor device. Portions of the doped nitride-based semiconductor layer may extend into the recessed portions of the barrier layer, and thus top and side surfaces of the planar portions of the barrier layer may contact the doped nitride-based semiconductor layer, thereby increasing a contact area between the doped nitride-based semiconductor layer and the barrier layer. Thus, the dopant in the doped nitride-based semiconductor layer may fully deplete the region of the 2DEG region under the flat portion, thereby avoiding leakage current problems.
Drawings
Various aspects of the invention can be readily appreciated from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity. Embodiments of the invention are described in more detail below with reference to the attached drawing figures, wherein:
fig. 1A is a top view of a nitride-based semiconductor device according to some embodiments of the present invention;
FIG. 1B is a vertical cross-sectional view taken along line A-A' in FIG. 1A;
FIG. 1C is a vertical cross-sectional view taken along line B-B' in FIG. 1A;
FIG. 1D is a vertical cross-sectional view along line C-C' in FIG. 1A;
Fig. 2A, 2B, 2C and 2D illustrate different stages of a method for fabricating a semiconductor device according to some embodiments of the invention;
fig. 3 is a top view of a nitride-based semiconductor device according to some embodiments of the present invention;
Fig. 4 is a top view of a nitride-based semiconductor device according to some embodiments of the present invention;
fig. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the invention; and
Fig. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the invention.
Detailed Description
The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present invention will be readily understood from the following detailed description in conjunction with the accompanying drawings.
Spatial descriptions such as "upper," "lower," "left," "right," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," etc., are intended to be relative to a certain component or group of components, or a plane of a component or group of components, for the orientation of the components shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that specific implementations of the structures described herein may be spatially arranged in any orientation or manner without departing from the spirit of the present invention.
Further, it should be noted that, subject to device manufacturing conditions, in an actual device, the actual shape of the various structures depicted as being approximately rectangular may be curved, or have rounded corners, or have a slightly non-uniform thickness, etc. Straight lines and right angles are only used to facilitate the presentation of layers and features.
In the following description, a semiconductor device/die/package and a method for manufacturing the same are set forth as preferred examples. It will be apparent that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring. However, the present invention was written in order to enable any person skilled in the art to practice the teachings thereof without undue experimentation.
Fig. 1A is a top view of a nitride-based semiconductor device 1A according to some embodiments of the present invention. Fig. 1B is a vertical sectional view along the line A-A' in fig. 1A.
Referring to fig. 1A and 1B, the nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16, electrodes 20, 22, a doped nitride-based semiconductor layer 30, a gate electrode 34, and a dielectric layer 40.
The substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, but are not limited to, si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) or other suitable substrate materials. In some embodiments, the substrate 10 may include, but is not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 10 may include, but is not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.
The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 is configured to reduce lattice and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 14, thereby overcoming defects caused by mismatch/difference. Buffer layer 12 may include a III-V compound. The III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials for the buffer layer may further include, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.
In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). A nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer is configured to provide a transition to accommodate the mismatch/difference between the III-nitride layers of the substrate 10 and the buffer layer 12. Exemplary materials for the nucleation layer may include, but are not limited to, alN or any alloy thereof.
A nitride-based semiconductor layer 14 may be disposed on the buffer layer 12. The nitride-based semiconductor layer 16 may be disposed on the nitride-based semiconductor layer 14. Exemplary materials for nitride-based semiconductor layer 14 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in xAlyGa(1-x-y) N (where x+y.ltoreq.1), or Al xGa(1-x) N (where x.ltoreq.1). Exemplary materials for nitride-based semiconductor layer 16 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in xAlyGa(1-x-y) N (where x+y.ltoreq.1), or Al yGa(1-y) N (where y.ltoreq.1).
The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the band gap (i.e., the forbidden band width) of the nitride-based semiconductor layer 16 is greater than the band gap of the nitride-based semiconductor layer 14, thereby making their electron affinities different from each other and forming a heterojunction therebetween. For example, when nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of about 3.4eV, nitride-based semiconductor layer 16 may be selected to be a GaN layer having a bandgap of about 4.0 eV. In this way, the nitride-based semiconductor layers 14 and 16 may function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A may be used to include at least one GaN-based High Electron Mobility Transistor (HEMT).
In conventional HEMT devices, a p-type doped nitride-based semiconductor layer is typically formed to deplete the region of the underlying 2DEG region, thereby obtaining an enhancement device. However, in some cases, the 2DEG region under the p-type doped nitride-based semiconductor layer may not be fully depleted, and thus, may cause leakage current problems when the device is in an off state.
At least to avoid the above problems, the present invention provides a novel structure.
During formation of the nitride-based semiconductor layer 16, first, an intermediate nitride-based semiconductor layer having a flat top surface is formed. Then, a patterning process is performed on the doped intermediate nitride-based semiconductor layer to remove portions of the intermediate nitride-based semiconductor layer, thereby forming the nitride-based semiconductor layer 16 having the plurality of concave portions 162A and the plurality of flat portions 164.
Referring to fig. 1A and 1B, the concave portions 162A and the flat portions 164 are alternately arranged in the direction D1. The concave portion 162A of the second nitride-based semiconductor layer extends in a direction D2 different from the direction D1, for example, the direction D2 is perpendicular to the direction D1. The contour of the concave portion 162A in fig. 1A has a constant width, for example, a rectangular contour with straight sides. The concave portions 162A are disposed at equal intervals in the direction D1. The concave portions 162A are separated from each other. Each flat portion 164 is located between two adjacent concave portions 162A. The top surface of each recessed portion 162A is lower than the top surface of the flat portion 164.
Thereafter, the doped nitride-based semiconductor layer 22 extends in the direction D1 to form a stripe-like profile such that the doped nitride-based semiconductor layer 22 conformally covers the nitride-based semiconductor layer 16. Specifically, portions 222 of the doped nitride-based semiconductor layer 22 cover the concave portions 162A, respectively. Portions 222 of the doped nitride-based semiconductor layer 22 are respectively accommodated/confined by the recessed portions 162A. Referring to fig. 1A, the width of the recess portion 162A is smaller than the width of the doped nitride-based semiconductor layer 22. Referring to fig. 1B, since each of the concave portions 162A has a rectangular profile, each of the portions 222 of the doped nitride-based semiconductor layer 22 also has a rectangular profile by the foregoing configuration. Portions 224 of the doped nitride-based semiconductor layer 22 are disposed on the planar portions 164, respectively. Portions 224 of doped nitride-based semiconductor layer 22 each cover planar portion 164. The top surface of portion 222 is lower than the top surface of portion 224. In this way, the doped nitride-based semiconductor layer 22 formed on the nitride-based semiconductor layer 16 has a wavy structure.
Based on the above configuration, the portion 222 of the doped nitride-based semiconductor layer 22 is in contact with the top surface of the recessed portion 162A with respect to the region R1 under the recessed portion 162A. Thus, in the region R1, the dopant in the doped nitride-based semiconductor layer 22 may deplete the region of the 2DEG region through the top surface of the recess portion 162A.
On the other hand, with respect to the region R2 under the flat portion 164, the flat portion 164 is surrounded by the portions 222, 224 of the doped nitride-based semiconductor layer 22 such that the side surfaces and the top surface of the flat portion 164 are in contact with the doped nitride-based semiconductor layer 22. Thus, in the region R2, the dopant in the doped nitride-based semiconductor layer 22 may deplete the region of the 2DEG region through the top and side surfaces of the flat portion 164. That is, since the contact area between the nitride-based semiconductor layer 16 and the doped nitride-based semiconductor layer 22 increases in the region R2, the region of the 2DEG region may be completely depleted of the dopant in the doped nitride-based semiconductor layer 22. When the nitride-based semiconductor device 1A is in the off state, the leakage current problem can be avoided. In some embodiments, the ratio of the width of region R1 to the width of region R2 is in the range of 1 to 10 to improve the sensitivity in the off state. Ratios outside this range may result in at least one leakage current in the off state.
Fig. 1C is a vertical sectional view along line B-B' in fig. 1A. Fig. 1D is a vertical sectional view along line C-C' in fig. 1A. Further, with the foregoing configuration, the stripe-shaped doped nitride-based semiconductor layer 22 is formed to cover the concave portion 162A and the flat portion 164, and thus the doped nitride-based semiconductor layer 22 has different profiles in different vertical sectional views as shown in fig. 1C and 1D, respectively. For example, in a vertical cross-sectional view of the nitride-based semiconductor device 1A through the portion 222 as shown in fig. 1C, the portion 222 of the doped nitride-based semiconductor layer 22 has a profile of which the width is variable. The portion 222 has an uneven top surface. In the vertical cross-sectional view of the nitride-based semiconductor device 1A through the portion 224 as shown in fig. 1D, the portion 224 of the doped nitride-based semiconductor layer 22 has a different profile, for example a rectangular profile, than the portion 222. Portion 224 has a flat top surface.
The gate 24 extends in the direction D1 to form a stripe-shaped profile such that the gate 24 is disposed/covered on the doped nitride-based semiconductor layer 22. The gate electrode 24 is in contact with the doped nitride-based semiconductor layer 30. The gate 24 has a width less than the recessed portion 162A. In fig. 1C, a portion 222 of the doped nitride-based semiconductor layer 22 is spaced apart from the gate 24. The doped nitride-based semiconductor layer 22 and the gate 24 may collectively function as a gate structure.
In the exemplary illustration of fig. 1B, nitride-based semiconductor device 1A is an enhancement-mode device that is in a normally-off state when gate 24 is at approximately zero bias. Specifically, doped nitride-based semiconductor layer 22 may create at least one p-n junction with nitride-based semiconductor layer 16 to deplete the 2DEG region such that at least one zone of the 2DEG region corresponding to a location below gate 24 has a different characteristic (e.g., a different electron concentration) than the rest of the 2DEG region, and is thus blocked.
Due to this mechanism, the nitride-based semiconductor device 1A has normally-off characteristics. In other words, when no voltage is applied to the gate 22 or the voltage applied to the gate 22 is less than the threshold voltage (i.e., the minimum voltage required to form an inversion layer under the gate 22), the band of the 2DEG region under the gate 22 remains blocked, and thus no current flows.
The doped nitride-based semiconductor layer 22 may be a p-type doped III-V semiconductor layer. Exemplary materials for doped nitride-based semiconductor layer 22 may include, but are not limited to, p-doped group III-V nitride semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is achieved by using p-type impurities (e.g., be, zn, cd, and Mg). In some embodiments, nitride-based semiconductor layer 14 comprises undoped GaN, nitride-based semiconductor layer 16 comprises AlGaN, and doped nitride-based semiconductor layer 22 is a p-type GaN layer that can bend the underlying band structure upward and deplete the corresponding band of the 2DEG region, thereby placing semiconductor device 1A in an off state.
Exemplary materials for gate 24 may include metals or metal compounds. The gate 24 may be formed as a single layer, or as multiple layers of the same or different composition. Exemplary materials for the metal or metal compound may include, but are not limited to, W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.
The electrodes 30, 32 are disposed on the nitride-based semiconductor layer 16. The electrodes 30, 32 extend in the direction D1 to form a strip-like profile. The electrodes 30, 32 are in contact with the nitride-based semiconductor layer 16. The gate 22 is located between the electrodes 30, 32. Each recessed portion 162A extends from electrode 30 to electrode 32 along direction D2. The electrodes 30, 32 are disposed on two opposite sides of the recessed portion 162A. In some embodiments, electrode 30 may serve as a source. In some embodiments, electrode 30 may function as a drain. In some embodiments, electrode 32 may serve as a source. In some embodiments, electrode 32 may function as a drain. The roles of electrodes 30 and 32 depend on the device design.
In some embodiments, electrodes 30 and 32 may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for electrodes 30 and 32 may include, but are not limited to, ti, alSi, tiN, or combinations thereof. Each electrode 30 and 32 may be a single layer, or multiple layers of the same or different composition. The electrodes 30 and 32 form ohmic contacts with the nitride-based semiconductor layer 16. In addition, ohmic contact may be achieved by applying Ti, al, or other suitable materials to the electrodes 30 and 32.
A dielectric layer 40 is disposed on the nitride-based semiconductor layer 16, the doped nitride-based semiconductor layer 22, the gate 24, and the electrodes 30, 32. The material of the dielectric layer 40 may include, but is not limited to, a dielectric material. For example, dielectric layer 40 may include, but is not limited to, siN x,SiOx,Si3N4, siON, siC, siBN, siCBN, oxide, nitride, plasma Enhanced Oxide (PEOX), or combinations thereof. In some embodiments, dielectric layer 40 may include an oxide. In some embodiments, the dielectric layer 40 may be a multi-layer structure, such as a composite dielectric layer of Al 2O3/SiN,Al2O3/SiO2,AlN/SiN,AlN/SiO2 or a combination thereof.
In some embodiments, the optional dielectric layer may be formed of a single layer or multiple layers of dielectric material. Exemplary dielectric materials may include, but are not limited to, one or more oxide layers, siO x layers, siN x layers, high-k dielectric materials (e.g., ,HfO2,Al2O3,TiO2,HfZrO,Ta2O3,HfSiO4,ZrO2,ZrSiO2, etc.), or combinations thereof.
As described below, fig. 2A, 2B, 2C and 2D show different stages of a method for manufacturing the semiconductor device 1A. Hereinafter, deposition techniques may include, but are not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other processes.
Referring to fig. 2A, a substrate 10 is provided. A nitride-based semiconductor layer is formed on the substrate 10 by a deposition technique. An intermediate nitride-based semiconductor layer 16' is formed on the first nitride-based semiconductor layer 14.
Referring to fig. 2B, portions of the intermediate nitride-based semiconductor layer 16' are removed to form the nitride-based semiconductor layer 16 having a plurality of concave portions 162A separated from each other and a plurality of flat portions 164 alternately arranged in the direction D1.
Referring to fig. 2C, a doped middle nitride-based semiconductor layer 22 'is formed to cover at least the concave portion 162A and the flat portion 164, thereby forming a doped middle nitride-based semiconductor layer 22' having a plurality of portions 222 and a plurality of portions 224. Portions 222 respectively cover recessed portions 162A and portions 224 respectively cover flat portions 164.
Referring to fig. 2D, a patterning process is performed on the doped middle nitride-based semiconductor layer 22' to remove an excess portion thereof, thereby forming the doped nitride-based semiconductor layer 22 having portions 222 and 224. The portion 222 has a variable width profile. The portion 224 has a rectangular profile. The gate electrode 24, the electrodes 30, 32, and the dielectric layer 40 are sequentially formed, thereby obtaining the nitride-based semiconductor device 1A in fig. 1A.
Fig. 3 is a top view of a nitride-based semiconductor device 1B according to some embodiments of the present invention. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A in fig. 1A,1B,1c, and 1D, except that the concave portion 162B has an elliptical profile with curved edges.
Fig. 4 is a top view of a nitride-based semiconductor device 1C according to some embodiments of the present invention. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A in fig. 1A,1b, and 1C, except that the concave portion 162C has a profile with a gradually changing width, for example, a trapezoidal profile. Specifically, the width of the recessed portion 162C gradually decreases in the direction D2 from the electrode 30 toward the electrode 32.
With respect to the nitride-based semiconductor devices 1B and 1C, by changing the outline of the concave portions 162B and 162C in the top view of the nitride-based semiconductor devices 1B and 1C, a desired electrical distribution can be obtained so as to satisfy different device requirements.
Fig. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present invention. The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A in fig. 1A, except that the concave portion 162D has an inclined side surface. The concave portion 162D and the flat portion 164D share the same inclined side surface. Since the doped nitride-based semiconductor layer 22D is conformally covered by the nitride-based semiconductor layer 16D, each of the portions 222D and 224D may have an inclined side surface. With this configuration, the contact area between the nitride-based semiconductor layer 16D and the doped nitride-based semiconductor layer 22D can be further increased. In this way, more dopant in the doped nitride-based semiconductor layer 22D may help deplete the zone of the 2DEG region.
Fig. 6 is a top view of a nitride-based semiconductor device 1E according to some embodiments of the present invention. The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A in fig. 1A,1b, and 1C, except that the concave portion 162E has a profile with a gradually changing width, such as a trapezoidal profile and an inverted trapezoidal profile. Specifically, the trapezoidal profile and the inverted trapezoidal profile are alternately arranged along the direction D1. The trapezoidal profile and inverted trapezoidal profile have sloped edges/boundaries so that more lateral area can be provided to deplete the 2DEG area for the normally off state.
The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially," "essentially," "about," and "approximately" are used to describe and illustrate minor variations. When used in connection with an event or circumstance, the term can include instances where the event or circumstance occurs precisely and instances where it occurs approximately. For example, when used in conjunction with a numerical value, these terms may encompass a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces lying along a same plane within a micrometer-scale distance, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm lying along the same plane.
As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass a situation in which a previous component is disposed directly on (e.g., in physical contact with) a subsequent component, as well as a situation in which one or more intermediate components are located between the previous component and the subsequent component.
While the invention has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations are not necessarily drawn to scale. There may be a distinction between artistic reproductions and actual devices in the present invention due to manufacturing processes and tolerances. Further, it should be understood that the actual devices and layers may deviate from the rectangular layer depiction of the drawings due to fabrication processes such as conformal deposition, etching, etc., and may include corner surfaces or edges, rounded corners, etc. Other embodiments of the invention not specifically shown are possible. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present invention. All such modifications are intended to be included within the scope of the following claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Thus, unless specifically indicated herein, the order and grouping of operations is not limiting.
Claims (25)
1. A nitride-based semiconductor device comprising:
A first nitride-based semiconductor layer;
A second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a larger band gap than the first nitride-based semiconductor layer, thereby forming a heterojunction and a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction, wherein the second nitride-based semiconductor layer has a plurality of concave portions and a plurality of flat portions alternately arranged along a first direction; and
A doped nitride-based semiconductor layer conformally covering the second nitride-based semiconductor layer and having a plurality of first portions and a plurality of second portions, wherein the first portions respectively cover the recessed portions and the second portions respectively cover the flat portions,
Wherein the doped nitride-based semiconductor layer has a first profile in a first vertical cross-sectional view of the nitride-based semiconductor device through the first portion; and
The doped nitride-based semiconductor layer has a second profile in a second vertical cross-sectional view through the second portion,
Wherein the second profile is different from the first profile.
2. The nitride-based semiconductor device of any one of the preceding claims, wherein the recessed portion of the second nitride-based semiconductor layer extends in a second direction different from the first direction.
3. The nitride-based semiconductor device of any one of the preceding claims, wherein the recessed portions of the second nitride-based semiconductor layer are arranged at equal intervals along the first direction.
4. The nitride-based semiconductor device of any one of the preceding claims, wherein in a top view of the nitride-based semiconductor device, a profile of at least one of the recessed portions has a curved or straight edge.
5. A nitride-based semiconductor device according to any one of the preceding claims, wherein at least one of the recessed portions has a profile of gradually changing width in a top view of the nitride-based semiconductor device.
6. The nitride-based semiconductor device of any one of the preceding claims, wherein the first portions of the doped nitride-based semiconductor layer are each bounded by the recessed portions.
7. The nitride-based semiconductor device of any one of the preceding claims, wherein a top surface of the first portion is lower than a top surface of the second portion.
8. A nitride-based semiconductor device according to any one of the preceding claims, wherein at least one of the recessed portions has at least one inclined side surface.
9. The nitride-based semiconductor device of any one of the preceding claims, wherein the first profile of the doped nitride-based semiconductor layer is a profile having a variable width.
10. The nitride-based semiconductor device of any one of the preceding claims, wherein the second profile of the doped nitride-based semiconductor layer is a rectangular profile.
11. The nitride-based semiconductor device of any one of the preceding claims, wherein in a third vertical cross-sectional view of the nitride-based semiconductor device comprising the first direction, wherein the flat portion is surrounded by the doped nitride-based semiconductor layer such that side and top surfaces of the flat portion are in contact with the doped nitride-based semiconductor layer.
12. The nitride-based semiconductor device of any one of the preceding claims, wherein a width of the recessed portion of the second nitride-based semiconductor layer is less than a width of the doped nitride-based semiconductor layer.
13. A nitride-based semiconductor device according to any one of the preceding claims, further comprising a gate electrode disposed on the doped nitride-based semiconductor layer, and a source electrode and a drain electrode disposed on the second nitride-based semiconductor layer, wherein the gate electrode is located between the source electrode and the drain electrode.
14. A nitride-based semiconductor device according to any one of the preceding claims, wherein the gate, the source and the drain electrodes each extend along the first direction to form a stripe-like profile.
15. The nitride-based semiconductor device of any one of the preceding claims, wherein the first portion of the doped nitride-based semiconductor layer is spaced apart from the gate in the first vertical cross-sectional view.
16. A method of manufacturing a nitride-based semiconductor device, comprising:
forming a first nitride-based semiconductor layer;
Forming an intermediate nitride-based semiconductor layer on the first nitride-based semiconductor layer, wherein a band gap of the intermediate nitride-based semiconductor layer is greater than a band gap of the first nitride-based semiconductor layer;
Removing portions of the intermediate nitride-based semiconductor layer to form a second nitride-based semiconductor layer having a plurality of concave portions separated from each other and a plurality of flat portions alternately arranged in a first direction; and
Forming a doped nitride-based semiconductor layer to cover at least the concave portion and the flat portion such that the doped nitride-based semiconductor layer has a plurality of first portions and a plurality of second portions, wherein the first portions cover the concave portion and the second portions cover the flat portion, respectively,
Wherein the doped nitride-based semiconductor layer has a first profile in a first vertical cross-sectional view through the first portion; and
The doped nitride-based semiconductor layer has a second profile in a second vertical cross-sectional view through the second portion,
Wherein the first profile is different from the second profile.
17. The manufacturing method according to any one of the preceding claims, wherein the first profile is a profile having a variable width.
18. The manufacturing method according to any one of the preceding claims, wherein the second profile is a rectangular profile.
19. The method of any of the preceding claims, further comprising forming a gate electrode on the doped nitride-based semiconductor layer.
20. The method of manufacturing according to any one of the preceding claims, further comprising forming a pair of electrodes on the second nitride-based semiconductor layer.
21. A semiconductor device, comprising:
A channel layer;
A barrier layer disposed on the channel layer and having a plurality of concave portions and a plurality of flat portions separated from each other, wherein each of the flat portions is located between two adjacent concave portions; and
A doped semiconductor layer conformally disposed over the recessed portion and the planar portion such that the doped semiconductor layer has a plurality of first portions respectively received by the recessed portion and a plurality of second portions respectively covering the planar portion,
Wherein in a first vertical cross-sectional view of the semiconductor device through the first portion and the recessed portion therebelow, the doped semiconductor layer has an uneven top surface; and
In a second vertical cross-sectional view of the semiconductor device through the second portion and the planar portion therebelow, the doped semiconductor layer has a planar top surface.
22. The semiconductor device of any of the preceding claims, further comprising a source and a drain disposed on two opposite sides of the recessed portion.
23. A semiconductor device according to any preceding claim, wherein each of the recessed portions extends in a direction from the source towards the drain.
24. A semiconductor device according to any preceding claim, further comprising a gate disposed between the source and drain.
25. A semiconductor device according to any preceding claim, wherein the gate, the source and the drain each extend in a first direction to form a stripe-like profile.
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| PCT/CN2022/134082 WO2024108489A1 (en) | 2022-11-24 | 2022-11-24 | Nitride-based semiconductor device and method for manufacturing the same |
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| US9543391B2 (en) * | 2011-10-19 | 2017-01-10 | Samsung Electronics Co., Ltd. | High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same |
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