WO2024040465A1

WO2024040465A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024040465A1
Application number: PCT/CN2022/114500
Authority: WO
Inventors: Qingyuan HE; Ronghui Hao; Wei Wang; Wen-Yuan HSIEH; Lixiang SHAO; King Yuen Wong
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-08-24
Filing date: 2022-08-24
Publication date: 2024-02-29
Also published as: CN118302864A

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, and a gate electrode. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and has an epitaxy portion making contact with the second nitride-based semiconductor layer and an amorphous portion connected to and located on the epitaxy portion. The gate electrode is disposed over the amorphous portion of the doped nitride-based semiconductor layer.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Qingyuan HE, Ronghui HAO, Wei WANG, Wen-Yuan HSIEH, Lixiang SHAO, King Yuen WONG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device with a gate structure having an amorphous portion.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and has an epitaxy portion making contact with the second nitride-based semiconductor layer and an amorphous portion connected to and located on the epitaxy portion. The gate electrode is disposed over the amorphous portion of the doped nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed over a substrate. A second nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. A blanket doped nitride-based semiconductor layer is formed over the second nitride-based semiconductor layer. An annealing process is performed on the blanket doped nitride-based semiconductor layer, such that hydrogen elements in the blanket doped nitride-based semiconductor layer dissipate. A surface treatment is performed on the blanket doped nitride-based semiconductor layer, such that a top portion of the blanket doped nitride-based semiconductor layer is converted to an amorphous portion of a doped nitride-based semiconductor layer. A gate electrode is formed over the amorphous portion of the doped nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a gate structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The gate structure is disposed over the second nitride-based semiconductor layer. The gate structure includes a doped nitride-based semiconductor layer, a gate electrode, and a blocking layer. The doped nitride-based semiconductor layer is in contact with the second nitride-based semiconductor layer. The gate electrode is disposed over the doped nitride-based semiconductor layer. The blocking layer is disposed between the gate electrode and the doped nitride-based semiconductor layer, such that hydrogen elements in the doped nitride-based semiconductor layer accumulate at a position adjacent to an interface formed between the doped nitride-based semiconductor layer and the blocking layer.

By the above configuration, in the present disclosure, at least a part of a top portion of the doped nitride-based semiconductor layer is converted to be an amorphous portion by performing a surface treatment. The amorphous portion can prevent from the hydrogen elements diffusing upwardly, so the electrical property of the Schottky diode/interface would not be affected by hydrogen elements. Also, since the resistivity of the amorphous portion is greater than the remaining portion of the doped nitride-based semiconductor layer, the amorphous portion can reduce gate leakage and improve breakdown voltage of the gate structure, thereby enhancing the reliability of the gate structure. As a result, the nitride-based semiconductor device of the present disclosure can have good electrical properties.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is an enlarged vertical cross-sectional view of a region in the FIG. 1A;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a semiconductor packaged device according to some embodiments of the present disclosure.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 7 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 8 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 9 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

FIG. 10 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. FIG. 1B is an enlarged vertical cross-sectional view of a region A in the FIG. 1A. The nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 20, 30, a gate structure (including a doped nitride-based semiconductor layer 40A and a gate electrode 50) , a dielectric layer 60, and

electrodes

70, 80.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A can include a buffer layer (not shown) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 20. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 20, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 20 can be disposed on/over/above the substrate 10. The nitride-based semiconductor layer 30 can be disposed on/over/above the nitride-based semiconductor layer 20. The exemplary materials of the nitride-based semiconductor layer 20 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 20 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 20 and 30 are selected such that the nitride-based semiconductor layer 30 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 20, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 20 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 30 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 20 and 30 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

In order to achieve an enhancement mode device, a gate structure including a p-type doped GaN layer and a gate electrode is usually applied to such the device. A Schottky interface/diode can be formed between the p-type doped GaN layer and the gate electrode. Turn-on voltage of the Schottky diode is low, which is advantageous for achieving a fast switching device. In general, an annealing process is usually performed after the formation of the gate structure for achieving a better device performance. Nevertheless, the hydrogen elements in the p-type doped GaN layer would diffuse upwardly to a position near the Schottky interface/diode by the annealing process. The existence of the hydrogen elements near the Schottky interface/diode would deteriorate the electrical property thereof.

On the other hand, with respect to practical demands, there is a need to apply a p-type doped GaN layer with high hole concentrations in the device. However, due to manufacturing factors, it is difficult to obtain p-type doped GaN layer with high hole concentrations. Specifically, during the formation of the p-type doped GaN layer, hydrogen (H ₂) gas is usually used as carrier gas. The p-type dopants/acceptors, for example, Mg, can form a very stable complex with an incorporated hydrogen, thereby being passivated. Thus, a zone of the 2DEG region under the p-type doped GaN layer cannot be fully depleted. The existence of the Mg–H complex seriously affects the electrical properties of the p-type doped GaN layer, which limits the applications of the device.

At least to overcome the aforesaid issues, the present disclosure provides a novel structure.

Specifically, during the formation of the gate structure, firstly, a blanket doped nitride-based semiconductor layer is formed, in which H ₂ gas is applied during the formation of the blanket doped nitride-based semiconductor layer. Thus, some hydrogen elements would remain in the blanket doped nitride-based semiconductor layer. Then, an in-situ annealing process (i.e., an in-situ rapid thermal process, RTP) is performed on the blanket doped nitride-based semiconductor layer, such that most of hydrogen elements would dissipate/remove from the blanket doped nitride-based semiconductor layer, and a small portion of the hydrogen elements still remain in the blanket doped nitride-based semiconductor layer. The term “in-situ annealing process” means that as a film is grown under a given environmental condition, the film is directly annealed without changing other environmental parameters (such as air pressure) expect temperature. In some embodiments, the blanket doped nitride-based semiconductor layer can be doped with p-type dopants, in which the type of p-type dopants can be Mg. Since most of the hydrogen elements are removed, the probability of forming the hydrogen complex, such as Mg–H complex, can be greatly reduced, thereby enhancing activate rate of p-type dopants in the blanket doped nitride-based semiconductor layer.

After that, a surface treatment, for example a plasma treatment, is performed on the blanket doped nitride-based semiconductor layer, such that a blanket top portion thereof is converted to a blanket amorphous portion. A blanket bottom portion of the blanket doped nitride-based semiconductor layer can serve as a blanket epitaxy portion. To be more specific, by applying the surface treatment to the blanket top portion, the original lattice structure of the blanket top portion would be destroyed, and thus the blanket top portion can be in an amorphous state. On the other hand, the blanket bottom portion is not affected by the surface treatment, so the blanket bottom portion can maintain its original lattice structure. Therefore, the defect density of the blanket amorphous portion is greater than that of the blanket epitaxy portion, and the number of types of crystal orientations of the blanket amorphous portion is greater than that of the blanket epitaxy portion. Since the blanket epitaxy portion and the blanket amorphous portion are manufactured by the same blanket doped nitride-based semiconductor layer, the blanket epitaxy portion and the blanket amorphous portion can include the same III-V group material.

Next, an etching process is performed on the blanket doped nitride-based semiconductor layer, such that a doped nitride-based semiconductor layer 40A including an amorphous portion 404A and an epitaxy portion 402A is formed. It should be noted that the surface treatment is aimed to destroy the original lattice structure of the blanket top portion. Thus, the resistivity of the formed amorphous portion 404A is greater than the epitaxy portion 402A. Then, a gate electrode 50 is formed on the amorphous portion 404A, such that a Schottky interface IF1 is formed therebetween. Then, the gate structure including the doped nitride-based semiconductor layer 40A and the gate electrode 50 can be obtained.

Thereafter,

electrodes

70, 80 can be formed at two opposite sides of the gate structure. Referring to the FIG. 1B, then, another annealing process is performed on the resulted structure, such that the remained hydrogen elements H in the epitaxy portion 402A would diffuse upwardly. The remained hydrogen elements H can be blocked by the amorphous portion 404A. Thus, the amorphous portion 404A can serve as a blocking layer. The amorphous portion 404A is formed to extend from a top surface TS of the doped nitride-based semiconductor layer 40A to form an interface IF2 with the epitaxy portion 402A. The remained hydrogen elements H would accumulate at a position adjacent to the interface IF2. The p-type dopants P would form a plurality of complexes CX with the remained hydrogen elements H adjacent to the interface IF2. Accordingly, the characteristics of Schottky interface IF1 will not be affected by the hydrogen elements H.

On the other hand, the p-type dopants P in the doped nitride-based semiconductor layer 40A would also diffuse upwardly due to the aforesaid another annealing process, and the p-type dopants P can also be blocked by the amorphous portion 404A instead of leaving the epitaxy portion 402A. Therefore, the activate rate of the p-type dopants P can maintain at a high level.

Referring back to FIG. 1A, the thickness T2 the amorphous portion 404A can be determined by the power of the surface treatment. The thickness of the amorphous portion 404A is controlled to be less than that of the epitaxy portion 402A. If the thickness T2 of the amorphous portion 404A is too thick, blocking ability to hydrogen elements of the amorphous portion 404A can be promoted, but the quality of the Schottky interface IF1 would be declined. If the thickness T2 of the amorphous portion 404A is too thin, blocking ability to hydrogen elements of the amorphous portion 404A would be low, but the quality of the Schottky interface IF1 would be improved. In some embodiments, a thickness ratio (T2/T1) of the amorphous portion 404A to the epitaxy portion 402A can be controlled in a range from about 0.05 to about 0.35; and therefore, the trade-off between blocking ability to hydrogen elements and quality of the Schottky interface IF1 issue is a net positive gain.

The doped nitride-based semiconductor layer 40A is disposed on/over/above the nitride-based semiconductor layer 30. The epitaxy portion 402A is in contact with the nitride-based semiconductor layer 30. The amorphous portion 404A is located on/over/above the epitaxy portion 402A. The profile of the amorphous portion 404A can be determined by at least one parameter, such as temperature or pressure. In the embodiments, the profile of the amorphous portion 404A can be a rectangular profile, and the thickness of the amorphous portion 404A is uniform.

The gate electrode 50 is disposed on/over/above the doped nitride-based semiconductor layer 40A. The gate electrode 50 makes contact with the amorphous portion 404A of the doped nitride-based semiconductor layer 40A. A width of the doped nitride-based semiconductor layer 40A is greater than that of the gate electrode 50. In some embodiments, a width of the doped nitride-based semiconductor layer 40A is substantially the same as a width of the gate electrode 50. The relationship of the widths of the doped nitride-based semiconductor layer 40A and the gate electrode 50 can depend on the device design.

In the exemplary illustration of FIG. 1A, the nitride-based semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 50 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 40A may create at least one p-n junction with the nitride-based semiconductor layer 30 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 50 has different characteristics (e.g., different electron concentrations) than the remain of the 2DEG region and thus is blocked.

Due to such mechanism, the nitride-based semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 50 or a voltage applied to the gate electrode 50 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 50) , the zone of the 2DEG region below the gate electrode 50 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 40A can be omitted, such that the nitride-based semiconductor device 1A is a depletion-mode device, which means the nitride-based semiconductor device 1A in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 40A can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 40A can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 20 includes undoped GaN and the nitride-based semiconductor layer 30 includes AlGaN, and the doped nitride-based semiconductor layer 40A is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the nitride-based semiconductor device 1A into an off-state condition.

The exemplary materials of the gate electrode 50 may include metals or metal compounds. The gate electrode 50 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

The dielectric layer 60 is disposed on/over/above the nitride-based semiconductor layer 30 and the gate structure. The dielectric layer 60 covers the nitride-based semiconductor layer 30 and the gate electrode 50. The material of the dielectric layer 60 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 60 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 60 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

The

electrodes

70 and 80 can be disposed on/over/above the nitride-based semiconductor layer 14. The doped nitride-based semiconductor layer 40A and the gate electrode 50 are located between the

electrodes

70, 80. The dielectric layer 60 has a plurality of through holes TH. The

electrodes

70 and 80 penetrate the dielectric layer 60 through the through holes TH, so as to make contact with the nitride-based semiconductor layer 30. In some embodiments, the electrode 70 can serve as a source electrode. In some embodiments, the electrode 70 can serve as a drain electrode. In some embodiments, the electrode 80 can serve as a source electrode. In some embodiments, the electrode 80 can serve as a drain electrode. The role of the

electrodes

70 and 80 depends on the device design.

In some embodiments, the

electrodes

70 and 80 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

70 and 80 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the

electrodes

70 and 80 may be a single layer, or plural layers of the same or different composition. The

electrodes

70 and 80 form ohmic contacts with the nitride-based semiconductor layer 30. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

70 and 80. In some embodiments, each of the

electrodes

70 and 80 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

Different stages of a method for manufacturing the semiconductor packaged device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, nitride-based semiconductor layers 20, 30 are formed on/over/above a substrate 10 in sequence using deposition technique.

Referring to FIG. 2B, a blanket doped nitride-based semiconductor layer 90 is formed on/over/above the nitride-based semiconductor layer 30. An in-situ annealing process is performed on the blanket doped nitride-based semiconductor layer 90, such that most of hydrogen elements H in the blanket doped nitride-based semiconductor layer 90 dissipate from the blanket doped nitride-based semiconductor layer 90. The in-situ annealing process, for example, can be an in-situ rapid thermal process. Most of hydrogen elements in the blanket doped nitride-based semiconductor layer 90 would dissipate by the annealing process, and a small portion of hydrogen elements still remain in the blanket doped nitride-based semiconductor layer 90.

Referring to FIG. 2C, a surface treatment ST is performed on the annealed blanket doped nitride-based semiconductor layer 90, such that a top portion of the blanket doped nitride-based semiconductor layer 90 is converted to a blanket amorphous portion AP and a bottom portion of the blanket doped nitride-based semiconductor layer 90 can serve as a bottom epitaxy portion EP. In some embodiments, the surface treatment ST can include an argon (Ar) plasma treatment.

Referring to FIG. 2D, an etching process is performed on the blanket doped nitride-based semiconductor layer 90 to remove the excess portions thereof, thereby forming an epitaxy portion 402A and an amorphous portion 404A. Thus, the doped nitride-based semiconductor layer 40A including an epitaxy portion 402A and an amorphous portion 404A is formed. A gate electode 50 is formed on/over/above the amorphous portion 404A of the doped nitride-based semiconductor layer 40A. Thereafter, the dielectric layer 60, and the

electrodes

70, 80 can be formed in sequence, obtaining the nitride-based semiconductor device 1A in the FIG. 1A.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that a thickness of the amorphous portion 404B is non-uniform, and a distance between the electrode 70 and the gate electrode 50 is less than a distance between the electrode 80 and the gate electrode 50. Specifically, the doped nitride-based semiconductor layer 40B has two opposite sides S1, S2. The thickness of the amorphous portion 404B gradually decreases along a direction from the side S1 to the side S2. The gate electrode 50 is disposed on a relatively thicker portion of the amorphous portion 404B. Therefore, a thickness distribution of the amorphous portion 404B can be adjusted according to position of the gate electrode 50, so the Schottky interface/diode IF1 can be fully protected from the amorphous portion 404B. An interface IF2 formed between the epitaxy portion 402B and the amorphous portion 404B can be curved.

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to nitride-based semiconductor device 1B as described and illustrated with reference to FIG. 4, except that the amorphous portion 404C has a triangle profile.

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to nitride-based semiconductor device 1B as described and illustrated with reference to FIG. 5, except that the amorphous portion 404D has a trapezoid profile.

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the amorphous portion 404E has sub-portions P1 to P3 with different thicknesses. The thickness of the sub-portion P1 is greater than that of the sub-portion P2, and the thickness of the sub-portion P2 is greater than that of the sub-portion P3. Thus, the amorphous portion 404E can have a step profile. The sub-portion P2 is located between the sub-portions P1, P3. The sub-portion P2 is located directly under the gate electrode 50.

FIG. 7 is a vertical cross-sectional view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure. Nitride-based semiconductor device 1F is similar to nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the amorphous portion 404E has sub-portions P1 to P3. The portion P2 is thinner than the portions P1, P3. The portion P2 is located between the portions P1, P3, and the portion P2 is located directly under the gate electrode 50.

FIG. 8 is a vertical cross-sectional view of a nitride-based semiconductor device 1G according to some embodiments of the present disclosure. The nitride-based semiconductor device 1G is similar to nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the amorphous portion 404G has sub-portions P1 to P3. The portion P2 is thicker than the portions P1, P3. The portion P2 is located between the portions P1, P3, and the portion P2 is located directly under the gate electrode 50.

FIG. 9 is a vertical cross-sectional view of a nitride-based semiconductor device 1G according to some embodiments of the present disclosure. Nitride-based semiconductor device 1H is similar to nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the amorphous portion 404H has a plurality of separated sub-portions. The sub-portions are arranged at equal intervals. Although the gate electrode 50 still makes contact with the epitaxial portion 402H, the Schottky interface IF1 may be affected by the remained hydrogen elements, but the amorphous portion 404H still can block most of remained hydrogen elements. Since a contact area between the gate electrode 50 and the epitaxy portion 402H is increased, the electrical properties of the Schottky interface IF1 can be enhanced.

FIG. 10 is a vertical cross-sectional view of a nitride-based semiconductor device 1I according to some embodiments of the present disclosure. Nitride-based semiconductor device 1I is similar to nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the epitaxial portion 402I surrounds the amorphous portion 404I, such that top surfaces of the amorphous portion 404I and the epitaxial portion 402I collectively forms a top surface of the doped nitride-based semiconductor layer 40I.

Based on the above descriptions, in the present disclosure, during the formation of the doped nitride-based semiconductor layer, a pre-annealing process is performed on a blanket doped nitride-based semiconductor layer, such that most of hydrogen elements in the blanket doped nitride-based semiconductor layer can dissipate from the blanket doped nitride-based semiconductor layer, which is advantageous to improve activate rate of the dopants in the doped nitride-based semiconductor layer.

Next, by performing a surface treatment on a top portion of the annealed blanket doped nitride-based semiconductor layer, such that the top portion can be converted to an amorphous portion with high resistivity. The introduction of amorphous portion with high resistance in the gate structure can reduce gate leakage and increase the breakdown voltage of the gate structure, so as to improve the reliability of the gate structure. Then, a post annealing process is performed on the resulted structure. Thermal diffusion of the remaining hydrogen elements in the doped nitride-based semiconductor layer would be blocked by the amorphous portion; and therefore, the probability of the hydrogen elements diffusing to a position near the Schottky interface can be greatly reduced. As a result, the nitride-based semiconductor device of the present disclosure can have good electrical properties.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a ban-dgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;

a doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and having an epitaxy portion making contact with the second nitride-based semiconductor layer and an amorphous portion connected to and located on the epitaxy portion; and

a gate electrode disposed over the amorphous portion of the doped nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, wherein defect density of the amorphous portion is greater than that of the epitaxy portion.
The nitride-based semiconductor device of claim 1, wherein a thickness of the amorphous portion is less than that of the epitaxy portion.
The nitride-based semiconductor device of claim 3, wherein a thickness ratio of the amorphous portion to the epitaxy portion is in a range from about 0.05 to about 0.35.
The nitride-based semiconductor device of claim 1, wherein the amorphous portion extends downward from a top surface of the doped nitride-based semiconductor layer to form an interface with the epitaxy portion.
The nitride-based semiconductor device of claim 5, wherein the epitaxy portion of the doped nitride-based semiconductor layer comprises a plurality of hydrogen elements adjacent to the interface.
The nitride-based semiconductor device of claim 1, wherein a thickness of the amorphous portion is uniform.
The nitride-based semiconductor device of claim 7, wherein the amorphous portion has a rectangular profile.
The nitride-based semiconductor device of claim 1, wherein a thickness of the amorphous portion is non-uniform.
The nitride-based semiconductor device of claim 9, wherein the doped nitride-based semiconductor layer has a first side and a second side which is opposite to the first side, wherein the thickness of the amorphous portion gradually decreases along a direction from the first side to the second side.
The nitride-based semiconductor device of claim 9, wherein the amorphous portion has a triangle profile, or a trapezoid profile.
The nitride-based semiconductor device of claim 9, wherein the amorphous portion has sub-portions with different thicknesses.
The nitride-based semiconductor device of claim 1, wherein resistivity of the amorphous portion is greater than that of the epitaxy portion.
The nitride-based semiconductor device of claim 1, further comprising a dielectric layer covering the doped nitride-based semiconductor layer and the gate electrode.
The nitride-based semiconductor device of claim 1, further comprising two electrodes disposed over the second nitride-based semiconductor layer, wherein the doped nitride-based semiconductor layer and the gate electrode are located between the two electrodes.
A manufacturing method of a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer over a substrate;

forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;

forming a blanket doped nitride-based semiconductor layer over the second nitride-based semiconductor layer;

performing an annealing process on the blanket doped nitride-based semiconductor layer, such that at least a portion of hydrogen elements in the blanket doped nitride-based semiconductor layer dissipate;

performing a surface treatment on the blanket doped nitride-based semiconductor layer, such that a top portion of the blanket doped nitride-based semiconductor layer is converted to an amorphous portion of a doped nitride-based semiconductor layer; and

forming a gate electrode over the amorphous portion of the doped nitride-based semiconductor layer.
The method of claim 16, wherein a remaining portion of the blanket doped nitride-based semiconductor layer under the amorphous portion serves as an epitaxy portion of the doped nitride-based semiconductor layer.
The method of claim 17, wherein a thickness ratio of the amorphous portion to the epitaxy portion is in a range from about 0.05 to about 0.35.
The method of claim 17, wherein resistivity of the amorphous portion is greater than that of the epitaxy portion.
The method of claim 17, wherein the surface treatment comprises an argon plasma treatment.
A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction; and

a gate structure disposed over the second nitride-based semiconductor layer, wherein the gate structure comprises:

a doped nitride-based semiconductor layer in contact with the second nitride-based semiconductor layer;

a gate electrode disposed over the doped nitride-based semiconductor layer; and

a blocking layer disposed between the gate electrode and the doped nitride-based semiconductor layer, such that hydrogen elements in the doped nitride-based semiconductor layer accumulate at a position adjacent to an interface formed between the doped nitride-based semiconductor layer and the blocking layer.
The nitride-based semiconductor device of claim 21, wherein the doped nitride-based semiconductor layer and the blocking layer comprises the same III-V group material.
The nitride-based semiconductor device of claim 21, wherein the blocking layer is in an amorphous state.
The nitride-based semiconductor device of claim 23, wherein the number of types of crystal orientations of the blocking layer is greater than that of the doped nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 21, wherein the doped nitride-based semiconductor layer is doped with p-type dopants such that the each of the p-type dopants form a complex with one of the hydrogen elements adjacent to the interface.