CN118426707A - Storage device and data processing method thereof - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
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Abstract
The invention provides a storage device and a data processing method thereof, wherein the storage device comprises: the flash memory comprises a plurality of blocks and is used for storing a data mapping table and host data, wherein the data mapping table stores mapping information of logical addresses and physical addresses of the host data and comprises a plurality of data mapping fragments; and the main controller is electrically connected with the flash memory and is used for reading a plurality of data mapping fragments and counting continuous values of the data mapping fragments, and in the data mapping fragments, if physical addresses corresponding to two adjacent logical addresses are also adjacent, two adjacent host data are continuous, and the continuous values are expressed as continuous numbers of the two adjacent host data in the data mapping fragments; the main controller shifts the host data in the block based on the continuous values of the plurality of data mapping fragments so that the host data corresponding to the plurality of data mapping fragments is continuous. The invention improves the reading efficiency of host data in the storage device.
Description
Technical Field
The present invention relates to the field of static memory technologies, and in particular, to a storage device and a data processing method thereof.
Background
Memory chips are a specific application of the concept of embedded system chips in the memory industry. Whether a system chip or a memory chip, the system chip and the memory chip are realized by embedding software in a single chip, so that the system chip can realize multifunction, high performance and support to various protocols, various hardware and different applications. The memory chip is widely applied to the fields of computers, mobile equipment, internet of things and the like, and is used for storing various data such as an operating system, application programs, music, videos, photos and the like.
The service performance of the data stored in the flash memory of the memory chip is affected by the data reading performance, and the condition that the memory system runs slowly can occur due to the poor reading performance of the memory chip at present. Therefore, there is a need for improvement.
Disclosure of Invention
The invention provides a storage device and a data processing method thereof, which are used for solving the technical problems that the reading performance of a storage chip is poor and the operation of a storage system is slow in the prior art.
The invention provides a storage device, comprising:
the flash memory comprises a plurality of blocks and is used for storing a data mapping table and host data, wherein the data mapping table stores mapping information of logical addresses and physical addresses of the host data, and the data mapping table comprises a plurality of data mapping fragments; and
The main controller is electrically connected with the flash memory and is used for reading a plurality of data mapping fragments and counting continuous values of the data mapping fragments, and in the data mapping fragments, if physical addresses corresponding to two adjacent logical addresses are also adjacent, two adjacent host data are continuous, and the continuous values are expressed as the continuous quantity of the two adjacent host data in the data mapping fragments;
And the main controller shifts the host data in the block based on the continuous values of the data mapping fragments so that the host data corresponding to the data mapping fragments are continuous.
In one embodiment of the present invention, when the continuous value of a certain data mapping segment is smaller than a continuous threshold value, the main controller moves host data associated with the data mapping segment, so that host data corresponding to the data mapping segment is continuous;
And when the continuous value of a certain data mapping fragment is larger than or equal to a continuous threshold value, the main controller does not move the host data associated with the data mapping fragment.
In one embodiment of the present invention, when the continuous value of a certain data mapping segment is smaller than the continuous threshold, the host controller reads host data on a corresponding physical address according to the sequence of the logical addresses in the data mapping segment, and moves the host data to a block according to the read sequence, so that the host data associated with the data mapping segment is continuous.
In one embodiment of the present invention, the flash memory includes a system block and a user block, the system block is configured to store firmware, the firmware is configured to move host data associated with a data mapping segment when a continuous value of the data mapping segment is less than a continuous threshold, and the firmware is configured to not move host data associated with the data mapping segment when the continuous value of the data mapping segment is greater than or equal to the continuous threshold;
the user block is used for storing a data mapping table and host data, and the main controller is used for performing read-write and erasure processing on the host data on the user block.
In one embodiment of the present invention, when the capacity of host data in a write block reaches 1/N of the total capacity of the flash memory, the host controller counts the continuous values of the plurality of data mapping segments, and performs a moving process on the host data in the block based on the continuous values of the plurality of data mapping segments, where N is a positive integer, and 4N is less than or equal to 10.
In one embodiment of the present invention, the host controller reads the host data associated with one page in the data mapping fragment for a time T, which satisfies the following conditions:
T=（1~M/L）Tr+Tdma；
Wherein, M is the data amount of one page in the data mapping segment, L is the unit data amount corresponding to each physical address, M/L is the number of physical addresses needed for one page in the data mapping segment, tr is the time when the page on the block prepares the host data after receiving the host controller read command, tdma is the time when the host data is output to the host controller along with the clock signal, and Tdma is positively correlated with the data amount of the host controller read host data.
In one embodiment of the present invention, a plurality of the data mapping fragments are arranged in a segment management order;
The main controller is used for counting the continuous values of a plurality of the data mapping fragments according to the segmentation management sequence and carrying out moving processing on the host data in the block based on the continuous values of the data mapping fragments.
The invention also provides a data processing method of the storage device, which comprises the following steps:
Storing a data mapping table and host data into a plurality of blocks of a flash memory, wherein the data mapping table stores mapping information of logical addresses and physical addresses of the host data, and the data mapping table comprises a plurality of data mapping fragments;
in the data mapping segment, host data of which the physical addresses corresponding to the two adjacent logical addresses are also adjacent are recorded as continuous, and the continuous number of the two adjacent host data in the data mapping segment is recorded as continuous value;
Reading a plurality of data mapping fragments, and counting continuous values of the plurality of data mapping fragments;
and according to the continuous values of the data mapping fragments, moving the host data in the block so that the host data corresponding to the data mapping fragments are continuous.
In one embodiment of the present invention, the step of moving the host data in the block according to the continuous values of the plurality of data mapping fragments so that the host data in the plurality of data mapping fragments is continuous includes:
When the continuous value of a certain data mapping fragment is smaller than the continuous threshold value, moving host data associated with the data mapping fragment so that the host data corresponding to the data mapping fragment is continuous;
And when the continuous value of a certain data mapping fragment is greater than or equal to a continuous threshold value, host data associated with the data mapping fragment is not moved.
In one embodiment of the present invention, the step of moving host data associated with a data mapping fragment when a continuous value of the data mapping fragment is smaller than a continuous threshold value includes:
when the continuous value of a certain data mapping segment is smaller than a continuous threshold value, reading host data on a corresponding physical address according to the sequence of the logical addresses in the data mapping segment;
And moving the host data to a block according to the reading sequence, so that the host data associated with the data mapping fragments are continuous.
The invention has the beneficial effects that: the storage device and the data processing method thereof provided by the invention have very good reading performance when the host machine carries out continuous reading action on the storage device, and can improve the service performance and the service life of the storage device.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the invention.
Fig. 2 is a diagram of mapping information of logical addresses and physical addresses in a data mapping table according to an embodiment of the present invention.
FIG. 3 is a schematic diagram illustrating a method for moving host data in a block according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of moving host data in a block according to another embodiment of the present invention.
Fig. 5 is a schematic diagram of moving host data in a block according to another embodiment of the present invention.
Fig. 6 is a schematic diagram of a system block and a user block in a flash memory according to an embodiment of the invention.
Fig. 7 is a schematic diagram illustrating steps of a data processing method of a memory device according to an embodiment of the invention.
Fig. 8 is a schematic diagram illustrating a step S40 in fig. 6 according to an embodiment of the invention.
Fig. 9 is a schematic diagram of step S410 in fig. 7 according to an embodiment of the invention.
Description of the reference numerals
10. A host; 20. a storage device; 30. a main controller; 31. a central processing unit; 32. a dynamic random access memory unit; 40. a flash memory; 41. a block; 410. a system block; 411. a user block; 42. pages.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
Referring to fig. 1 to 9, the present invention provides a storage device and a data processing method thereof, which can be applied to memory devices such as eMMC (Embedded Multi MEDIA CARD), SSD (Solid STATE DISK ), UFS (Univeral Flash Storage, universal flash memory) and the like. The invention can carry out the moving process on the host data in the block 41, wherein the host data is the application data written by the host 10, and the reading efficiency of the host 10 on the host data in the storage device 20 is improved, so that the service performance and the service life of the storage device 20 can be further improved. The following is a detailed description of specific embodiments.
Referring to fig. 1 and 2, in an embodiment of the invention, a memory device 20 is provided, the memory device 20 is provided with a bus interface, the memory device 20 is electrically connected to a host 10 through the bus interface, the host 10 can write host data and send commands to the memory device 20, or the host 10 can read host data and receive commands from the memory device 20. The host 10 may be a communication device such as a personal computer (PC, personal Computer), a tablet (Pad), a mobile Phone (Cell Phone), etc.
Referring to fig. 1, in one embodiment of the present invention, a memory device 20 may include a main controller 30 and a flash memory 40. The flash memory 40 is a nonvolatile memory, and is generally used for storing host data, system programs, and the like. The main controller 30 is mainly used for operating and managing the flash Memory 40, and the main controller 30 also provides functions of Cache (Cache), memory array (Memory array), and interleaving (interleaving). The main controller 30 is electrically connected to the flash memory 40, and the main controller 30 can control various functions of the flash memory 40, such as bad fast management, wear leveling, error Checking and Correction (ECC), etc., and the main controller 30 can greatly improve the read-write and moving performance of host data in the flash memory 40.
Referring to fig. 1, in an embodiment of the present invention, a flash memory interface is disposed on a main controller 30 inside a memory device 20, and the main controller 30 is electrically connected to a flash memory 40 through the flash memory interface. The main controller 30 may include a central processing unit (CPU, central Processing Unit) 31 and a dynamic random access memory (DRAM, dynamic Random Access Memory) 32, the central processing unit 31 being an operation core and a control core of the storage device 20, the dynamic random access memory 32 being an internal memory that directly exchanges data with the central processing unit 31, also referred to as a main memory (internal memory). In the memory device 20, the flash memory 40 is not a memory for directly exchanging data with the central processing unit 31, and thus the flash memory 40 is an auxiliary memory (external memory).
Specifically, when the host 10 writes host data to the storage device 20, the host data of the host 10 is stored in the dynamic random access memory unit 32, and the dynamic random access memory unit 32 then transmits the host data of the host 10 to the flash memory 40. In the case that the host 10 reads data from the storage device 20, the host data in the flash memory 40 is stored in the dynamic random access memory unit 32, and then the dynamic random access memory unit 32 sends the host data of the flash memory 40 to the host 10.
Specifically, in the case where the host 10 transmits an instruction or receives an instruction to the storage device 20, the host controller 30 buffers the host data related to the transmission instruction or the reception instruction through the dynamic random access memory unit 32, and then processes the host data accordingly based on the transmission instruction or the reception instruction.
Referring to fig. 1 and 2, in one embodiment of the present invention, the flash memory 40 may include a plurality of blocks (blocks) 41, the blocks 41 may be used to store a data mapping table and host data written by the host 10, and one Block 41 may further include a plurality of pages (pages) 42. As shown in fig. 2, the data mapping table stores mapping information of logical addresses and physical addresses of host data, the logical addresses being relative addresses used in user programs, also referred to as virtual addresses, and the logical addresses being generated by the central processing unit 31 for accessing data in the flash memory 40. The physical address is a real address in the flash memory 40, also referred to as a real address. The mapping information in the data mapping table is queried by using the logical address, so that the corresponding physical address can be found, and then the host data on the corresponding physical address in the flash memory 40 is subjected to the processes of reading, writing, moving and the like. The data mapping table records the mapping relationship between all logical addresses and physical addresses in the storage device 20, and the storage device 20 performs segment management on the data mapping table because the data mapping table is relatively large. The data mapping table may include a plurality of data mapping fragments, such as data mapping fragment 1, data mapping fragment 2, data mapping fragments 3, … …, data mapping fragment X.
Specifically, the dynamic random access unit 32 may be used to store temporary data of program operation, so that the data mapping table is stored in the dynamic random access unit 32 and can be accessed conveniently and quickly. In addition, the flash memory 40 may store a data mapping table to prevent the data loss after the power-off of the storage device 20, and the central processing unit 31 may also periodically update the data mapping table in the flash memory 40.
Referring to fig. 2 and 3, in one embodiment of the present invention, the main controller 30 may read a plurality of data mapping fragments and count consecutive values of the data mapping fragments. In the data mapping fragment, if the physical addresses corresponding to the adjacent two logical addresses are also adjacent, the adjacent two host data are consecutive. The consecutive value is expressed as the number of consecutive host data in the data map segment. For example, in the data mapping fragment of fig. 2, the logical addresses are 1,2, 3, 4,5, 6 … …, and the physical addresses are 2,3, 5, 88, 17, 62, wherein the numbers related to the logical addresses and the physical addresses only represent the cis-position relationship, and do not represent specific logical addresses and physical addresses. In fig. 2, the logical addresses are consecutive, but the physical addresses to which the logical addresses correspond are not consecutive, 2 to which the logical addresses correspond to 3 to which the logical addresses correspond to 5 to which the logical addresses correspond, and the two host data are not consecutive.
Referring to fig. 2 and 3, in an embodiment of the present invention, in an idle state of the storage device 20, the host controller 30 may move the host data in the block 41 based on the continuous values of the plurality of data mapping fragments, so that the host data in the plurality of data mapping fragments are continuous. The idle state of the storage device 20 means that no read/write operation is performed between the host 10 and the storage device 20. As shown in fig. 3, fig. 3 is a case where two adjacent logical addresses correspond to host data on the same block 41. If the host data at the physical address corresponding to the two adjacent logical addresses is A, B, then the host data A, B is not adjacent. If the host data A, B in the first block 41 is to be moved so that the corresponding host data A, B in the data map segment is continuous, the following operation is required.
First, the central processing unit 31 reads the host data A, B in the first block 41 into the dynamic random access memory unit 32, and second, for the host data A, B cached on the dynamic random access memory unit 32, the central processing unit 31 writes the host data A, B to two adjacent physical addresses on the second block 41, so that the host data A, B is continuous. In the data mapping fragment, the logical address corresponding to the host data A, B is unchanged, and the physical address corresponding to the host data A, B is changed. The mapping information of the data mapping fragment with respect to the host data A, B is updated, i.e., the host data A, B on the first block 41 becomes invalid data and the host data A, B on the second block 41 becomes valid data.
In addition, it should be noted that, after the host data A, B on the first block 41 in fig. 3 is moved, if the first block 41 needs to be erased, the following operation is required. As shown in fig. 4, when all host data on the first block 41 is moved, all host data on the first block 41 becomes invalid data, and then the first block 41 is erased, so that the first block 41 has a plurality of free pages 42 to be written with new host data.
Referring to fig. 5, in one embodiment of the present invention, the host controller 30 may move the host data in the block 41 based on the continuous values of the plurality of data mapping fragments, so that the host data in the plurality of data mapping fragments are continuous. Fig. 5 shows a case where two adjacent logical addresses correspond to host data on different blocks 41. If the host data at the physical address corresponding to the two adjacent logical addresses is A, B, then the host data A, B is not adjacent. If the host data a in the first block 41 and the host data B in the second block 41 are to be moved so that the corresponding host data A, B in the data map section is continuous, the following operation is required.
Firstly, the central processing unit 31 reads the host data a in the first block 41 and the host data B in the second block 41 into the dynamic random access memory unit 32, and secondly, for the host data A, B cached on the dynamic random access memory unit 32, the central processing unit 31 writes the host data A, B to two adjacent physical addresses on the third block 41 so that the host data A, B is continuous. In the data mapping fragment, the logical address corresponding to the host data A, B is unchanged, and the physical address corresponding to the host data A, B is changed. The mapping information of the data mapping fragment with respect to the host data A, B is updated, that is, the host data a on the first block 41, the host data B in the second block 41 become invalid data, and the host data A, B on the third block 41 become valid data.
Referring to fig. 1, 3 and 5, in one embodiment of the present invention, when the continuity value of a certain data mapping fragment is smaller than the continuity threshold, the host controller 30 moves the host data associated with the data mapping fragment, so that the host data corresponding to the data mapping fragment is continuous. When the continuous value of a certain data mapping fragment is equal to or greater than the continuous threshold value, the host controller 30 does not move the host data associated with the data mapping fragment.
Specifically, assuming that the capacity of one data map segment is 8KB (KiloByte), one physical address needs 4B (Byte) to be recorded, one data map segment records 2048 physical addresses. If the continuity threshold is set to 80%, and the continuity value of the data mapping segment is equal to or greater than 1639 (2048×80% = 1638.4), that is, the number of physical addresses corresponding to the continuity of the logical addresses is equal to or greater than 1639, the current data mapping segment is considered to be continuous, and the host data associated with the data mapping segment is not required to be moved. Otherwise, if the continuous value of the data mapping segment is less than 1639, that is, if the number of physical addresses corresponding to the continuous logical addresses is less than 1639, the current data mapping segment is considered to be discontinuous, and the host data associated with the data mapping segment needs to be moved, so that all host data corresponding to the current data mapping segment is continuous.
Referring to fig. 1,3 and 5, in one embodiment of the present invention, when the continuous value of a certain data mapping segment is smaller than the continuous threshold, the host controller 30 reads host data at the corresponding physical address according to the sequence of the logical addresses in the data mapping segment, and moves the host data to a block 41 according to the read sequence, so that the host data associated with the data mapping segment is continuous.
Specifically, as shown in fig. 3 and fig. 5, when the continuous value of a certain data mapping segment is smaller than the continuous threshold, first, according to the sequence of the logical addresses in the data mapping segment, the host data on the physical address corresponding to the logical address may be read into the dynamic random storage unit 32 for caching. Then, the host data in the dynamic random access memory unit 32 is moved to a block 41 according to the sequence of reading the logical addresses, so that the host data associated with the data mapping fragments are continuous.
Referring to fig. 1, 3 and 5, in one embodiment of the present invention, when the capacity of host data in a certain write block 41 reaches 1/N of the total capacity of flash memory 40, the host controller 30 counts the continuous values of a plurality of data mapping fragments, and performs a moving process on the host data in the block 41 based on the continuous values of the plurality of data mapping fragments, wherein N is a positive integer, and N is equal to or greater than 4 and equal to or less than 10.
Specifically, when N is 5 and the random data writing amount of the host 10 exceeds 1/5 of the total capacity of the flash memory 40, the host controller 30 may count the continuous values of the plurality of data mapping fragments and move the host data in the block 41 based on the continuous values of the plurality of data mapping fragments.
Referring to fig. 1,3 and 5, in one embodiment of the present invention, the host controller 30 reads the host data on the associated one page 42 for a time T in the data mapping fragment, which satisfies the following conditions:
T=（1~M/L）Tr+Tdma；
Wherein, M is the data amount of one page 42 associated with each physical address in the data mapping segment, L is the unit data amount corresponding to each physical address, M/L is the number of physical addresses required for one page 42 associated with the data mapping segment, tr is the time when the page 42 on the block 41 prepares the host data after receiving the host controller 30 read command, tdma is the time when the host data is output to the host controller 30 along with the clock signal, and Tdma is positively correlated with the data amount of the host data read by the host controller 30. In the data mapping fragment, for the case that the host data associated with one page 42 are all continuous and the physical addresses are distributed in the same page 42, the continuous value associated with one page 42 in the corresponding data mapping fragment is M/L-1, and only one page 42 needs to be read, where the reading time T is tr+ Tdma. In the data mapping fragment, when host data associated with one page 42 is all discontinuous and physical addresses are distributed in different pages 42, the continuous value associated with one page 42 in the corresponding data mapping fragment is 0, and M/L pages 42 need to be read, where the reading time T is (M/L) tr+ Tdma.
Specifically, the purpose of achieving continuity by moving host data is to improve the reading performance, and the page 42 is a unit of reading of host data. For example, if the partial data size of one page 42 associated in the data mapping fragment is 16KB and the unit data size corresponding to each physical address is 4KB, then the number of physical addresses required is 4 if the partial data size of one page 42 associated in the data mapping fragment is 16 KB. Specifically, when a 16KB amount of data on one page 42 is associated in a read data mapping fragment, the 16KB of host data will map to 4 physical addresses. If the continuous value of the 16KB data amount on the associated one page 42 in the corresponding data mapping fragment is 0 when the 4 physical addresses are respectively on the different pages 42 of the four blocks 41, then the 4 pages 42 need to be read at this time, and the total time taken to read the 16KB data amount is (tr+4 KBTdma) ×4=4tr+16 kbtdma. After the host controller 30 moves the host data of 16KB, when the 4 physical addresses are on the same page 42 of the same block 41, the continuous value of the data size of 16KB on the associated page 42 in the corresponding data mapping segment is 3, and only 1 page 42 needs to be read at this time, the total time consumed for reading the data size of 16KB is tr+16KBTdma, and the time of 3 Tr is saved. Therefore, the reading time of the host data on the same page 42 is far less than the reading time of the host data on different pages 42, and the invention improves the reading efficiency of the host 10 to the host data in the storage device 20, and can improve the service performance and the service life of the storage device 20.
In addition, it should be noted that when the flash memory 40 reads non-adjacent pages 42 on the same block 41, only serial processing is performed, i.e. after one page 42 is read, another page 42 is read. When reading the discontinuous page 42, for example, the pages 42 numbered N, N +2 and n+4 are read, data preparation cannot be performed in advance during data transmission. Specifically, the page 42 numbered n+2 starts data preparation only after the host data on the page 42 numbered N is read, and then the host data on the page 42 numbered n+2 can be read.
Flash memory 40 provides a degree of parallel processing when successive pages 42 of the same block 41 are read, i.e., during reading of one page 42, the next page 42 is ready for data. When reading consecutive pages 42, for example, pages 42 numbered N, N +1, n+2, data preparation may be performed in advance during data transfer. Specifically, during the process of reading the host data on the N-numbered page 42, the n+1-numbered page 42 starts to perform data preparation, i.e., tr of the n+1-numbered page 42 can be performed simultaneously with Tdma of the N-numbered page 42, thereby saving the reading time. The read time for consecutive pages 42 will be much less than the read time for non-consecutive pages 42. By means of data moving, host data are continuously stored, and therefore reading performance can be greatly improved when the host data are read subsequently.
Referring to fig. 1,3 and 5, in one embodiment of the present invention, the number of data mapping fragments may be plural, and the storage device 20 may segment and manage the plural data mapping fragments. The main controller 30 may be configured to sequentially count consecutive values of the plurality of data mapping fragments according to the segment management order, and perform a moving process on the host data in the block 41 based on the consecutive values of the plurality of data mapping fragments. The main controller 30 counts the continuous values of the plurality of data mapping fragments according to the sequence of segment management and performs a moving process, thereby improving the reading performance of the host data corresponding to the plurality of data mapping fragments.
Referring to fig. 6, in one embodiment of the present invention, the flash memory 40 may include a system block 410 and a user block 411, where the system block 410 is configured to store firmware (FW, firmware) including instructions to move host data associated with a data mapping fragment when a consecutive value of the data mapping fragment is less than a consecutive threshold. The firmware further includes instructions for not moving host data associated with a data mapping fragment when a continuation value of the data mapping fragment is equal to or greater than a continuation threshold value. In the storage device 20, the optimization and improvement in terms of hardware process are not needed, and only the firmware is needed to be modified, so that the reading efficiency of host data in the storage device 20 can be improved, and the service performance and service life of the storage device 20 can be improved. The user block 411 is used for storing a data mapping table and host data written by the host 10, and the host 10 is used for performing read-write and erase processing on the host data on the user block 411.
Specifically, the system block 410 may include a firmware code configuration area, a bad block table and a bad block free area, a system block setup area, a system block pointer area, a boot area, and an encryption area. The system block 410 is a block 41 that is inaccessible to the user, and the flash memory cells of the system block 410 are Single level cell memory (SLC). The user block 411 may include a boot area and an encryption area, a regular user area. The user block 411 is a block 41 that can be accessed by a user, and the flash memory cells of the user block 411 are Single level cell memory (SLC), double level cell Memory (MLC), triple level cell memory (TLC), LEVEL CELL.
Referring to fig. 7, in an embodiment of the present invention, a data processing method of a memory device 20 is provided, which may include the following steps.
Step S10, storing a data mapping table and host data into a plurality of blocks of the flash memory, wherein the data mapping table stores mapping information of logical addresses and physical addresses of the host data, and the data mapping table comprises a plurality of data mapping fragments.
In step S20, in the data mapping segment, the host data whose physical addresses corresponding to the two adjacent logical addresses are also adjacent are recorded as continuous, and the two adjacent host data in the data mapping segment are recorded as continuous numbers and recorded as continuous values.
Step S30, a plurality of data mapping fragments are read, and continuous values of the plurality of data mapping fragments are counted.
Step S40, according to the continuous values of the plurality of data mapping fragments, the host data in the block are shifted so that the host data corresponding to the plurality of data mapping fragments are continuous.
The following is a detailed description of specific embodiments.
Step S10, storing a data mapping table and host data into a plurality of blocks of the flash memory, wherein the data mapping table stores mapping information of logical addresses and physical addresses of the host data, and the data mapping table comprises a plurality of data mapping fragments.
In one embodiment of the present invention, the data mapping table stores mapping information of logical addresses and physical addresses of host data, the logical addresses being relative addresses, also referred to as virtual addresses, used in the user program, the logical addresses being generated by the central processing unit 31 for accessing data in the flash memory 40. The physical address is a real address in the flash memory 40, also referred to as a real address. The mapping information in the data mapping table is queried by using the logical address, so that the corresponding physical address can be found, and then the host data on the corresponding physical address in the flash memory 40 is subjected to the processes of reading, writing, moving and the like.
Specifically, the data mapping table records the mapping relationship between all the logical addresses and the physical addresses in the storage device 20, and the storage device 20 performs segment management on the data mapping table because the data mapping table is relatively large. The data mapping table may include a plurality of data mapping fragments, such as data mapping fragment 1, data mapping fragment 2, data mapping fragments 3, … …, data mapping fragment X.
In step S20, in the data mapping segment, the host data whose physical addresses corresponding to the two adjacent logical addresses are also adjacent are recorded as continuous, and the two adjacent host data in the data mapping segment are recorded as continuous numbers and recorded as continuous values.
In one embodiment of the present invention, in the data mapping fragment, if the physical addresses corresponding to the adjacent two logical addresses are also adjacent, then the adjacent two host data are consecutive. The consecutive value is expressed as the number of consecutive host data in the data map segment. In fig. 2, the logical addresses are consecutive, but the physical addresses to which the logical addresses correspond are not consecutive, 2 to which the logical addresses correspond to 3 to which the logical addresses correspond to 5 to which the logical addresses correspond, and the two host data are not consecutive.
Step S30, a plurality of data mapping fragments are read, and continuous values of the plurality of data mapping fragments are counted.
In one embodiment of the invention, a plurality of data mapping fragments are read, and successive values of the data mapping fragments are counted. For example, in the data mapping fragment of fig. 2, the logical addresses are 1,2, 3, 4, 5, 6 … …, and the physical addresses are 2, 3, 5, 88, 17, 62, wherein the numbers related to the logical addresses and the physical addresses only represent the cis-position relationship, and do not represent specific logical addresses and physical addresses. For the data mapping fragment in fig. 2, the first 6 rows have a consecutive value of 1 and the first 6 rows have a discontinuous value of 4.
Step S40, according to the continuous values of the plurality of data mapping fragments, the host data in the block are shifted so that the host data corresponding to the plurality of data mapping fragments are continuous.
In one embodiment of the present invention, in the idle state of the storage device 20, the host controller 30 may move the host data in the block 41 based on the consecutive values of the plurality of data mapping fragments, such that the host data in the plurality of data mapping fragments is consecutive. The idle state of the storage device 20 means that no read/write operation is performed between the host 10 and the storage device 20. As shown in fig. 3, fig. 3 is a case where two adjacent logical addresses correspond to host data on the same block 41. If the host data at the physical address corresponding to the two adjacent logical addresses is A, B, then the host data A, B is not adjacent. If the host data A, B in the first block 41 is to be moved so that the corresponding host data A, B in the data map segment is continuous, the following operation is required.
First, the central processing unit 31 reads the host data A, B in the first block 41 into the dynamic random access memory unit 32, and second, for the host data A, B cached on the dynamic random access memory unit 32, the central processing unit 31 writes the host data A, B to two adjacent physical addresses on the second block 41, so that the host data A, B is continuous. In the data mapping fragment, the logical address corresponding to the host data A, B is unchanged, and the physical address corresponding to the host data A, B is changed. The mapping information of the data mapping fragment with respect to the host data A, B is updated, i.e., the host data A, B on the first block 41 becomes invalid data and the host data A, B on the second block 41 becomes valid data.
Referring to fig. 7, in an embodiment of the present invention, step S40 may include step S410 and step S420. Step S410 may be represented by shifting host data associated with a data mapping fragment when the continuous value of the data mapping fragment is smaller than the continuous threshold, so that the host data corresponding to the data mapping fragment is continuous. Step S420 may be expressed as not moving host data associated with a certain data mapping fragment when the continuous value of the certain data mapping fragment is equal to or greater than the continuous threshold.
Specifically, assuming that the capacity of one data map segment is 8KB (KiloByte), one physical address needs 4B (Byte) to be recorded, one data map segment records 2048 physical addresses. If the continuity threshold is set to 80%, and the continuity value of the data mapping segment is equal to or greater than 1639 (2048×80% = 1638.4), that is, the number of physical addresses corresponding to the continuity of the logical addresses is equal to or greater than 1639, the current data mapping segment is considered to be continuous, and the host data associated with the data mapping segment is not required to be moved. Otherwise, if the continuous value of the data mapping segment is less than 1639, that is, if the number of physical addresses corresponding to the continuous logical addresses is less than 1639, the current data mapping segment is considered to be discontinuous, and the host data associated with the data mapping segment needs to be moved, so that all host data corresponding to the current data mapping segment is continuous.
Referring to fig. 9, in an embodiment of the present invention, step S410 may include step S411 and step S412. Step S411 may be expressed as reading host data on a corresponding physical address according to the order of logical addresses in a certain data mapping fragment when the consecutive value of the data mapping fragment is smaller than the consecutive threshold. Step S412 may be represented by moving the host data onto a block 41 in the order of reading, so that the host data associated with the data mapping fragment is continuous.
Specifically, as shown in fig. 3 and fig. 5, when the continuous value of a certain data mapping segment is smaller than the continuous threshold, first, according to the sequence of the logical addresses in the data mapping segment, the host data on the physical address corresponding to the logical address may be read into the dynamic random storage unit 32 for caching. Then, the host data in the dynamic random access memory unit 32 is moved to a block 41 according to the sequence of reading the logical addresses, so that the host data associated with the data mapping fragments are continuous.
In summary, the present invention provides a storage device and a data processing method thereof, which can provide a good reading performance and improve the service performance and the service life of the storage device when a host performs a continuous reading operation on the storage device.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A memory device, comprising:
the flash memory comprises a plurality of blocks and is used for storing a data mapping table and host data, wherein the data mapping table stores mapping information of logical addresses and physical addresses of the host data, and the data mapping table comprises a plurality of data mapping fragments; and
The main controller is electrically connected with the flash memory and is used for reading a plurality of data mapping fragments and counting continuous values of the data mapping fragments, and in the data mapping fragments, if physical addresses corresponding to two adjacent logical addresses are also adjacent, two adjacent host data are continuous, and the continuous values are expressed as the continuous quantity of the two adjacent host data in the data mapping fragments;
And the main controller shifts the host data in the block based on the continuous values of the data mapping fragments so that the host data corresponding to the data mapping fragments are continuous.
2. The storage device according to claim 1, wherein the host controller moves host data associated with a data mapping fragment when a continuity value of the data mapping fragment is smaller than a continuity threshold value, so that host data corresponding to the data mapping fragment is continuous;
And when the continuous value of a certain data mapping fragment is larger than or equal to a continuous threshold value, the main controller does not move the host data associated with the data mapping fragment.
3. The storage device according to claim 2, wherein when the continuous value of a certain data mapping segment is smaller than the continuous threshold value, the host controller reads host data at a corresponding physical address according to the sequence of logical addresses in the data mapping segment, and moves the host data to a block according to the read sequence, so that the host data associated with the data mapping segment is continuous.
4. The memory device of claim 2, wherein the flash memory comprises a system block and a user block, the system block configured to store firmware configured to move host data associated with a data mapping fragment when a continuity value of the data mapping fragment is less than a continuity threshold, the firmware configured to not move host data associated with the data mapping fragment when the continuity value of the data mapping fragment is greater than or equal to the continuity threshold;
the user block is used for storing a data mapping table and host data, and the main controller is used for performing read-write and erasure processing on the host data on the user block.
5. The memory device of claim 1, wherein the host controller counts consecutive values of the plurality of data mapping segments when the capacity of host data in a write block reaches 1/N of the total capacity of the flash memory, and performs a moving process on host data in the block based on the consecutive values of the plurality of data mapping segments, wherein N is a positive integer, and N is 4.ltoreq.10.
6. The storage device of claim 1, wherein the master controller reads host data associated with one page in the data mapping fragment for a time T that satisfies:
T=（1~M/L）Tr+Tdma；
Wherein, M is the data amount of one page in the data mapping segment, L is the unit data amount corresponding to each physical address, M/L is the number of physical addresses needed for one page in the data mapping segment, tr is the time when the page on the block prepares the host data after receiving the host controller read command, tdma is the time when the host data is output to the host controller along with the clock signal, and Tdma is positively correlated with the data amount of the host controller read host data.
7. The storage device of claim 1, wherein a plurality of the data mapping fragments are arranged in a segment management order;
The main controller is used for counting the continuous values of a plurality of the data mapping fragments according to the segmentation management sequence and carrying out moving processing on the host data in the block based on the continuous values of the data mapping fragments.
8. A data processing method of a storage device, comprising:
Storing a data mapping table and host data into a plurality of blocks of a flash memory, wherein the data mapping table stores mapping information of logical addresses and physical addresses of the host data, and the data mapping table comprises a plurality of data mapping fragments;
in the data mapping segment, host data of which the physical addresses corresponding to the two adjacent logical addresses are also adjacent are recorded as continuous, and the continuous number of the two adjacent host data in the data mapping segment is recorded as continuous value;
Reading a plurality of data mapping fragments, and counting continuous values of the plurality of data mapping fragments;
and according to the continuous values of the data mapping fragments, moving the host data in the block so that the host data corresponding to the data mapping fragments are continuous.
9. The method according to claim 8, wherein the step of shifting host data in a block according to consecutive values of the plurality of data mapping fragments so that the host data in the plurality of data mapping fragments is consecutive, comprises:
When the continuous value of a certain data mapping fragment is smaller than the continuous threshold value, moving host data associated with the data mapping fragment so that the host data corresponding to the data mapping fragment is continuous;
And when the continuous value of a certain data mapping fragment is greater than or equal to a continuous threshold value, host data associated with the data mapping fragment is not moved.
10. The method for processing data in a storage device according to claim 9, wherein the step of moving host data associated with a data mapping fragment when a consecutive value of the data mapping fragment is smaller than a consecutive threshold value comprises:
when the continuous value of a certain data mapping segment is smaller than a continuous threshold value, reading host data on a corresponding physical address according to the sequence of the logical addresses in the data mapping segment;
And moving the host data to a block according to the reading sequence, so that the host data associated with the data mapping fragments are continuous.
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