CN109671458A - The method of management flash memory module and relevant flash controller - Google Patents
The method of management flash memory module and relevant flash controller Download PDFInfo
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- CN109671458A CN109671458A CN201710967426.8A CN201710967426A CN109671458A CN 109671458 A CN109671458 A CN 109671458A CN 201710967426 A CN201710967426 A CN 201710967426A CN 109671458 A CN109671458 A CN 109671458A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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Abstract
The present invention discloses a kind of method for managing flash memory module and relevant flash controller, this method includes: sequentially establishing the more sector address mapping data of multiple sections, wherein the more sector address map the logical address and corresponding physical address that data include each section；A part of section in multiple section with continuous logic address is merged into cluster, and the data-moving of the partial sector is had to multiple data pages of continuous physical address into the flash memory module；And the cluster address mapping data of the cluster is established, and wipe the sector address corresponding to the partial sector previously established and map data.The method of management flash memory module disclosed in this invention and relevant flash controller, can be greatly reduced the capacity of address mapping table, with acceleration logic/physical address search speed, and extend the service life of flash memory module.
Description
Technical field
The present invention is about flash memory, espespecially a kind of method for managing flash memory module and relevant flash controller.
Background technique
There can be a flash translation layer (FTL) (Flash Translation Layer, FTL) in flash controller, it will be literary
Logical address in part system is converted to the physical address in flash memory module, and the block for managing and being controlled in flash memory module whereby makes
Use situation.Flash translation layer (FTL) would generally have there are two problem, and wherein first problem is how to increase logical address and physically
Inquiry/conversion speed of location, to accelerate data access；And Second Problem is the block erasing time how reduced in flash memory module
Number, to extend the service life of flash memory module.Specifically, since the capacity of current flash memory module is increasing, therefore it is used to record to patrol
The capacity of section (sector) address mapping table of volume address and physical address relationship is also increasing, thus will lead to logic/
The search speed of physical address is slack-off；On the other hand, since sector address mapping table can be stored in flash memory module, area is added
Content in sector address mapping table can need continually to update because of the variation of data stored in flash memory module,
The capacity of sector address mapping table but will cause the block erasing times in flash memory module to be significantly increased in the case of becoming larger, and influence
To the service life of flash memory module.
Summary of the invention
In view of this, the present invention provides a kind of method for managing flash memory module and relevant flash controller.
In one embodiment of the invention, a kind of method for managing a flash memory module is disclosed comprising: sequentially establish
As many as multiple sections sector address maps data, and wherein the more sector address mapping data include patrolling for each section
Collect address and corresponding physical address；A part of section in multiple section with continuous logic address is merged into one
Cluster, and by the data-moving of the partial sector into the flash memory module with continuous physical address multiple data pages；And it builds
The cluster address mapping data of the cluster is found, and wipes the sector address corresponding to the partial sector previously established and maps data.
In another embodiment of the present invention, a kind of flash controller is disclosed, wherein the flash controller is used to deposit
A flash memory module is taken, and the flash controller includes memory and microprocessor, wherein the memory is used to store program
Code, and the microprocessor is used to execute the program code to control the access to the flash memory module.In the flash controller
In operation, which sequentially establishes the more sector address mapping data of multiple sections, and wherein the more sector address reflect
Penetrate the logical address and corresponding physical address that data include each section；And the microprocessor will be in multiple section
A part of section with continuous logic address merges into cluster, and by the data-moving of the partial sector into the flash memory module
Multiple data pages with continuous physical address, and the cluster address mapping relation of the cluster is established, and wipe and previously establish it
Sector address corresponding to the partial sector maps data.
In another embodiment of the present invention, a kind of method for managing flash memory module is disclosed comprising: establish address
Mapping table, wherein the address mapping table include multiple sections logical address and corresponding physical address；And by the ground
Location mapping table is written in the same data page into the flash memory module together together with other data, and wherein other data are unrelated
In any about logical address and the mapping data of physical address.
In another embodiment of the present invention, a kind of method for managing flash memory module is disclosed comprising: read first
Stored erasing serial number in block, wherein the erasing serial number is used to indicate that this first piece in upper primary progress erasing operation is the sudden strain of a muscle
Whole which time erasing operation carried out in storing module；Judged the data in this first piece for hot number according to the erasing serial number
According to or cold data；When the data in this first piece are judged as cold data, the data in first piece of use are copied to
In second piece；And wipe data in this first piece.Then the cold data of other blocks is focused on second in the same way
Block, second piece of cold data is just not likely to move later, can reduce unnecessary move.
The method of management flash memory module provided by the present invention and relevant flash controller, can be greatly reduced address and reflect
The capacity of firing table with acceleration logic/physical address search speed, and extends the service life of flash memory module.
For having read those skilled in the art of the subsequent better embodiment as shown by each attached drawing and content
For, each purpose of the invention is apparent.
Detailed description of the invention
Fig. 1 is the architecture diagram for accessing flash memory module.
Fig. 2 is the schematic diagram according to the storage device of one embodiment of the invention.
Fig. 3 is the schematic diagram according to multiple mapping address tables of one embodiment of the invention.
Fig. 4 is using multiple mapping address tables shown in Fig. 3 according to one embodiment of the invention to read from flash memory module
The flow chart for evidence of fetching.
Fig. 5 is the schematic diagram for how generating cluster (cluster) address mapping data.
Fig. 6 is the flow chart of the method for management flash memory module shown in fig. 5.
Fig. 7 is the schematic diagram that address mapping table is written to flash memory module according to one embodiment of the invention.
Fig. 8 is the flow chart according to the method for the management flash memory module of another embodiment of the present invention.
Specific embodiment
Fig. 1 is the architecture diagram for accessing a flash memory module 120, depicts file system 112 and passes through flash translation layer (FTL) (FTL)
114 read data from flash memory module 120 to write data into flash memory module 120, or by flash translation layer (FTL) 114.?
In general flash memory device, not due to the file system 112 of flash memory module 120 and master device (for example, computer or processor)
It is identical, it is therefore desirable to be converted to flash memory mould using flash translation layer (FTL) 114 come the logical address in the file system 112 by master device
Physical address used in block 120, successfully to carry out accessing operation to flash memory module 120.In addition, in addition to carrying out logically
Except conversion between location and physical address, the block that flash translation layer (FTL) 114 separately can be managed and be controlled with this in flash memory module 120 makes
Use situation.
Fig. 2 is the schematic diagram according to the storage device 100 of one embodiment of the invention.Storage device 100 is controlled including flash memory
Device 110 and flash memory module 120, wherein flash controller 110 includes interface circuit 211, microprocessor 212, read-only memory
213, buffer storage 215 and control logic 216.Read-only memory 213 is used to store program code 214, and microprocessor
212 are used to execute program code 214 to control the access to flash memory module 120, that is, flash translation layer (FTL) 114 shown in FIG. 1 can
It is realized with executing program code 214 by microprocessor 212.In addition, flash controller 110 is connected by interface circuit 322
To master device (for example, computer or processor), and the master device can access flash memory module 120 by flash controller 110.
Flash memory module 120 includes multiple flash chips, each flash chip includes multiple pieces (block), and each
Block includes multiple data pages (page) again.In the specification of flash memory module 120, flash controller 110 carries out flash memory module 120
Erasing operation is to carry out in blocks, i.e., block is a smallest erasure unit；In addition, flash controller 110 is to flash memory
Module 120, which carries out write operation, to be carried out as unit of data page, i.e., data page is one the smallest write-in unit.
It in the present embodiment, is in order by more data when master device needs to write data into flash memory module 120
It is sequentially sent in flash controller 110, wherein each data have fixed size.In currently used file system
In, each data correspond to section (sector), and its size is 4KB.Each section data (that is, above-mentioned is every
One data) be written to flash memory module 120 during, microprocessor 212 with can also establishing a section of the section simultaneously
Location maps data, and wherein this sector address maps the logical address and corresponding physical address that data include the section.It should
Sector address mapping data can be first temporarily stored in buffer storage 215, and subsequent suitable time point is waited to store again
Into flash memory module 120.As noted previously, as the data of each section can need to establish in write-in to flash memory module 120
One sector address maps data, therefore, when the capacity of flash memory module 120 is increasing (such as 8GB, 16GB or more), area
The data volume that sector address maps data also can be quite huge, thus causes the burden of buffer storage 215 and waste flash memory
Space in module 120.In addition, in the case of the data volume of sector address mapping data is excessive, it is also possible to can reduce and patrol
Collect inquiry/conversion speed of address and physical address.
Therefore, in order to which the data volume for solving the problems, such as above-mentioned sector address mapping data is excessive, the present embodiment proposes one
The method that kind can reduce sector address mapping data, by will have multiple sections of continuous logic address to merge into one
Cluster (cluster), and be single cluster address mapping data by multiple sector address of script mapping data reduction, to reduce ground
The quantity of location mapping data.
Specifically, with reference to Fig. 3, for according to the schematic diagram of multiple mapping address tables of one embodiment of the invention.In Fig. 3
Embodiment in, three layers of mapping address table of major design, wherein first layer is FTL configuration, with having recorded multiple clusters
The address of location mapping table group CMT_G0, CMT_G1, CMT_G2 ... etc. in flash memory module 120；The second layer is each cluster
Multiple projects included by address mapping table group, Fig. 3 are by taking cluster address mapping table group CMT_G0 as an example comprising Duo Gexiang
Mesh C1~C3, and each project is corresponded to multiple sections；And third layer is then sector address mapping table comprising Duo Biqu
Sector address maps data S1~S15.In the present embodiment, project C1, which corresponds to 128, has continuous logic address and continuous object
The section of address is managed, so 128 sections are integrated into a cluster, and project C1 only includes a cluster address mapping data, and
The cluster address mapping data can be first logical address of above-mentioned 128 sections and the information of first physical address；
And due to the lazy weight of the section with continuous logic address and continuous physical address in project C3, therefore its corresponding section is simultaneously
It is not integrated into a cluster, therefore project C3 includes the information for being linked to sector address mapping table.
Multiple mapping address table handlings shown in Fig. 3, referring to FIG. 4, it is the use according to one embodiment of the invention
Multiple mapping address tables shown in Fig. 3 are with the flow chart of the reading data from flash memory module 120.In step 400, process is opened
Begin.In step 402, microprocessor 212 receives reading order from master device, to require to read the data of particular section.In step
In rapid 404, microprocessor 212 is looked for corresponding cluster address from FTL configuration according to the logical address of the particular section and is reflected
Firing table group, in the present embodiment, the particular section correspond to cluster address mapping table group CMT_G0.In a step 406, micro- place
Reason device 212 judges that required information is located in cluster address mapping table group CMT_G0 according to the logical address of the particular section
That project, in the present embodiment, if the logical address of the particular section corresponds to project C1, then process enters step
408；And if the logical address of the particular section corresponds to project C3, then process enters step 412.In a step 408, due to
Project C1 only has recorded a cluster address mapping data, and therefore, microprocessor 212 just directly obtains this cluster address of cache number
According to, and in step 410 the physical address according to recorded in this cluster address mapping data with from flash memory module 120 sequentially
The content of 128 sections is read, and thus the content of 128 sections obtains the data of the particular section (particular section is this
One of 128 sections).On the other hand, in step 412, a sector address is linked to since project C3 includes one
The information of mapping table, therefore microprocessor 212 is linked to the sector address mapping table；Then in step 414, microprocessor 212
Sector address mapping data, such as S2 are obtained according to the logical address of the particular section, and in step 416 according to the area
Sector address maps physical address recorded in data sequentially to read the content of the particular section from flash memory module 120.
In the above embodiment, 128 areas are indicated due to only having recorded a cluster address mapping data in project C1
The physical address of section, therefore the data volume of mapping address table can be greatly decreased.Further, since the data volume of mapping address table subtracts
It is few, thus by the use process of mapping address table shown in the 3rd~4 figure can also rapidly look for it is required physically
Location, to promote access speed and efficiency.
Fig. 5 depicts the schematic diagram for how generating cluster address mapping data.As shown in figure 5, firstly, microprocessor 212 connects
Receipts carry out multiple write instructions of autonomous devices to require to have the data of 128 sections of continuous logic address LA0~LA127
D_S0~D_S127 is written into flash memory module 120, at this point, microprocessor 212 in order by the data D_S0 of 128 sections~
D_S127 is written in block 510, and establishes sector address mapping table simultaneously to record logical address LA0~LA127 and its correspondence
Physical address PA0~PA127.It is noted that the address in the block 510 that data D_S0~D_S127 is written to is not necessarily
It is continuously, i.e., physical address PA0~PA127 is not necessarily continuous physical address.Then, when institute in sector address mapping table
When the number of sections of record reach predetermined quantity (the present embodiment is 128 sections), microprocessor 212 just prepares this
128 sections with continuous logic address merge into a cluster, and data D_S0~D_S127 is moved from block 510 to block
In multiple data pages in 520 with continuous physical address.As noted previously, as data D_S0~D_S127 meeting after moving
With continuous logical address and continuous physical address, therefore, microprocessor 212 can establish accordingly data D_S0~
The cluster address mapping data of D_S127, wherein the cluster address mapping data only includes in the LA0~LA127 of continuous logic address
First physical address PA0 ' of continuous physical address in one logical address LA0 and above-mentioned piece 520.
After establishing cluster address mapping data, the sector address mapping table of script is just no longer required, therefore can be with
Directly delete to save storage space.In addition, the cluster address mapping data that Fig. 5 is established can be arranged at cluster shown in Fig. 3
In address mapping table group, such as the project C1 of CMT_G0.
It is noted that the above-mentioned sections by 128 with continuous logic address merge into a cluster and by data D_
The process that S0~D_S127 moved or copied to block 520 from block 510 is not to carry out immediately, but can be in flash controller
110 it is available free when flash controller 110 need to carry out merged block or junk data and collect (garbage
Collection row processing again when).
In the present embodiment, block 510 can be the storage of the single-layer type with very fast access speed (Single-Level
Cell, SLC) block, and block 520 can be and store (Triple-Level Cell, TLC) with the three-layer type compared with high storage density
Block, wherein single-layer type block storage indicates that one of floating gate transistor is only used to store a position, and three-layer type block storage table
Show that one of floating gate transistor can be used to store three positions.
Fig. 6 is the flow chart of the method for management flash memory module 120 shown in fig. 5.With reference to the 5th, 6 figures and above disclosed
Content, process are as described below.
Step 600: process starts.
Step 602: sequentially more data of multiple sections being written in first piece of flash memory module, and sequentially establishing should
More sector address of multiple sections map data.
Step 604: a part of section in multiple section with continuous logic address being merged into cluster, and by the portion
The data-moving of sectional is into second piece of the flash memory module with multiple data pages of continuous physical address.
Step 606: establishing the cluster address mapping data of the cluster, and wipe the partial sector that corresponds to previously established
Sector address maps data.
On the other hand, in the prior art, if insufficient space in buffer storage 215 and need not needing at present
When address mapping table (sector address mapping table as escribed above) the occupied space release used, microprocessor 212 can be incited somebody to action
Address mapping table is stored into flash memory module 120, and this address mapping table is removed from buffer storage 215.However, address
Region stored by mapping table is typically different than general sector data, that is, sector address mapping table is needed solely according to one
Writing commands are written to flash memory module 120, thus increase system burden.In order to solve this problem, in addition the present embodiment mentions
A kind of method that address mapping table can be written to the same data page together together with sector data is gone out, to promote system effect
Energy.
With reference to Fig. 7, for according to the signal that address mapping table is written to flash memory module 120 of one embodiment of the invention
Figure, wherein this address mapping table can be cluster address mapping table shown in Fig. 3 group and/or sector address mapping table.Such as Fig. 7 institute
Show, block 710 is located in flash memory module 120, and including multiple data pages (only drawing data page 712 as representative), and in this reality
Applying data page 712 in example includes data field (data area) and spare area (spare area), and wherein the size of data field is
16KB, and can be used to store 4 sector datas (every sector data is 4KB)；And spare area is then for storing metadata
(meta data).In the present embodiment, when the address mapping table in buffer storage 215 needs to be stored to flash memory module 120
When, microprocessor 212 will use the same writing commands, and address mapping table is written to together together with other sector datas
In data page 712, to save read-write number.By the way that address mapping table is written to the same data page 712 together with sector data
In, it can reduce again and store more data in the case of number is written, and due to sector data and corresponding address mapping table
There is higher probability that can be stored in the same data page, therefore the number for reading address mapping table can be saved.
On the other hand, movement of the data between block is very inefficent thing, in order to reduce the mobile number of data,
It is dsc data or cold data that flash controller 110, which can go data stored in decision block, then determines that junk data is searched accordingly
Processing mode when collection, wherein dsc data above-mentioned refers to the data of write time soon, i.e., the regular data used；And
Cold data refers to the data of the time being stored in block for a long time, i.e., for a long time without use/update data.Due to cold number
It, will be by data therein according to being considered as rarely needed data, therefore when block stored in flash memory decision block is cold data
(valid data) are concentrated to another piece, and the block of script just releases for subsequent use.And block locating for cold data needs
The probability being cleared out will very little, mobile number can be reduced.The block in flash memory module 120 is also mentioned in above-mentioned disclosure
Including single-layer type block and three-layer type block, in general, single-layer type block has faster access speed and allows more erasing
Number.The method of above-mentioned cold and hot data can be applied and determine how the data of single-layer type block are moved to three-layer type block, to reach
To the optimal use efficiency of single-layer type block, or determine the movement between three-layer type block and three-layer type block, to avoid three-layer type block it
Between meaningless move.
However, flash controller 110 needs whether many information carry out data stored in decision block in the prior art
It for cold data, therefore may require that additional space stores relevant information, and will also result in its running burden, therefore, in the present invention
In one embodiment, flash controller 110 can be directly according to itself stored erasing serial number (erase in each block
Sequence number) judge that the data in the block are dsc data or cold data, to avoid need it is additional collect storage its
His information.Specifically, when having one piece to need to be wiped free of in flash memory module 120, flash controller 110 will be updated flash memory
The total degree (that is, number adds 1) of block erasing operation conducted in module 120, and data write-in is carried out in the subsequent block
When together using this update total degree be written among the block as the erasing serial number.In other words, which uses
To indicate the block in which time erasing operation that upper primary progress erasing operation is that entirety is carried out in flash memory module 120.Later,
When the subsequent space for needing to discharge the block or idle flash controller 110, flash controller 110 can be from the block
Serial number is wiped in middle reading, and according to conducted in the flash memory module 120 that the erasing serial number and flash controller 110 are recorded at present
Block erasing operation total degree between gap judge that the data in the block are dsc data or cold data.As described above,
Due to the present embodiment during judging cold heat data it is only necessary to use to be stored in information in block originally, therefore can be with
It avoids the problem that needing to store additional information and cause system burden in the prior art.
Block conducted in the flash memory module 120 that above-mentioned piece of erasing serial number and flash controller 110 is recorded at present is wiped
Except the gap between the total degree of operation can be used to indicate the cold-hot condition of data, the bigger data that represent of gap can more be regarded
To be cold data, and gap is smaller, represents Data writing time soon therefore can be considered to be dsc data.As an example it is assumed that
The total degree of block erasing operation conducted in the flash memory module 120 that flash controller 110 is recorded at present is 20000 times, the
Erasing serial number 17000 recorded in one piece, second piece of erasing serial number 19500 recorded, then data in first piece
It can be considered to be cold data, and the data in second piece can then be considered to be dsc data.
In the present embodiment, the erasing serial number and flash controller 110 that flash controller 110 can first calculate block are at present
Gap between the total degree of block erasing operation conducted in the flash memory module 120 recorded, and carried out according to this gap
Some mathematical operations or judge (for example, whether the gap is greater than a critical value) come determine the data in the block be dsc data or
Cold data.
Fig. 8 is the flow chart according to the method for the management flash memory module 120 of another embodiment of the present invention.With reference to Fig. 8 and with
On about the disclosure for judging cold data and dsc data, process is as described below.
Step 800: process starts.
Step 802: reading erasing serial number stored in block.
Step 804: judging that the data in the block are dsc data or cold data according to the erasing serial number.
Step 806: when the data in the block are judged as cold data, the data in the block being copied in another piece.
Step 808: wiping the data in the block.
The brief summary present invention provides firstly a kind of address of cache in the method for management flash memory module of the invention
Section with continuous logic address can be merged into a cluster by the design and management method of table, and accordingly by multiple areas
Sector address maps the cluster address mapping data that data reduction is single pen, to be greatly reduced the capacity of address mapping table, such one
Come, can be with acceleration logic/physical address search speed, and extend the service life of flash memory module.In one embodiment, address of cache
Table is to be written together with other sector datas to the same data page, to reduce write-in number.In addition, in addition the present invention proposes
A kind of can be the method for cold data or dsc data come the data in decision block according to itself stored erasing serial number in block,
To avoid data-moving meaningless between block the problem of needing to store additional information in the prior art and cause system burden.
The foregoing is merely better embodiment of the invention, all equivalent changes done according to the claims in the present invention and repair
Decorations, should all belong to the scope of the present invention.
Claims (20)
1. a kind of method for managing flash memory module characterized by comprising
The more sector address mapping data of multiple sections are sequentially established, wherein the more sector address mapping data include each
The logical address of a section and corresponding physical address；
A part of section in multiple section with continuous logic address is merged into cluster, and by the data of the partial sector
Multiple data pages with continuous physical address are moved into the flash memory module；And
The cluster address mapping data of the cluster is established, and wipes the sector address corresponding to the partial sector previously established and maps
Data.
2. the method as described in claim 1, which is characterized in that the cluster address mapping data is being somebody's turn to do with continuous logic address
First logical address of partial sector, and first physical address of multiple data page with continuous physical address.
3. the method as described in claim 1, which is characterized in that will have the part of continuous logic address in multiple section
Section merges into the step of cluster and includes:
When the quantity of the partial sector with continuous logic address reaches predetermined quantity, just start to have in multiple section
There is the partial sector of continuous logic address to merge into the cluster.
4. the method as described in claim 1, which is characterized in that separately include:
The data of multiple section are sequentially stored at least one first piece of the flash memory module, and sequentially establish multiple area
The more sector address mapping data that section is somebody's turn to do；And
When the partial sector with continuous logic address merges into the cluster, and by the data of the partial sector from this first piece
Multiple data page with continuous physical address is moved into second piece of the flash memory module.
5. method as claimed in claim 4, which is characterized in that this at least one first piece includes single-layer type block storage, and this
Two pieces are three-layer type block storage.
6. the method as described in claim 1, which is characterized in that further include:
Address mapping table is established according to the more sector address mapping data and the cluster address mapping data；And
The address mapping table is written in the same data page into the flash memory module together together with other sector datas.
7. method as claimed in claim 6, which is characterized in that the data page is the minimum writing unit in the flash memory module,
And the write operation of the address mapping table and this other sector datas is carried out according to the same writing commands.
8. a kind of flash controller, which is characterized in that the flash controller is used to access a flash memory module and flash memory control
Device includes:
Memory, for storing program code；
Microprocessor, for executing the program code to control the access to the flash memory module；
Wherein the microprocessor sequentially establishes the more sector address mapping data of multiple sections, and wherein the more sector address reflect
Penetrate the logical address and corresponding physical address that data include each section；And the microprocessor will be in multiple section
A part of section with continuous logic address merges into cluster, and by the data-moving of the partial sector into the flash memory module
Multiple data pages with continuous physical address, and establish the cluster address mapping relation of the cluster, and wipe and previously to have been established
Sector address corresponding to the partial sector maps data.
9. flash controller as claimed in claim 8, which is characterized in that the cluster address mapping data is with continuous logic
First logical address of the partial sector of location, and first physics of multiple data page with continuous physical address
Address.
10. flash controller as claimed in claim 8, which is characterized in that will have continuous logic address in multiple section
Partial sector the step of merging into the cluster include:
When the quantity of the partial sector with continuous logic address reaches predetermined quantity, just start to have in multiple section
There is the partial sector of continuous logic address to merge into the cluster.
11. flash controller as claimed in claim 8, which is characterized in that further include:
The data of multiple section are sequentially stored at least one first piece of the flash memory module, and sequentially establish multiple area
The more sector address mapping data that section is somebody's turn to do；And
When the partial sector with continuous logic address merges into the cluster, and by the data of the partial sector from this first piece
Multiple data page with continuous physical address is moved into second piece of the flash memory module.
12. flash controller as claimed in claim 11, which is characterized in that this at least one first piece includes that single-layer type stores
Block, and this second piece is three-layer type block storage.
13. flash controller as claimed in claim 8, which is characterized in that further include:
Address mapping table is established according to the more sector address mapping data and the cluster address mapping data；And
The address mapping table is written in the same data page into the flash memory module together together with other sector datas.
14. flash controller as claimed in claim 13, which is characterized in that the data page is the most small letter in the flash memory module
Enter unit, and the write operation of the address mapping table and this other sector datas is carried out according to the same writing commands.
15. a kind of method for managing flash memory module characterized by comprising
Establish address mapping table, wherein the address mapping table include multiple sections logical address and it is corresponding physically
Location；And
The address mapping table is written in the same data page into the flash memory module together together with other data, wherein this its
His data are independent of any about logical address and the mapping data of physical address.
16. method as claimed in claim 15, which is characterized in that the data page is that the minimum write-in in the flash memory module is single
Member, and the write operation of the address mapping table and this other sector datas is carried out according to the same writing commands.
17. method as claimed in claim 15, which is characterized in that executed by flash controller.
18. a kind of method for managing flash memory module characterized by comprising
Erasing serial number stored in block is read, wherein the erasing serial number is used to indicate that the block is in upper primary progress erasing operation
Whole which time erasing operation carried out in the flash memory module；
Judge that the data in the block are dsc data or cold data according to the erasing serial number；
When the data in the block are judged as cold data, the data in the block are copied in another piece；And
Wipe the data in the block.
19. method as claimed in claim 18, which is characterized in that judge the data in the block according to the erasing serial number for heat
The step of data or cold data, includes:
The block is judged according to the gap between the total degree of block erasing operation conducted in the erasing serial number and flash memory module
In data be dsc data or cold data.
20. method as claimed in claim 18, which is characterized in that the block is single-layer type block or three-layer type block, and this another piece
For three-layer type block.
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| CN201710967426.8A CN109671458A (en) | 2017-10-17 | 2017-10-17 | The method of management flash memory module and relevant flash controller |
| TW107101829A TW201917581A (en) | 2017-10-17 | 2018-01-18 | Method for managing flash memory module and associated flash memory controller |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110968524A (en) * | 2019-12-09 | 2020-04-07 | Oppo广东移动通信有限公司 | Data storage control method, device, storage medium and electronic device |
| CN111061649A (en) * | 2019-10-28 | 2020-04-24 | 宁波三星智能电气有限公司 | Self-adaptive allocation method for storage space of memory |
| CN113126915A (en) * | 2021-03-26 | 2021-07-16 | 山东英信计算机技术有限公司 | SSD table updating method, system and device based on Trim instruction |
| CN113377279A (en) * | 2020-03-09 | 2021-09-10 | 慧荣科技股份有限公司 | Data storage device and data processing method |
| CN113535074A (en) * | 2020-04-15 | 2021-10-22 | 慧荣科技股份有限公司 | Method and apparatus for block management for non-volatile memory |
| CN118426707A (en) * | 2024-07-04 | 2024-08-02 | 合肥康芯威存储技术有限公司 | Storage device and data processing method thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113885779B (en) | 2020-07-02 | 2024-03-12 | 慧荣科技股份有限公司 | Data processing method and corresponding data storage device |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008089643A1 (en) * | 2007-01-17 | 2008-07-31 | Memoright Memoritech(Shenzhen) Co., Ltd. | Method for managing flash memory block |
| CN102332290A (en) * | 2010-05-24 | 2012-01-25 | 慧荣科技股份有限公司 | Apparatuses for managing and accessing flash memory module |
| CN102650931A (en) * | 2012-04-01 | 2012-08-29 | 华为技术有限公司 | Method and system for writing data |
| CN102819496A (en) * | 2012-08-16 | 2012-12-12 | 无锡紫芯集成电路系统有限公司 | Address translation method of flash FTL (Flash Translation Layer) |
| US20130326121A1 (en) * | 2012-05-30 | 2013-12-05 | Silicon Motion, Inc. | Data-storage device and flash memory control method |
| CN103455437A (en) * | 2012-05-30 | 2013-12-18 | 慧荣科技股份有限公司 | Data storage device and data storage device operation method |
| CN104102585A (en) * | 2013-04-03 | 2014-10-15 | 群联电子股份有限公司 | Mapping information recording method, memory controller and memory storage device |
| CN107066393A (en) * | 2017-01-12 | 2017-08-18 | 安徽大学 | The method for improving map information density in address mapping table |
-
2017
- 2017-10-17 CN CN201710967426.8A patent/CN109671458A/en not_active Withdrawn
-
2018
- 2018-01-18 TW TW107101829A patent/TW201917581A/en unknown
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008089643A1 (en) * | 2007-01-17 | 2008-07-31 | Memoright Memoritech(Shenzhen) Co., Ltd. | Method for managing flash memory block |
| CN102332290A (en) * | 2010-05-24 | 2012-01-25 | 慧荣科技股份有限公司 | Apparatuses for managing and accessing flash memory module |
| CN102650931A (en) * | 2012-04-01 | 2012-08-29 | 华为技术有限公司 | Method and system for writing data |
| US20130326121A1 (en) * | 2012-05-30 | 2013-12-05 | Silicon Motion, Inc. | Data-storage device and flash memory control method |
| CN103455437A (en) * | 2012-05-30 | 2013-12-18 | 慧荣科技股份有限公司 | Data storage device and data storage device operation method |
| CN102819496A (en) * | 2012-08-16 | 2012-12-12 | 无锡紫芯集成电路系统有限公司 | Address translation method of flash FTL (Flash Translation Layer) |
| CN104102585A (en) * | 2013-04-03 | 2014-10-15 | 群联电子股份有限公司 | Mapping information recording method, memory controller and memory storage device |
| CN107066393A (en) * | 2017-01-12 | 2017-08-18 | 安徽大学 | The method for improving map information density in address mapping table |
Non-Patent Citations (2)
| Title |
|---|
| 申兆岩: "基于超级块的实时闪存转换层的设计与研究", 《CNKI硕士论文全文数据库》 * |
| 谢徐超: "固态盘闪存转换层优化技术研究", 《CNKI硕士论文全文数据库》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111061649A (en) * | 2019-10-28 | 2020-04-24 | 宁波三星智能电气有限公司 | Self-adaptive allocation method for storage space of memory |
| CN111061649B (en) * | 2019-10-28 | 2023-09-29 | 宁波三星智能电气有限公司 | Storage space self-adaptive allocation method of memory |
| CN110968524A (en) * | 2019-12-09 | 2020-04-07 | Oppo广东移动通信有限公司 | Data storage control method, device, storage medium and electronic device |
| CN110968524B (en) * | 2019-12-09 | 2022-04-12 | Oppo广东移动通信有限公司 | Data storage control method, device, storage medium and electronic device |
| CN113377279A (en) * | 2020-03-09 | 2021-09-10 | 慧荣科技股份有限公司 | Data storage device and data processing method |
| CN113377279B (en) * | 2020-03-09 | 2024-11-01 | 慧荣科技股份有限公司 | Data storage device and data processing method |
| CN113535074A (en) * | 2020-04-15 | 2021-10-22 | 慧荣科技股份有限公司 | Method and apparatus for block management for non-volatile memory |
| CN113535074B (en) * | 2020-04-15 | 2024-09-10 | 慧荣科技股份有限公司 | Method and apparatus for block management for non-volatile memory |
| CN113126915A (en) * | 2021-03-26 | 2021-07-16 | 山东英信计算机技术有限公司 | SSD table updating method, system and device based on Trim instruction |
| CN118426707A (en) * | 2024-07-04 | 2024-08-02 | 合肥康芯威存储技术有限公司 | Storage device and data processing method thereof |
| CN118426707B (en) * | 2024-07-04 | 2024-11-05 | 合肥康芯威存储技术有限公司 | Storage device and data processing method thereof |
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