CN117479036A

CN117479036A - Quantization circuit, image sensor, and signal quantization method

Info

Publication number: CN117479036A
Application number: CN202311570090.3A
Authority: CN
Inventors: 陈鹏; 衡佳伟
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2023-11-22
Filing date: 2023-11-22
Publication date: 2024-01-30

Abstract

The invention provides a quantization circuit, an image sensor and a signal quantization method, comprising the following steps: m comparators; m is an integer greater than or equal to 1; each comparator comprises a comparison module, an amplifying module and a clamping module; the comparison module is used for comparing the magnitude of the input signal with the magnitude of the reference signal and obtaining a comparison result, and then outputting a first output voltage based on the comparison result; the amplifying module obtains a second output voltage which is amplified and reversely output based on the first output voltage; the first end of the clamping module is connected with the first voltage source, the second end of the clamping module is connected with the output end of the amplifying module, and the clamping module is used for adjusting the second output voltage to a preset potential when the second output voltage does not meet the preset potential. According to the invention, the clamping module is arranged, so that the voltage can be boosted when the level value of the low level of the comparator is low, and the problems of inaccurate output, too low turnover speed and the like of the slope ADC caused by the level turnover of the comparator are avoided.

Description

Quantization circuit, image sensor, and signal quantization method

Technical Field

The present invention relates to the field of image sensing, and in particular, to a quantization circuit, an image sensor, and a signal quantization method.

Background

For an image sensor, incident photons are photoelectrically converted into Analog electrical signals at each pixel point in a pixel array, and the Analog signals are converted into digital signals by an Analog-to-digital converter (ADC) converter and output. The analog signals generated by the pixel array are converted into digital signals through the ADC and output. In view of the dual constraints of power consumption and area, an ADC for acquiring column pixels generally adopts a monoclinic structure, i.e. a ramp ADC.

The comparator in the ADC plays an important role in analog-to-digital conversion, but the comparator in the traditional ADC can turn over according to the comparison result, and in the process of turning over the low level to the high level, the level value of the low level of the comparator is lower, so that the change range of the whole complete turning over process from low to high is overlarge, the power supply voltage is influenced, and the voltage states of other adjacent comparators are influenced, so that the final ADC output is inaccurate. In addition, the transistor requires a longer recovery time due to the excessive voltage range variation during the inversion process, affecting the speed of inversion.

Based on this, how to solve the problem that the ADC output is inaccurate and the inverting speed is too slow due to the level inversion of the comparator becomes a urgent need to be solved.

It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a quantization circuit, an image sensor and a signal quantization method, which are used for solving the problems of inaccurate output and too slow flip speed of a ramp ADC caused by level flip of a comparator in the prior art.

To achieve the above and other related objects, the present invention provides a quantization circuit comprising: m comparators; m is an integer greater than or equal to 1; each comparator comprises a comparison module, an amplifying module and a clamping module;

the first input end of the comparison module receives an input signal, the second input end of the comparison module receives a reference signal, and the comparison module is used for comparing the magnitude of the input signal with the magnitude of the reference signal and obtaining a comparison result, and then outputting a first output voltage based on the comparison result;

the amplifying module is connected with the output end of the comparing module and is used for obtaining a second output voltage which is amplified and reversely output based on the first output voltage;

The first end of the clamping module is connected with a first voltage source, and the second end of the clamping module is connected with the output end of the amplifying module and used for adjusting the second output voltage to the preset potential when the second output voltage does not meet the preset potential.

Optionally, the comparison module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch, a second switch, and a tail current source; the tail current source is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube and is used for generating tail current; the grid electrode of the first NMOS tube is used as a first input end of the comparison module, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with a second voltage source, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is used as the output end of the comparison module; the source electrode of the second PMOS tube is connected with the second voltage source, and the grid electrode of the second PMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the second NMOS tube is used as a second input end of the comparison module, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube; the two ends of the first switch are respectively connected with the grid electrode and the drain electrode of the first NMOS tube, the control end receives a first zeroing signal, and the self-bias zeroing is carried out on the first NMOS tube based on the first zeroing signal; and two ends of the second switch are respectively connected with the grid electrode and the drain electrode of the second NMOS tube, the control end receives a second zeroing signal, and the second NMOS tube is subjected to self-bias zeroing based on the second zeroing signal.

Optionally, the amplifying module includes a third PMOS transistor, a fifth NMOS transistor, a third switch, and a capacitor; the source electrode of the third PMOS tube is connected with a third voltage source, the grid electrode of the third PMOS tube is connected with the output end of the comparison module, and the drain electrode of the third PMOS tube is used as the output end of the amplification module; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode is connected with a fourth voltage source through the capacitor, and the source electrode is connected with the fourth voltage source; and two ends of the third switch are respectively connected with the grid electrode and the drain electrode of the fifth NMOS tube, and the control end receives a first control signal.

Optionally, the tail current source includes a third NMOS tube and a fourth NMOS tube; the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube is connected with a first bias voltage, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube; and the grid electrode of the fourth NMOS tube is connected with the second bias voltage, and the source electrode of the fourth NMOS tube is connected with the fifth voltage source.

Optionally, the clamping module includes a sixth NMOS transistor; and the drain electrode of the sixth NMOS tube is connected with the first voltage source, the grid electrode of the sixth NMOS tube is connected with the clamping voltage, the source electrode of the sixth NMOS tube is connected with the output end of the amplifying module, and the sixth NMOS tube is conducted based on the clamping voltage so as to regulate the second output voltage.

Optionally, the clamping module further includes a seventh NMOS transistor disposed between the output end of the amplifying module and the sixth NMOS transistor; the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode receives a second control signal, the source electrode is connected with the output end of the amplifying module, and the clamping module is started or stopped based on the second control signal.

Optionally, the quantization circuit further comprises a pulse generation logic module; the pulse generation logic module is connected with the output end of the clamping module and receives a counting enabling signal so as to reverse and output the second output voltage when the counting enabling signal is valid, and then a third output voltage is obtained.

Optionally, the pulse generating logic module includes an eighth NMOS transistor, a ninth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a nand gate, and an inverter; the source electrode of the eighth NMOS tube is connected with a sixth voltage source, the grid electrode of the eighth NMOS tube is connected with the counting enabling signal, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the ninth NMOS tube; the grid electrode of the ninth NMOS tube receives the second output voltage, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the fourth PMOS tube; the source electrode of the fourth PMOS tube is connected with a seventh voltage source, and the grid electrode of the fourth PMOS tube receives the second output voltage; the source electrode of the fifth PMOS tube is connected with the seventh voltage source, the grid electrode of the fifth PMOS tube is connected with the counting enabling signal, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube; the first input end of the NAND gate is connected with the counting enabling signal, and the second input end of the NAND gate is connected with the drain electrode of the fourth PMOS tube; and the input end of the inverter is connected with the output end of the NAND gate, and the output end outputs the third output voltage.

Optionally, the quantization circuit further comprises a voltage generator; the voltage generator is connected with the clamping module in the comparator and is used for generating clamping voltage to adjust the adjusting range of the second output voltage by the corresponding clamping module.

Optionally, the voltage generator includes a reference voltage generation module and a boost module; the reference voltage generation module is used for generating a first voltage corresponding to the clamping module; the boost module receives the first voltage, and is configured to boost the first voltage to a second voltage and output the second voltage to the clamp module, so as to adjust the second output voltage based on the second voltage.

Optionally, when the comparison module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch, a second switch, and a tail current source; the tail current source comprises a third NMOS tube and a fourth NMOS tube; the amplifying module comprises a third PMOS tube, a fifth NMOS tube, a third switch and a capacitor; when the clamping module comprises a sixth NMOS tube and a seventh NMOS tube:

the reference voltage generation module comprises a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a fifteenth NMOS tube; the source electrode of the tenth NMOS tube is connected with a fifth voltage source, the grid electrode of the tenth NMOS tube is connected with a third bias voltage, and the drain electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube; the grid electrode of the eleventh NMOS tube is connected with a fourth bias voltage, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the twelfth NMOS tube; the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the grid electrode is connected with the drain electrode; the source electrode of the sixth PMOS tube is connected with a second voltage source, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the grid electrode of the eighth PMOS tube; the source electrode of the seventh PMOS tube is connected with a second voltage source, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the thirteenth NMOS tube, and the grid electrode of the seventh PMOS tube is connected with the drain electrode; the source electrode of the thirteenth NMOS tube is connected with the source electrode of the twelfth NMOS tube, and the grid electrode is connected with the drain electrode; the source electrode of the eighth PMOS tube is connected with a third voltage source, and the drain electrode of the eighth PMOS tube outputs the first voltage; the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the eighth PMOS tube, the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the fifteenth NMOS tube, and the grid electrode of the fourteenth NMOS tube is connected with the drain electrode; the source electrode of the fifteenth NMOS tube is connected with a fourth voltage source, and the grid electrode of the fifteenth NMOS tube is connected with a first voltage source;

Wherein, the tenth NMOS tube and the fourth NMOS tube have the same parameters; the eleventh NMOS tube and the third NMOS tube have the same parameters; the twelfth NMOS transistor has the same parameters as the first NMOS transistor; the thirteenth NMOS tube and the second NMOS tube have the same parameters; the fifteenth NMOS transistor and the seventh NMOS transistor have the same parameters; the fourteenth NMOS transistor and the sixth NMOS transistor have the same parameters; the sixth PMOS tube has the same parameters as the first PMOS tube; the seventh PMOS tube and the second PMOS tube have the same parameters; the eighth PMOS tube and the third PMOS tube have the same parameters; the first bias voltage is the same as the fourth bias voltage; the second bias voltage is the same as the third bias voltage.

Optionally, the boost module includes a PMOS current mirror structure, a resistive component, and an NMOS current mirror structure; the first end of the NMOS current mirror structure is connected with an eighth voltage source, the second end receives the first voltage, the third end receives a fifth bias voltage, and the NMOS current mirror structure is conducted based on the fifth bias voltage so as to offset the internal current of the PMOS current mirror structure; the first end of the resistor component is connected with the second end of the NMOS current mirror structure, and the second end of the resistor component is connected with the first end of the PMOS current mirror structure; wherein a second end of the resistor assembly is used as an output end of the boosting module to output the second voltage; the second end of the PMOS current mirror structure is connected with a ninth voltage source, the third end receives a sixth bias voltage, and the PMOS current mirror structure is conducted based on the sixth bias voltage so as to boost the voltage of the resistor; the currents at two ends of the resistor component are equal.

Optionally, the boost module includes a series-structured resistor assembly, and the voltage is increased by passing a current of a fixed magnitude through the series-structured resistor assembly.

Optionally, the PMOS current mirror structure includes at least P ninth PMOS transistors and P tenth PMOS transistors; p is an integer greater than or equal to 1; each ninth PMOS tube is arranged in one-to-one correspondence with each tenth PMOS tube; the source electrode of each ninth PMOS tube is connected with the ninth voltage source, the grid electrode is connected with the sixth bias voltage, and the drain electrode is connected with the source electrode of the corresponding tenth PMOS tube; the grid electrode of each tenth PMOS tube is respectively connected with a corresponding first current control signal, and the drain electrode is connected with the second end of the resistor component; and conducting the corresponding tenth PMOS tube through each first current control signal, and loading the pull-up current with the corresponding magnitude for the resistor assembly.

Optionally, the NMOS current mirror structure includes at least Q fourteenth NMOS transistors and Q seventeenth NMOS transistors; q is an integer greater than or equal to 1; each fourteenth NMOS tube is arranged in one-to-one correspondence with each seventeenth NMOS tube; the source electrode of each fourteenth NMOS tube is connected with an eighth voltage source, the grid electrode is connected with the fifth bias voltage, and the drain electrode is connected with the source electrode of the corresponding seventeenth NMOS tube; the grid electrode of each seventeenth NMOS tube is respectively connected with a corresponding second current control signal, and the drain electrode of each seventeenth NMOS tube is connected with the first end of the resistance component; and the corresponding seventeenth NMOS tube is conducted through each second current control signal, so that the resistance component is loaded with pull-down current with corresponding magnitude to offset the internal current of the PMOS current mirror structure.

To achieve the above and other related objects, the present invention provides an image sensor, including the implementation of the quantization circuit described above: the image sensor comprises a pixel array which is arranged in an array, wherein each comparator corresponds to at least one column of pixel columns, and when the voltage generator exists in the quantization circuit, the voltage generator corresponds to a row formed by the comparators.

To achieve the above and other related objects, the present invention provides a signal quantization method, implemented based on the quantization circuit, comprising:

providing an input signal and a reference signal to obtain a comparison result, and outputting a first output voltage based on the comparison result; obtaining a second output voltage which is amplified and reversely output based on the first output voltage; adjusting the output signal to a preset potential when the second output voltage does not meet the preset potential; the pulse width of the level at which the reference voltage starts to cross the input signal is taken as a signal quantization result.

Optionally, the reference signal is set as a ramp signal; the input signal is set as a reset signal or an image signal, respectively; and performing difference calculation based on the quantization result of the reset signal and the quantization result of the image signal to realize correlated double sampling.

As described above, the quantization circuit, the image sensor, and the signal quantization method of the present invention have the following advantageous effects:

according to the quantization circuit, the image sensor and the signal quantization method, the clamping module is arranged, so that the voltage can be boosted when the low-level value of the comparator is low, and the problems of inaccurate output of a slope ADC, too low turnover speed and the like caused by the level turnover of the comparator are avoided. Meanwhile, the quantization circuit, the image sensor and the signal quantization method are further provided with the voltage generator on the basis of the clamping module, so that the stability of output voltage can be ensured, and the interference caused by the introduction of the clamping module is avoided. In addition, the invention can solve a series of problems caused by the level inversion of the comparator by only adding at least one MOS tube in each row of the comparator, has less increased area, is beneficial to the integration of the image sensor and can be conveniently popularized and applied on a large scale.

Drawings

Fig. 1 shows a schematic diagram of a comparator.

Fig. 2 shows a quantization timing diagram of the comparator of fig. 1.

Fig. 3 is a schematic diagram of a quantization circuit according to the present invention.

Fig. 4 is a schematic diagram of a comparator according to the present invention.

Fig. 5 shows a quantization timing diagram of the comparator of fig. 4.

Fig. 6 is a schematic diagram of a comparator with pulse generation logic according to the present invention.

Fig. 7 is a schematic diagram showing the structure of the pulse generating logic module.

FIG. 8 is a timing diagram of the comparator of FIG. 6

Fig. 9 is a schematic diagram showing the structure of the voltage generator of the present invention.

Fig. 10 is a schematic diagram showing a structure of a resistor assembly in the voltage generator according to the present invention.

Description of element reference numerals

1. Comparator with a comparator circuit

2. Quantization circuit

21. Comparator with a comparator circuit

211. Comparison module

2111. Tail current source

212. Amplifying module

213. Clamping module

214. Pulse generation logic module

2141. NAND gate

2142. Inverter with a high-speed circuit

22. Voltage generator

221. Reference voltage generation module

222. Boost module

2221 PMOS current mirror structure

2222 NMOS current mirror structure

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1-10. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Comparative example

As shown in fig. 1, the present comparative example provides a comparator 1 including: the MOS transistor comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a first switch S1, a second switch S2, a third switch S3 and a capacitor C.

Specifically, the source electrode of the first MOS transistor M1 is grounded to the ground GND, the gate electrode is connected to the first voltage V1, and the drain electrode is connected to the source electrode of the second MOS transistor M2; the grid electrode of the second MOS tube M2 is connected with a second voltage V2, and the drain electrode of the second MOS tube M3 is connected with the source electrode; the grid electrode of the third MOS tube M3 receives a first input signal VINP, and the drain electrode is connected to the grid electrode through a first switch S1; the grid electrode of the fourth MOS tube M4 receives a second input signal VINN, and the drain electrode is connected to the grid electrode through a second switch S2; the source electrode of the fifth MOS tube M5 is connected with the working voltage VDD, the drain electrode of the fifth MOS tube M3 is connected with the drain electrode, and the grid electrode of the fifth MOS tube M5 is connected with the drain electrode; the source electrode of the sixth MOS tube M6 is connected with the working voltage VDD, the grid electrode of the sixth MOS tube M5 is connected with the grid electrode of the fifth MOS tube M4, and the drain electrode of the sixth MOS tube M6 is connected with the drain electrode of the fourth MOS tube M4 and outputs a first voltage signal stg1_out; the source electrode of the seventh MOS tube M7 is connected with the working voltage VDD, the grid electrode of the seventh MOS tube M6 is connected with the drain electrode of the sixth MOS tube M6, and the drain electrode is used as the output end of the comparator 1 to output a second voltage signal stg2_out; the source electrode of the eighth MOS transistor M8 is grounded, the gate electrode is connected to the drain electrode via the third switch S3, and the gate electrode is also connected to the source electrode via the capacitor C.

The working mechanism of this comparative example is: after the first switch S1 and the second switch S2 are both closed, the current of the branch where the seventh MOS transistor M7 is located depends on the gate-source voltage (Vgs) of the seventh MOS transistor M7, when the third switch S3 is closed, the seventh MOS transistor M7 starts to charge the capacitor C, so that the current of the branch where the seventh MOS transistor M7 is located is converted into the current controlled by the gate voltage of the eighth MOS transistor M8 and outputs a voltage signal, and when the third switch S3 is opened, the capacitor C maintains the voltage of the circuit, so that the current of the branch where the seventh MOS transistor M7 is located is determined by the gate-source voltage (Vgs) of the eighth MOS transistor M8.

The comparator 1 of the present comparative example was used for signal quantization based on the above mechanism, and the level state of each signal during quantization was analyzed as shown in fig. 2. The first switch S1 and the second switch S2 are turned on and then turned off, the second input signal VINN is set as a reset signal or an image signal, and the first input signal VINP is set as a ramp signal.

As shown in fig. 2, as the voltage of the ramp signal rises, the voltage of the first input signal VINP is greater than the voltage of the second input signal VINN. Because the tail current formed by the first MOS tube M1 and the second MOS tube M2 is unchanged, the current of the branch where the third MOS tube M3 is located is increased, and the current of the branch where the fourth MOS tube M4 is located is reduced. Since the sixth MOS transistor M6 is pushed into the linear region when the saturation region is not satisfied, the drain-source voltage (Vds) of the sixth MOS transistor decreases, and the first voltage signal stg1_out rises. The gate-source voltage (Vgs) of the seventh MOS transistor M7 becomes smaller, the current of the branch where the seventh MOS transistor M7 is located decreases, and the eighth MOS transistor M8 needs to be pressed into the linear region to decrease the current, so that the finally output second voltage signal stg2_out starts to decrease to the low level.

When the ramp signal falls (at time t 1), the voltage of the first input signal VINP falls until it crosses the second input signal VINN (at time t 2), the voltage of the second input signal VINN is greater than the voltage of the second input signal VINP, and finally the second voltage signal stg2_out is turned from low level to high level, so as to complete the quantization of the second input signal (the reset signal in the present comparative example).

Based on the above steps, the image signal (time t3 to time t 4) is quantized again.

In the quantization step shown in fig. 2, since the low level of the second voltage signal stg2_out is close to 0V, the variation range of the second voltage signal stg2_out is larger and is directly close to the operating voltage VDD during the inversion phase of the second voltage signal stg2_out. This can lead to a number of problems: (1) The power line where the working voltage VDD is located and the current on the power line where the working voltage VDD is located as the ground GND have large variations, resulting in a large voltage drop range; since in practical use, the power line is not connected to only one comparator, other adjacent comparators may be affected, resulting in inaccurate quantization process of other comparators. (2) A wide variation of the second voltage signal stg2_out may be coupled to other devices or other nodes, resulting in a variation of the performance of the comparator, affecting the accuracy of the comparator. (3) The second voltage signal stg2_out is too low in voltage at a low level, so that the MOS transistor needs a longer recovery time when turning over, and the turning over speed is affected.

Example 1

As shown in fig. 3 and 4, the present embodiment provides a quantization circuit 2 including: m comparators 21; m is an integer greater than or equal to 1. Each comparator 21 includes a comparing module 211, an amplifying module 212, and a clamping module 213.

As shown in fig. 4, the first input terminal of the comparison module 211 receives an input signal VINN, the second input terminal receives a reference signal VINP, and the comparison module is configured to compare the magnitudes of the input signal VINN and the reference signal VINP and obtain a comparison result, so as to output a first output voltage VOUT1 based on the comparison result.

Specifically, the comparison module 211 includes a first PMOS MP1, a second PMOS MP2, a first NMOS MN1, a second NMOS MN2, a first switch S1, a second switch S2, and a tail current source 2111; the tail current source 2111 is connected to the source of the first NMOS MN1 and the source of the second NMOS MN2, and is configured to generate a tail current; the gate of the first NMOS transistor MN1 is used as a first input end (receiving the input signal VINN) of the comparison module 211, and the drain is connected to the drain of the first PMOS transistor MP 1; the source electrode of the first PMOS MP1 is connected to a second voltage source (in this embodiment, the first supply voltage AVDD), the gate electrode is connected to the gate electrode of the second PMOS MP2, and the drain electrode is used as the output end (output first output voltage VOUT 1) of the comparison module 211; the source electrode of the second PMOS MP2 is connected to the second voltage source (in this embodiment, the first supply voltage AVDD), and the gate electrode is connected to the drain electrode; the gate of the second NMOS transistor MN2 is used as the second input end (receiving the reference signal VINP) of the comparison module 211, and the drain is connected to the drain of the second PMOS transistor MP 2; two ends of the first switch S1 are respectively connected with a grid electrode and a drain electrode of the first NMOS tube MN1, a control end receives a first zeroing signal, and self-bias zeroing is carried out on the first NMOS tube MN1 based on the first zeroing signal; two ends of the second switch S2 are respectively connected to the gate and the drain of the second NMOS MN2, and the control end receives a second zeroing signal, and performs self-bias zeroing on the second NMOS MN2 based on the second zeroing signal.

As an example, the tail current source 2111 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4; the drain electrode of the third NMOS MN3 is connected to the source electrodes of the first NMOS MN1 and the second NMOS MN2, the gate electrode is connected to the first bias voltage VB1, the source electrode is connected to the drain electrode of the fourth NMOS MN4, the gate electrode of the fourth NMOS MN4 is connected to the second bias voltage VB2, and the source electrode is connected to a fifth voltage source (in this embodiment, ground GND), and the tail current is controlled to be generated based on the first bias voltage VB1 and the second bias voltage VB 2.

In this embodiment, when the first switch S1 is closed so that the gate and the drain of the first NMOS MN1 are connected, and the second switch S2 is closed so that the gate and the drain of the second NMOS MN2 are connected, a self-bias circuit is respectively formed, self-bias zero calibration is implemented, and the input offset voltage of the comparator 21 is eliminated, so that the input and output common mode levels of the comparison module 211 are determined.

It should be noted that, by adjusting the first bias voltage VB1 and the second bias voltage VB2, the magnitude of the tail current may be adjusted, so as to regulate the driving capability of the comparison module 211. In addition, the specific arrangement of the tail current source 2111 is not limited to the embodiment, and any arrangement capable of providing tail current to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 is the protection scope of the embodiment.

As shown in fig. 4, the amplifying module 212 is connected to the output end of the comparing module 211, and amplifies the first output voltage VOUT1 in an inverting manner and outputs the second output voltage VOUT2.

Specifically, the amplifying module 212 includes a third PMOS MP3, a fifth NMOS MN5, a third switch S3, and a capacitor C; the source electrode of the third PMOS MP3 is connected to a third voltage source (in this embodiment, the first supply voltage AVDD), the gate electrode is connected to the output end of the comparing module 211, and the drain electrode is used as the output end of the amplifying module 212; the drain electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the third PMOS tube MP3, the grid electrode is connected with a fourth voltage source (in the embodiment, the ground GND) through the capacitor C, and the source electrode is connected with the fourth voltage source; two ends of the third switch S3 are respectively connected to the gate and the drain of the fifth NMOS MN5, and the control end is connected to the first control signal Vc1. The third switch S3 is controlled to be turned on or off based on the first control signal Vc1, so as to ensure the switching of the second output voltage VOUT2 in different states.

In the embodiment, when the first NMOS transistor MN1 and the second NMOS transistor MN2 in the comparison module 211 are both set in the self-bias state, the current of the branch where the MP3 of the third PMOS transistor is located is determined by the gate voltage of the MP3 of the third PMOS transistor. When the third switch S3 is closed, the current of the branch where the MP3 of the third PMOS tube is located determines the gate voltage of the fifth NMOS tube MN 5; when the third switch S3 is turned off, the current of the branch where the MP3 of the third PMOS transistor is located is determined by the voltage maintained by the gate of the fifth NMOS transistor MN5, and the on or off of the third switch S3 will realize the state switching of the second output voltage VOUT2.

As shown in fig. 4, the first end of the clamping module 213 is connected to a first voltage source (in this embodiment, the first supply voltage AVDD), and the second end of the clamping module 213 is connected to the output end of the amplifying module 212, for adjusting the second output voltage VOUT2 to the preset potential when the second output voltage VOUT2 does not satisfy the preset potential, in this embodiment, for boosting the second output voltage VOUT2 to the preset potential when the second output voltage VOUT2 is lower than the preset potential.

Specifically, the clamping module 213 includes a sixth NMOS transistor MN6; the drain electrode of the sixth NMOS MN6 is connected to the first voltage source, the gate electrode is connected to the clamp voltage Vclamp, the source electrode is connected to the output end of the amplifying module 212, and the sixth NMOS is turned on based on the clamp voltage Vclamp to regulate the second output voltage VOUT 2. In this embodiment, the sixth NMOS MN6 is turned on to boost the second output voltage VOUT 2.

When the voltage of the second output voltage VOUT2 is lower than a certain voltage value, vgs of the sixth NMOS transistor MN6 is greater than Vth, the sixth NMOS transistor MN6 is turned on, the current held by MN5 of the fifth NMOS transistor flows through the sixth NMOS transistor MN6 of the clamp transistor, and the first voltage source (the first supply voltage AVDD) can charge the node of the second output voltage VOUT2, so that the second output voltage VOUT2 cannot continuously drop. In one embodiment, the voltage value to which the second output voltage VOUT2 is regulated may be adjusted by adjusting the voltage at the gate terminal of the sixth NMOS transistor MN 6. In one implementation, the voltage at the gate terminal of the sixth NMOS transistor MN6 may be generated by a fixed voltage source.

As an example, the clamping module 213 further includes a seventh NMOS transistor MN7 disposed between the output end of the amplifying module 212 and the sixth NMOS transistor MN 6; the drain electrode of the seventh NMOS MN7 is connected to the source electrode of the sixth NMOS MN6, the gate electrode is connected to the second control signal Vc2, the source electrode is connected to the output end of the amplifying module 212, and the clamping module 213 is turned on or off based on the second control signal Vc 2. Under the condition that the second control signal Vc2 is valid, the clamping module 213 is turned on, so as to detect the voltage state of the second output voltage VOUT2 and boost the voltage state. In addition, setting the second control signal Vc2 can also adjust the voltage of the clamping module 213, and regulate the boost time.

According to the clamping method provided by the embodiment, two MOS transistors (the sixth NMOS transistor MN6 and the seventh NMOS transistor MN 7) can be added in each comparator, and if clamping enabling logic is not added, only one MOS transistor (the sixth NMOS transistor MN 6) can be added, so that the area added when the clamping function is realized is small, and the overall performance of the device is improved.

In this embodiment, when the voltage of the second output voltage VOUT2 is lower than a certain value, the sixth NMOS transistor MN6 is turned on as a clamp, and limits the second output voltage VOUT2 to a certain voltage value. As shown in fig. 4 and fig. 5, when the first switch S1, the second switch S2, and the third switch S3 are all turned off, the current of the branch where the MP3 of the third PMOS transistor is located is maintained by the fifth NMOS transistor MN 5. After the reference signal is set to the ramp signal and the ramp signal begins to ramp up, the second output voltage VOUT2 should be flipped to a low level. When the second output voltage VOUT2 is lower than the preset voltage value, since the sixth NMOS transistor MN6 is turned on, the branch current held by the MN5 of the fifth NMOS transistor flows through the sixth NMOS transistor MN6, so that the first voltage source (in this embodiment, the first supply voltage AVDD) connected to the sixth NMOS transistor MN6 charges the node where the second output voltage VOUT2 is located, thereby ensuring that the voltage to the second output voltage VOUT2 does not continuously drop, and ensuring that the potential to the second output voltage VOUT2 is not lower than a certain preset voltage value. Since the gate voltage of the sixth NMOS transistor MN6 determines the voltage value at which the second output voltage VOUT2 is clamped, the second output voltage VOUT2 can be regulated by setting the clamping voltage Vclamp of the gate connection of the sixth NMOS transistor MN 6.

It should be noted that, the second output voltage VOUT2 may be clamped by another voltage node, and the clamped voltage value may be adjusted by adjusting the gate voltage of the seventh NMOS transistor MN 7. Because the second output voltage VOUT2 is clamped, the variation range of the second output voltage VOUT2 is ensured to be relatively reduced, and a series of problems caused by the supply voltage when the second output voltage VOUT2 is directly turned to a low voltage after the second output voltage VOUT2 is turned over are avoided.

In one embodiment, as shown in fig. 6, the quantization circuit further includes a pulse generation logic module 214, where the pulse generation logic module 214 is connected to the output end of the clamping module 213, and receives a count enable signal cmp_en, so as to invert and output the second output voltage when the count enable signal cmp_en is valid, thereby obtaining a third output voltage cmp_out. Wherein, alternatively, the timing of the pulse generation logic 214 may be as shown in fig. 8.

In a specific example, referring to fig. 7 and 8, the pulse generation logic module 214 includes: the device comprises an eighth NMOS tube MN8, a ninth NMOS tube MN9, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a NAND gate 2141 and an inverter 2142; a source electrode of the eighth NMOS MN8 is connected to a sixth voltage source (in this embodiment, DGND is referred to), a gate electrode is connected to the count enable signal (active high), and a drain electrode is connected to the source electrode of the ninth NMOS MN 9; the grid electrode of the ninth NMOS tube MN9 receives the second output voltage VOUT2, and the drain electrode of the ninth NMOS tube MN9 is connected with the drain electrode of the fourth PMOS tube PM 4; the source of the fourth PMOS PM4 is connected to a seventh voltage source (in this embodiment, the second power supply voltage DVDD), and the gate receives the second output voltage VOUT2; the source electrode of the fifth PMOS tube MP5 is connected with the seventh voltage source, the grid electrode is connected with the counting enabling signal cmp_en, and the drain electrode is connected with the drain electrode of the fourth PMOS tube MP 4; a first input end of the nand gate 2141 is connected to the count enable signal cmp_en, and a second input end is connected to the drain of the fourth PMOS MP 4; the input end of the inverter 2142 is connected to the output end of the nand gate 2141, and the output end outputs the third output voltage cmp_out. The second output voltage VOUT2 is input to the gates of the fourth PMOS MP4 and the ninth NMOS MN9 at the same time, so as to change the voltage state input to the nand gate 2141, and then the voltage state is inverted by the inverter 2142. In practical use, the number of stages of the inverter for turning can be set based on the requirement, so as to adjust the level state and the buffering time of the output signal.

The embodiment also provides a signal quantization method, which is implemented based on the quantization circuit 2, and includes: providing an input signal VINN and a reference signal VINP to obtain a comparison result, and outputting a first output voltage VOUT1 based on the comparison result; inverting-amplifying the first output voltage VOUT1 and outputting a second output voltage VOUT2; adjusting the output signal to a preset potential when the second output voltage does not meet the preset potential, and in this embodiment, boosting the output signal to the preset potential when the second output voltage VOUT2 is lower than the preset potential; further, a pulse width of a level at which the reference voltage starts to cross the input signal may be used as a signal quantization result, for example, a pulse width at which the reference voltage starts to fall to the level of the input signal may be used as a signal quantization result.

Specifically, the reference signal VINP is set as a ramp signal; the input signal VINN is set as a reset signal or an image signal, respectively; and performing difference calculation based on the quantization result of the reset signal and the quantization result of the image signal to realize correlated double sampling. In this embodiment, the reference signal is set as a ramp signal, and the rising edge and the falling edge of the ramp signal are detected by the counter, and the counter is triggered until the ramp signal starts to fall to a level consistent with the level of the input signal, so as to read out the pulse bandwidth corresponding to the input signal VINN.

In the present embodiment, as shown in fig. 5 and 8, the reset signal is quantized first, and the input signal VINN is set as the reset signal: as the voltage of the ramp signal (reference signal VINP) rises, the voltage of the reference signal VINP is greater than the voltage of the input signal VINN. Because the tail current formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4 is unchanged, the current of the branch where the second NMOS transistor MN2 is located increases, and the current of the branch where the first NMOS transistor MN1 is located decreases. The drain-source voltage (Vds) of the third PMOS MP3 decreases, and the first output voltage VOUT1 increases. The gate-source voltage (Vgs) of the third PMOS transistor MP3 becomes smaller, the current of the branch where the third PMOS transistor MP3 is located decreases, and the fifth NMOS transistor MN5 needs to be pressed into the linear region to decrease the current, so that the finally output second output voltage VOUT2 begins to decrease to the low level. When the ramp signal falls (at time t1 '), the voltage of the reference signal VINP falls until it crosses the input signal VINN (at time t 2'), the voltage of the input signal VINN is greater than the voltage of the reference signal VINP, and the second output voltage VOUT2 of the second voltage signal is turned from low level to high level, thereby completing quantization of the input signal VINN (in this comparative example, the reset signal). The pulse width from time t1 'to time t2' is the quantization result of the reset signal.

In the present embodiment, as shown in fig. 5 and 8, the image signal is post-quantized, the input signal VINN is set as the image signal, and the ramp signal returns to the level after the occurrence of the step signal. Repeating the above steps, the pulse width from time t3 'to time t4' is the quantization result of the image signal

The quantized result after Correlated Double Sampling (CDS) can be obtained by subtracting the quantized pulse width of the reset signal from the quantized pulse width of the image signal.

Example two

In this embodiment, an adjustable voltage source is connected to a gate (gate end) of the sixth MOS transistor MN6 by providing the clamp voltage Vclamp to realize an adjustable function of the second output voltage VOUT2, and in some embodiments, the gate voltage of the sixth MOS transistor MN6 is a constant value during the operation of the comparator, and when the circuit is affected by PVT fluctuation, the voltage of the second output voltage VOUT2 may greatly fluctuate, which affects the performance of the circuit, or even affects the normal flip of the comparator.

The present embodiment provides another quantization circuit 2, which differs from the above-described embodiments mainly in that the second output voltage VOUT2 can be kept relatively constant without fluctuating with the PVT of the circuit. The main difference is that the quantization circuit 2 of the present embodiment further includes a voltage generator 22, and the voltage generator 22 supplies the clamp voltage Vclamp to the clamp block 213 in the comparator 21. Other structures may be described in the first embodiment, and will not be described herein.

Specifically, as shown in fig. 3, the quantization circuit 2 further includes a voltage generator 22; the voltage generator 22 is connected to the clamping modules 213 in the comparators 21, and in an example, the voltage generator 22 is connected to the clamping modules 213 in each comparator 21, respectively, and is configured to generate the clamping voltage Vclamp to adjust the adjustment range of the second output voltage VOUT2 by the corresponding clamping module 213, for example, to generate the clamping voltage Vclamp to adjust the boosting range of the second output voltage VOUT2 by the clamping module 213.

As an example, the voltage generator 22 includes a reference voltage generation module 221 and a boost module 222; the reference voltage generating module is configured to generate a first voltage corresponding to the clamping module, for example, the reference voltage generating module 221 is configured to generate a first voltage V1 having the same magnitude as the voltage of the clamping module 213; the boost module 222 receives the first voltage V1, and is configured to boost the first voltage V1 to a second voltage V2 and output the second voltage V2 to the clamp module 213 to adjust the second output voltage based on the second voltage; the voltage in the clamping module 213 may be cancelled, thereby avoiding that the voltage of the clamping module 213 affects the clamping voltage Vclamp.

Further, when the comparison module 211 is configured as the device and the connection structure provided in the first embodiment (including the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, the second NMOS transistor MN2, the first switch S1, the second switch S2, and the tail current source 2111, the tail current source 2111 includes the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the amplifying module 212 includes the third PMOS transistor MP3, the fifth NMOS transistor MN5, the third switch S3, and the capacitor C, and the clamping module 213 includes the sixth NMOS transistor MN6 and the seventh NMOS transistor MN 7), the reference voltage generating module 212 includes the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, and the fifteenth NMOS transistor MN15; the source electrode of the tenth NMOS MN10 is connected to a fifth voltage source (in this embodiment, ground AGND), the gate electrode is connected to the third bias voltage VB3, and the drain electrode is connected to the source electrode of the eleventh NMOS MN 11; the gate of the eleventh NMOS transistor MN11 is connected to the fourth bias voltage VB4, the drain is connected to the source of the twelfth NMOS transistor MN12, and the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are turned on or off based on the third bias voltage VB3 and the fourth bias voltage VB4 to generate a tail current; the drain electrode of the twelfth NMOS tube MN12 is connected with the drain electrode of the sixth PMOS tube MP6, and the grid electrode is connected with the drain electrode; the source electrode of the sixth PMOS tube MP6 is connected with a second voltage source, the grid electrode of the sixth PMOS tube MP7 is connected with the grid electrode of the seventh PMOS tube MP8, and the drain electrode of the sixth PMOS tube MP6 is connected with the grid electrode of the eighth PMOS tube MP 8; the source electrode of the seventh PMOS tube MP7 is connected with a second voltage source, the drain electrode is connected with the drain electrode of the thirteenth NMOS tube MN13, and the grid electrode is connected with the drain electrode; the source electrode of the thirteenth NMOS tube MN13 is connected with the source electrode of the twelfth NMOS tube MN12, and the grid electrode is connected with the drain electrode; the source electrode of the eighth PMOS tube MP8 is connected with a third voltage source, and the drain electrode outputs the first voltage V1; the drain electrode of the fourteenth NMOS tube MN14 is connected with the drain electrode of the eighth PMOS tube MP8, the source electrode is connected with the drain electrode of the fifteenth NMOS tube MN15, and the grid electrode is connected with the drain electrode; the source of the fifteenth NMOS transistor MN15 is connected to a fourth voltage source (in this embodiment, ground AGND), and the gate is connected to the first voltage source.

In this embodiment, in the above device, parameters of the tenth NMOS transistor MN10 and the fourth NMOS transistor MN4 are the same; the eleventh NMOS transistor MN11 and the third NMOS transistor MN3 have the same parameters; the twelfth NMOS transistor MN12 has the same parameters as the first NMOS transistor MN 1; the thirteenth NMOS transistor MN13 has the same parameters as the second NMOS transistor MN 2; the fourteenth NMOS transistor MN14 and the sixth NMOS transistor MN6 have the same parameters; the fifteenth NMOS transistor MN15 and the seventh NMOS transistor MN7 have the same parameters; the sixth PMOS tube MP6 has the same parameters as the first PMOS tube MP 1; the parameters of the seventh PMOS tube MP7 and the second PMOS tube MP2 are the same; the parameters of the eighth PMOS tube MP8 and the third PMOS tube MP3 are the same; the first bias voltage VB1 is the same as the fourth bias voltage VB 4; the second bias voltage VB2 is the same as the third bias voltage VB 3.

The reference voltage generation module 212 is equivalent to a first voltage V1 obtained by copying the voltages generated by the comparison module 211 and the amplification module 212 in the comparator 21. Therefore, in order to ensure that the supplied voltage remains stable, it is required that the reference voltage generating module 221 should be matched with the voltages generated by the comparing module 211 and the amplifying module 212 in the comparator 21, so that the types, materials, manufacturing processes, sizes and layout designs of the transistors disposed at the corresponding positions should be the same to ensure that the first voltage V1 is stable and varies along with the variation of the comparing module 211 and the amplifying module 212 in the comparator 21.

It should be further noted that, as shown in fig. 9, the current of the branch where the eighth PMOS transistor MP8 is located in the reference voltage generating module 221, because the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 are always in the self-bias state, the first voltage V1 is still determined by the gate voltage of the eighth PMOS transistor MP8, and is still dependent on the gate voltage of the eighth PMOS transistor MP 8. This current will flow into the fifteenth NMOS transistor MN15 creating a voltage drop. Since the gate-source voltage (Vgs) of the fourteenth NMOS transistor MN14 is the same as the gate-source voltage (Vgs) of the sixth NMOS transistor MN6, the follow-up is realized. At this time, the first voltage V1 is equal to the gate-source voltage of the fourteenth NMOS transistor MN14 plus the voltage drop of the fifteenth NMOS transistor MN15, i.e.: the first voltage V1 satisfies:

V1＝Vgs _MN14 + V _DSMN15 (1)

wherein Vgs _MN14 The gate-source voltage of the fourteenth NMOS transistor MN 14; v (V) _DSMN15 Is the voltage drop of the fifteenth NMOS transistor MN 15.

Further, the boost module 222 includes a PMOS current mirror structure 2221, a resistive component (in this example, a resistor R ₀ To illustrate), NMOS current mirror structure 2222; the voltage can be made to increase on the basis of the gate-source voltage (Vgs) of the fourteenth NMOS transistor MN 14. The first end of the NMOS current mirror structure 2222 is connected to an eighth voltage source (in this embodiment, ground is referred to), the second end receives the first voltage V1, the third end receives a fifth bias voltage VB5, and the NMOS current mirror structure 2222 is turned on based on the fifth bias voltage VB5 to offset the internal current of the PMOS current mirror structure 2221; the resistor R ₀ A first end of the NMOS current mirror structure 2222 is connected to a second end of the PMOS current mirror structure 2221; wherein the resistance R ₀ The second end of the voltage boosting module is used as an output end (outputting a clamp voltage Vclamp, which is provided to a clamp module, such as a grid electrode of an eighth PMOS tube MP 8); a second end of the PMOS current mirror structure 2221 is connected to a ninth voltage source (in this embodiment, the first supply voltage AVDD), and a third end receives a sixth bias voltage VB6, and the PMOS current mirror structure is turned on based on the sixth bias voltage to boost the voltage of the resistor; wherein, the two ends of the resistance component are electrically connectedThe flows are equal; in this embodiment, the fifth bias voltage VB5 and the sixth bias voltage VB6 are derived from the same bias current source, which is beneficial for the PMOS current mirror structure and the NMOS current mirror structure to have equal currents.

In this embodiment, the PMOS current mirror structure 2221 includes at least P ninth PMOS transistors MP9 and P tenth PMOS transistors MP10; p is an integer greater than or equal to 1; each ninth PMOS tube MP9 is arranged in one-to-one correspondence with each tenth PMOS tube MP 8; the source electrode of each ninth PMOS MP9 is connected to the ninth voltage source (in this embodiment, the first supply voltage AVDD), the gate electrode is connected to the sixth bias voltage, and the drain electrode is connected to the source electrode of the corresponding tenth PMOS MP10; the gates of the tenth PMOS transistors MP10 are respectively connected to corresponding first current control signals (in this embodiment, P is set to 4, there are 4 first current control signals including selp <0>、selp<1>、selp<2>、selp<3>) The drain electrode is connected with the resistor R ₀ Is a second end of (2); the corresponding tenth PMOS tube MP10 is conducted through each first current control signal, and then the resistor R is obtained ₀ A pull-up current of a corresponding magnitude is loaded. For example, by applying the leftmost first current control signal (i.e., selp<3>) Effectively providing a corresponding pull-up current to the resistor. The resistor R can be effectively adjusted by introducing the PMOS current mirror structure 2221 ₀ The above current, and thus the output clamp voltage Vclamp, but since the current of the PMOS current mirror structure 2221 itself affects the voltage division, the clamp voltage Vclamp is biased, and thus the corresponding NMOS current mirror structure 2222 is configured to counteract the current fluctuation effect caused by the introduction of the PMOS current mirror structure 2221.

In this embodiment, the NMOS current mirror structure 2222 includes at least Q sixteenth NMOS transistors MN16 and Q seventeenth NMOS transistors MN17; q is an integer greater than or equal to 1; each sixteenth NMOS tube MN16 is arranged in one-to-one correspondence with each seventeenth NMOS tube MN17; the source of each sixteenth NMOS transistor MN16 is connected to an eighth voltage source (in this embodiment, ground), the gate is connected to the fifth bias voltage, and the drain is connected to the source of the corresponding seventeenth NMOS transistor MN17; the gates of the seventeenth NMOS transistors MN17 are respectively connected with corresponding second current control signals (in this embodiment, Q is set to be 4, there are 4 second current control signals including seln<0>、seln<1>、seln<2>、seln<3>) The drain electrode is connected with the resistor R ₀ Is a first end of (2); the seventeenth NMOS transistor MN17 is turned on by each second current control signal to become the resistor R ₀ A corresponding amount of current is loaded to cancel the internal current of the PMOS current mirror structure 2221.

It should be noted that, in actual use, the currents of the NMOS current mirror structure and the PMOS current mirror structure are the same, and cancel each other, so as to avoid the NMOS current mirror structure from introducing excessive current to the clamp voltage Vclamp. Through the balance of the upper NMOS current mirror structure, the output clamp voltage Vclamp cannot be affected by current brought by the inside of the NMOS current mirror structure. The clamp voltage Vclamp finally output at this time satisfies:

Vclamp＝V1+I ₀ ×R ₀ (2)

wherein I is ₀ The magnitude of the current flowing through the resistor.

The output clamp voltage Vclamp is output to the comparator 21 shown in fig. 4, since the magnitude of the second output voltage VOUT2 satisfies:

VOUT2＝Vclamp-Vgs _MN6 - V _DSMN7 (3)

wherein Vgs _MN6 The gate-source voltage of the sixth NMOS transistor MN 6; v (V) _DSMN7 Is the voltage drop between the drain and source of the seventh NMOS transistor MN 7.

In this embodiment, the parameters of the sixth NMOS transistor MN6 and the fourteenth NMOS transistor MN14 are the same (the gate-source voltages are the same); the seventh NMOS transistor MN7 has the same parameters (same voltage drop) as the fifteenth NMOS transistor MN 15. Thus, the second output voltage VOUT2 satisfies the following equations (1), (2), (3):

VOUT2＝I ₀ ×R ₀ (4)

Therefore, the second output voltage VOUT2 depends on the resistor R ₀ And flow through resistor R ₀ The current of the second output voltage VOUT2 is ensured to be relatively constant, is not influenced by the gate-source voltage of the sixth NMOS tube MN6 of the clamping tube and is not fluctuated along with the PVT of the circuit, and the second output voltage VOUT2 is realized to be not fluctuated along with the gate-source voltage Vgs of the sixth NMOS tube MN6 of the clamping tubeThe clamp voltage Vclamp is ensured to follow the fluctuation of the sixth NMOS tube MN6, and the influence of the introduced sixth NMOS tube MN6 on the second output voltage VOUT2 is avoided.

It should be further noted that the resistor R set in this embodiment ₀ The flow through resistor R is regulated by PMOS current mirror structure 2221 and NMOS current mirror structure 2222 to a fixed value ₀ The current achieves the purpose of voltage division output, and finally achieves the voltage lifting of the second output voltage VOUT2. In practical use, as shown in fig. 10, the voltage boosting module 222 may set the resistor part to be a series structure, and realize voltage division and lifting by passing a current with a fixed magnitude through the resistors in series, and then output the voltage as the clamp voltage Vclamp. For example, the node where the first voltage division Vx1 is located is selected as the clamp voltage Vclamp to be output, and if the voltage is smaller, the node where the second voltage division Vx2 is located or the node where the third voltage division Vx3, the fourth voltage division Vx4, etc. are located can be adjusted to be output. In fact, the boost module 222 may be set to other situations, so long as the setting that can ensure that the clamp voltage Vclamp output by the boost module 22 can keep the second output voltage VOUT2 stable is the protection scope of the present embodiment.

In addition, in order to facilitate the wiring of the quantization circuit 2, a plurality of comparators 21 may be provided on the same side of the voltage generator 22. The position of the voltage generator 22 may be set based on actual needs. In practice, a plurality of voltage generators 22 with different output clamp voltages Vclamp may be set based on actual needs, which is not limited to the present embodiment.

Embodiment III:

the present embodiment also provides an image sensor including the quantization circuit as described in any one of the above embodiments. The image sensor can be a CMOS image sensor, the image sensor can be an image acquisition device, and can be security monitoring, vehicle-mounted electronics, a mobile phone camera, machine vision and other devices.

The image sensor includes a pixel array arranged in an array, in one implementation, each comparator corresponds to at least one column of pixels, for example, the comparators may correspond to the columns of pixels one by one, and the quantization circuit is configured to include a row of comparators, and the pixel array is quantized row by row based on the row of comparators, which may, of course, also be in other arrangements. In addition, when the quantization circuit is present, in one implementation, the voltage generators correspond to rows formed by the comparators, for example, when there is a row of comparators, one of the voltage generators corresponds to a row of comparators for realizing the row-by-row quantization of the pixel array, and further, alternatively, the voltage generators may be in one-to-one correspondence with the ramp generators.

In summary, the present invention provides a quantization circuit, an image sensor and a signal quantization method, including: m comparators; m is an integer greater than or equal to 1; each comparator comprises a comparison module, an amplifying module and a clamping module; the comparison module is used for comparing the magnitude of the input signal with the magnitude of the reference signal and obtaining a comparison result, and then outputting a first output voltage based on the comparison result; the amplifying module is connected with a second output voltage which is amplified based on the first output voltage and reversely output; the first end of the clamping module is connected with a first voltage source, the second end of the clamping module is connected with the output end of the amplifying module, and the clamping module is used for adjusting the second output voltage to the preset potential when the second output voltage does not meet the preset potential. According to the invention, by arranging the clamping module, the voltage boosting can be performed when the level value of the low level of the comparator is low, and further the problems of inaccurate output, too slow turnover speed and the like of the slope ADC caused by the level turnover of the comparator are avoided. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A quantization circuit, the quantization circuit comprising at least: m comparators; m is an integer greater than or equal to 1; each comparator comprises a comparison module, an amplifying module and a clamping module;

2. The quantization circuit of claim 1, wherein: the comparison module comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first switch, a second switch and a tail current source;

the tail current source is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube and is used for generating tail current; the grid electrode of the first NMOS tube is used as a first input end of the comparison module, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with a second voltage source, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is used as the output end of the comparison module; the source electrode of the second PMOS tube is connected with the second voltage source, and the grid electrode of the second PMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the second NMOS tube is used as a second input end of the comparison module, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube; the two ends of the first switch are respectively connected with the grid electrode and the drain electrode of the first NMOS tube, the control end receives a first zeroing signal, and the self-bias zeroing is carried out on the first NMOS tube based on the first zeroing signal; two ends of the second switch are respectively connected with the grid electrode and the drain electrode of the second NMOS tube, a control end receives a second zeroing signal, and self-bias zeroing is carried out on the second NMOS tube based on the second zeroing signal;

And/or the amplifying module comprises a third PMOS tube, a fifth NMOS tube, a third switch and a capacitor;

the source electrode of the third PMOS tube is connected with a third voltage source, the grid electrode of the third PMOS tube is connected with the output end of the comparison module, and the drain electrode of the third PMOS tube is used as the output end of the amplification module; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode is connected with a fourth voltage source through the capacitor, and the source electrode is connected with the fourth voltage source; and two ends of the third switch are respectively connected with the grid electrode and the drain electrode of the fifth NMOS tube, and the control end receives a first control signal.

3. The quantization circuit of claim 2, wherein: the tail current source comprises a third NMOS tube and a fourth NMOS tube;

the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube is connected with a first bias voltage, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube;

and the grid electrode of the fourth NMOS tube is connected with the second bias voltage, and the source electrode of the fourth NMOS tube is connected with the fifth voltage source.

4. The quantization circuit of claim 1, wherein: the clamping module comprises a sixth NMOS tube;

and the drain electrode of the sixth NMOS tube is connected with the first voltage source, the grid electrode of the sixth NMOS tube is connected with the clamping voltage, the source electrode of the sixth NMOS tube is connected with the output end of the amplifying module, and the sixth NMOS tube is conducted based on the clamping voltage so as to regulate the second output voltage.

5. The quantization circuit of claim 4, wherein: the clamping module further comprises a seventh NMOS tube arranged between the output end of the amplifying module and the sixth NMOS tube;

the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode receives a second control signal, the source electrode is connected with the output end of the amplifying module, and the clamping module is started or stopped based on the second control signal.

6. The quantization circuit of claim 1, wherein: the quantization circuit further comprises a pulse generation logic module;

the pulse generation logic module is connected with the output end of the clamping module and receives a counting enabling signal so as to reverse and output the second output voltage when the counting enabling signal is valid, and then a third output voltage is obtained.

7. The quantization circuit of claim 6, wherein: the pulse generation logic module comprises an eighth NMOS tube, a ninth NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a NAND gate and an inverter;

the source electrode of the eighth NMOS tube is connected with a sixth voltage source, the grid electrode of the eighth NMOS tube is connected with the counting enabling signal, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the ninth NMOS tube;

The grid electrode of the ninth NMOS tube receives the second output voltage, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the fourth PMOS tube;

the source electrode of the fourth PMOS tube is connected with a seventh voltage source, and the grid electrode of the fourth PMOS tube receives the second output voltage;

the source electrode of the fifth PMOS tube is connected with the seventh voltage source, the grid electrode of the fifth PMOS tube is connected with the counting enabling signal, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube;

the first input end of the NAND gate is connected with the counting enabling signal, and the second input end of the NAND gate is connected with the drain electrode of the fourth PMOS tube;

and the input end of the inverter is connected with the output end of the NAND gate, and the output end outputs the third output voltage.

8. The quantization circuit according to any one of claims 1-7, wherein: the quantization circuit further comprises a voltage generator;

the voltage generator is connected with the clamping module in the comparator and is used for generating clamping voltage to adjust the adjusting range of the second output voltage by the corresponding clamping module.

9. The quantization circuit of claim 8, wherein: the voltage generator comprises a reference voltage generation module and a boosting module;

the reference voltage generation module is used for generating a first voltage corresponding to the clamping module;

The boost module receives the first voltage, and is configured to boost the first voltage to a second voltage and output the second voltage to the clamp module, so as to adjust the second output voltage based on the second voltage.

10. The quantization circuit of claim 9, wherein: when the comparison module comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first switch, a second switch and a tail current source; the tail current source comprises a third NMOS tube and a fourth NMOS tube; the amplifying module comprises a third PMOS tube, a fifth NMOS tube, a third switch and a capacitor; when the clamping module comprises a sixth NMOS tube and a seventh NMOS tube:

the reference voltage generation module comprises a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a fifteenth NMOS tube;

the source electrode of the tenth NMOS tube is connected with a fifth voltage source, the grid electrode of the tenth NMOS tube is connected with a third bias voltage, and the drain electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube;

the grid electrode of the eleventh NMOS tube is connected with a fourth bias voltage, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the twelfth NMOS tube;

The drain electrode of the twelfth NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the grid electrode is connected with the drain electrode;

the source electrode of the sixth PMOS tube is connected with a second voltage source, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the grid electrode of the eighth PMOS tube;

the source electrode of the seventh PMOS tube is connected with a second voltage source, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the thirteenth NMOS tube, and the grid electrode of the seventh PMOS tube is connected with the drain electrode;

the source electrode of the thirteenth NMOS tube is connected with the source electrode of the twelfth NMOS tube, and the grid electrode is connected with the drain electrode;

the source electrode of the eighth PMOS tube is connected with a third voltage source, and the drain electrode of the eighth PMOS tube outputs the first voltage;

the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the eighth PMOS tube, the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the fifteenth NMOS tube, and the grid electrode of the fourteenth NMOS tube is connected with the drain electrode;

the source electrode of the fifteenth NMOS tube is connected with a fourth voltage source, and the grid electrode of the fifteenth NMOS tube is connected with a first voltage source;

wherein, the tenth NMOS tube and the fourth NMOS tube have the same parameters; the eleventh NMOS tube and the third NMOS tube have the same parameters; the twelfth NMOS transistor has the same parameters as the first NMOS transistor; the thirteenth NMOS tube and the second NMOS tube have the same parameters; the fifteenth NMOS transistor and the seventh NMOS transistor have the same parameters; the fourteenth NMOS transistor and the sixth NMOS transistor have the same parameters; the sixth PMOS tube has the same parameters as the first PMOS tube; the seventh PMOS tube and the second PMOS tube have the same parameters; the eighth PMOS tube and the third PMOS tube have the same parameters; the first bias voltage is the same as the fourth bias voltage;

The second bias voltage is the same as the third bias voltage.

11. The quantization circuit of claim 9, wherein: the boost module comprises a PMOS current mirror structure, a resistor component and an NMOS current mirror structure;

the first end of the NMOS current mirror structure is connected with an eighth voltage source, the second end receives the first voltage, the third end receives a fifth bias voltage, and the NMOS current mirror structure is conducted based on the fifth bias voltage so as to offset the internal current of the PMOS current mirror structure;

the first end of the resistor component is connected with the second end of the NMOS current mirror structure, and the second end of the resistor component is connected with the first end of the PMOS current mirror structure; wherein a second end of the resistor assembly is used as an output end of the boosting module to output the second voltage;

the second end of the PMOS current mirror structure is connected with a ninth voltage source, the third end receives a sixth bias voltage, and the PMOS current mirror structure is conducted based on the sixth bias voltage so as to boost the voltage of the resistor;

the currents at two ends of the resistor component are equal;

alternatively, the boost module includes a series resistor assembly, and the voltage is increased by passing a constant current through the series resistor assembly.

12. The quantization circuit of claim 11, wherein: the PMOS current mirror structure at least comprises P ninth PMOS tubes and P tenth PMOS tubes; p is an integer greater than or equal to 1;

each ninth PMOS tube is arranged in one-to-one correspondence with each tenth PMOS tube;

the source electrode of each ninth PMOS tube is connected with the ninth voltage source, the grid electrode is connected with the sixth bias voltage, and the drain electrode is connected with the source electrode of the corresponding tenth PMOS tube;

the grid electrode of each tenth PMOS tube is respectively connected with a corresponding first current control signal, and the drain electrode is connected with the second end of the resistor component; the corresponding tenth PMOS tube is conducted through each first current control signal, and then the resistor component is loaded with pull-up current with corresponding magnitude;

and/or, the NMOS current mirror structure at least comprises Q fourteenth NMOS transistors and Q seventeenth NMOS transistors; q is an integer greater than or equal to 1;

each fourteenth NMOS tube is arranged in one-to-one correspondence with each seventeenth NMOS tube;

the source electrode of each fourteenth NMOS tube is connected with an eighth voltage source, the grid electrode is connected with the fifth bias voltage, and the drain electrode is connected with the source electrode of the corresponding seventeenth NMOS tube;

the grid electrode of each seventeenth NMOS tube is respectively connected with a corresponding second current control signal, and the drain electrode of each seventeenth NMOS tube is connected with the first end of the resistance component; and the corresponding seventeenth NMOS tube is conducted through each second current control signal, so that the resistance component is loaded with pull-down current with corresponding magnitude to offset the internal current of the PMOS current mirror structure.

13. An image sensor, characterized in that: the quantization circuit of any one of claims 1-12, the image sensor comprising an array of pixels arranged in an array, wherein each of the comparators corresponds to at least one column of pixels, and the voltage generator corresponds to a row formed by the comparators when the quantization circuit is present.

14. A signal quantization method based on a quantization circuit implementation as claimed in any one of claims 1-12, characterized in that:

providing an input signal and a reference signal to obtain a comparison result, and outputting a first output voltage based on the comparison result; obtaining a second output voltage which is amplified and reversely output based on the first output voltage; adjusting the output signal to a preset potential when the second output voltage does not meet the preset potential;

the pulse width of the level at which the reference voltage starts to cross the input signal is taken as a signal quantization result.

15. The signal quantization method according to claim 14, wherein: the reference signal is set as a ramp signal; the input signal is set as a reset signal or an image signal, respectively; and performing difference calculation based on the quantization result of the reset signal and the quantization result of the image signal to realize correlated double sampling.