CN117270630A

CN117270630A - System-on-chip and timestamp capturing method, device and storage medium thereof

Info

Publication number: CN117270630A
Application number: CN202311220611.2A
Authority: CN
Inventors: 朱家骅
Original assignee: Beijing Horizon Information Technology Co Ltd
Current assignee: Beijing Horizon Information Technology Co Ltd
Priority date: 2023-09-20
Filing date: 2023-09-20
Publication date: 2023-12-22

Abstract

The method comprises the step of time synchronization of a time control circuit of the system on chip and an external clock source of the system on chip; responding to the data frame received by the bus controller of the system on chip, determining a first time value of a time control circuit at the current moment, and triggering the central processing unit of the system on chip to interrupt; determining a second time value of the time control circuit at the interrupt response time; based on the first time value and the second time value, a timestamp corresponding to the data frame is determined. Because the time value of the time control circuit is the same as the time value of the external clock source, the time stamp of the system on chip determined according to the first time value and the second time value is small in error and stable, and the safety of intelligent driving cannot be influenced.

Description

System-on-chip and timestamp capturing method, device and storage medium thereof

Technical Field

The disclosure relates to the technical field of intelligent driving, in particular to a system-on-chip and a method, a device and a storage medium for capturing a time stamp thereof.

Background

At present, when the intelligent driving system of the vehicle performs planning control on the vehicle, the vehicle CAN be reliably planned and controlled according to the CAN data frame and the time stamp of the CAN data frame by receiving the CAN data frame sent by the sensor on the vehicle and capturing the time stamp of the CAN data frame.

Generally, a method for a System-On-a-Chip (SOC) to obtain a timestamp of a received data frame includes: after the CAN driver receives the CAN data frame (message) transmitted by the CAN bus, the CPU (Central Processing Unit, CPU) is triggered to interrupt, an interrupt service routine of the CPU is executed, and the system time of the SOC is read in the interrupt service routine.

After reading the system time of the SOC, a time stamp may be stamped on the CAN data frame based on the read system time of the SOC, and finally the CAN data frame is sent to the sensing application layer. Because the perception application layer carries out planning control on the vehicle according to the CAN data frame, the accuracy of the time stamp is critical to the safety of the intelligent driving system.

However, since the SOC in the vehicle is relatively large and unstable in the work load, there is a large interrupt response delay, and thus there is a large error in the read system time, and the time stamp of the CAN data frame is also a large error, which affects the safety of the intelligent driving system.

Disclosure of Invention

In the existing scheme for capturing the time stamp in the system-on-chip, due to the existence of interrupt response delay, the captured time stamp has larger error and unstable error, and the safety of the intelligent driving system is affected.

In order to solve the technical problems, the present disclosure provides a timestamp capturing method based on a system-on-chip, so as to solve the problem of larger timestamp error of the system-on-chip capturing.

In a first aspect of the present disclosure, a method for capturing a timestamp based on a system on a chip is provided, including:

the time control circuit of the system-on-chip and an external clock source of the system-on-chip are synchronized in time;

responding to the data frame received by the bus controller of the system on chip, determining a first time value of a time control circuit at the current moment, and triggering the central processing unit of the system on chip to interrupt;

determining a second time value of the time control circuit at the interrupt response time;

based on the first time value and the second time value, a timestamp corresponding to the data frame is determined.

In a second aspect of the present disclosure, there is provided a system on a chip, comprising:

an external clock source for providing a synchronization time;

the time control circuit is used for receiving the time synchronization signal sent by the central processing unit and synchronizing with the synchronization time based on the time synchronization signal;

The bus controller is used for responding to the received data frame, triggering the interruption of the central processing unit and saving a first time value of the time control circuit at the current moment;

the central processing unit is respectively coupled with the external clock source, the time control circuit and the bus controller and is used for generating a time synchronization signal; reading a first time value stored by the bus controller and a second time value of the time control circuit at the interrupt response moment; based on the first time value and the second time value, a timestamp corresponding to the data frame is determined.

In a third aspect of the present disclosure, there is provided a timestamp capture apparatus of a system-on-chip, including:

the synchronous module is used for carrying out time synchronization on the time control circuit of the system on chip and the clock source of the system on chip;

the response module is used for responding to the data frame received by the bus controller of the system on chip, determining a first time value of the time control circuit at the current moment and triggering the central processing unit of the system on chip to interrupt;

the first determining module is used for determining a second time value of the time control circuit at the interrupt response moment;

and the second determining module is used for determining the timestamp corresponding to the data frame based on the first time value and the second time value.

In a fourth aspect of the present disclosure, a computer readable storage medium is provided, where the storage medium stores a computer program for executing the system-on-chip-based timestamp capturing method according to the first aspect.

In the embodiment of the disclosure, since the time control circuit of the SOC is time-synchronized with the external clock source of the SOC, the time value of the time control circuit is the same as the time value of the external clock source. Furthermore, the first time value of the time control circuit when the bus controller triggers the CPU interrupt is the same as the time value of the external clock source when the bus controller triggers the CPU interrupt, and the second time value of the time control circuit at the interrupt response time is the same as the time value of the external clock source at the interrupt response time. That is, there is no large error between the first time value, the second time value and the external clock source, and the first time value, the second time value and the external clock source are stable. Therefore, the time stamp of the system on chip determined according to the first time value and the second time value is small in error and stable, and the safety of intelligent driving cannot be affected.

Drawings

The foregoing and other objects, features and advantages of the present application will become more apparent from the following more particular description of embodiments of the present application, as illustrated in the accompanying drawings. The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate the application and not constitute a limitation to the application. In the drawings, like reference numerals generally refer to like parts or steps.

Fig. 1 is a schematic flow chart of an implementation of a timestamp capturing method based on a system on chip according to an exemplary embodiment of the disclosure.

Fig. 2 is a schematic flow chart of another implementation of a timestamp capturing method based on a system on chip according to an exemplary embodiment of the disclosure.

Fig. 3 is a schematic flow chart of an implementation of yet another timestamp capturing method based on a system on chip according to an exemplary embodiment of the present disclosure.

Fig. 4 is a flowchart illustrating an implementation of still another timestamp capture method based on a system on chip according to an exemplary embodiment of the present disclosure.

Fig. 5 is a schematic flow chart of an implementation of a further timestamp capturing method based on a system on chip according to an exemplary embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a composition structure of a system on a chip according to an exemplary embodiment of the present disclosure.

Fig. 7 is a schematic diagram of the composition of another system-on-chip provided in an exemplary embodiment of the present disclosure.

Fig. 8 is a schematic diagram of the composition of yet another system-on-chip provided in an exemplary embodiment of the present disclosure.

Fig. 9 is a schematic diagram of a composition structure of yet another system-on-chip provided in an exemplary embodiment of the present disclosure.

Fig. 10 is a schematic diagram of a composition structure of a timestamp capture apparatus based on a system on chip according to an exemplary embodiment of the disclosure.

Fig. 11 is a schematic diagram of the composition of another timestamp capture apparatus based on a system-on-chip according to an exemplary embodiment of the disclosure.

Fig. 12 is a schematic diagram of the composition of yet another timestamp capture apparatus based on a system-on-chip provided in an exemplary embodiment of the present disclosure.

Fig. 13 is a schematic diagram of a composition structure of yet another timestamp capture apparatus based on a system-on-chip according to an exemplary embodiment of the present disclosure.

Fig. 14 is a schematic diagram of the composition and structure of a timestamp capture apparatus based on a system-on-chip according to an exemplary embodiment of the present disclosure.

Fig. 15 is a component configuration diagram of an electronic device provided in an exemplary embodiment of the present disclosure.

Detailed Description

For the purpose of illustrating the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application and not all of the embodiments of the present application, and it should be understood that the present application is not limited by the example embodiments described herein.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. "A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

Summary of the application

CAN bus is now becoming a standard on-board bus. The auxiliary driving system and the automatic driving system CAN acquire various sensor data such as a vehicle-mounted camera, infrared, ultrasonic and millimeter wave radar through a CAN bus, process the sensor data through a vehicle-mounted artificial intelligence (Artifical Intelligence, AI) chip, generate corresponding control instructions and issue the control instructions to an actuator through the CAN bus so as to drive the vehicle to execute corresponding control actions.

The CAN driver needs to make an accurate time stamp on the CAN data frame after receiving the CAN data frame to ensure that the system CAN correctly sense and cope with the surrounding environment corresponding to the sensor data, so that the accuracy of the time stamp is critical to the safety of the automatic driving system.

Typically, the complete time stamp data of the CAN data frame is 64 bits, and the bit width of the register for recording the time stamp in the CAN controller is 32 bits, only 32 bits of time stamp data CAN be recorded, and thus the time stamp recorded by the CAN controller is incomplete. In order to obtain the complete time stamp of the CAN data frame, a CAN driver in the vehicle-mounted SOC triggers the CPU to interrupt after receiving the CAN data frame transmitted by the CAN bus, and reads the system time of the SOC or the hardware time of the SOC by executing an interrupt service routine of the CPU. The received CAN data frames are then time stamped based on the system time or hardware time. And finally, submitting the CAN data frame to a perception application layer to control the vehicle.

However, in the method for acquiring the timestamp of the CAN bus received data frame by the CPU interrupt service routine, since the workload of the vehicle-mounted SOC is relatively large and unstable, and there is a large interrupt response delay, the system time of the read SOC or the hardware time of the SOC may have a large error, and the error is also unstable, which affects the safety of the intelligent driving system.

Based on the technical problems described above, the embodiments of the present disclosure provide a timestamp capturing method based on a system on a chip, by performing time synchronization on a time control circuit of an SOC and an external clock source of the system on a chip, and when a bus controller of the SOC receives a data frame, acquiring a first time value of the time control circuit at a current time, triggering a CPU interrupt at the same time, then acquiring a second time value of the time control circuit at an interrupt response time, and finally determining a timestamp corresponding to the data frame according to the first time value and the second time value. Therefore, the time stamp corresponding to the data frame can be accurately determined, and the safety of intelligent driving is improved.

Exemplary method

Fig. 1 is a schematic flow chart of an implementation of a timestamp capturing method based on a system on chip according to an exemplary embodiment of the disclosure. The embodiment can be applied to an SOC, as shown in fig. 1, including the following steps:

Step 101, time synchronization is performed on a time control circuit of the SOC and an external clock source of the SOC.

For example, a time control circuit of the SOC may be provided between the external clock source and the bus controller for transferring the time of the external clock source to the bus controller of the SOC. The external clock source of the SOC may be an external hardware clock of the SOC. In one example, the external Hardware Clock of the SOC may include a Clock chip (RTC), a portal (precision Time protocol (Precision Time Protocol, PTP) hard Clock, PHC) Clock, a bus board (serial expansion bus board (Peripheral Component Interconnect Express, PCIE)) Clock, or a global positioning system (Global Positioning System, GPS) Clock.

In some embodiments, time synchronizing the time control circuit of the SOC with an external clock source of the SOC may include: and starting from the power-on moment of the SOC, regulating the count value of a counter in a time control circuit of the SOC in real time, so that the time difference between the time represented by the counter in the time control circuit of the SOC and the time of an external clock source of the SOC is within a preset time length error range. In one example, a counter in the time control circuit is used for counting, the count value of the counter representing a time value at a certain moment.

Illustratively, the preset duration error range may be a value greater than or equal to 0 and less than or equal to 1 μs (microseconds), which is not limited by the present disclosure.

For example, the interrupt service routine may be executed by the CPU to acquire the time of the external clock source and the time indicated by the counter, and calculate the difference between the time of the external clock source and the time indicated by the counter. And adjusting the count value of a counter in the time control circuit in real time according to the difference value, so that the time difference between the time represented by the counter and an external clock source is smaller than or equal to a preset time length error range. In some examples, the count value in the counter may be 64 bits wide.

Step 102, in response to the bus controller of the SOC receiving the data frame, determining a first time value of the time control circuit at the current time, and triggering a CPU interrupt of the SOC.

The bus controller of the SOC may be a CAN controller, for example. The embodiments of the present disclosure do not limit the types of the bus controllers, and in the following embodiments, the bus controller is taken as a CAN controller as an example for illustration.

The first time value at the current time (denoted by t1 in this disclosure) may be a partial count value of a counter in the time control circuit when the bus controller receives the data frame. The first time value may be 32 bits wide, for example, the first time value may be the lower 32 bits of the 64-bit count value of the counter.

In some embodiments, the data frame received by the CAN controller is a CAN data frame, and when the CAN controller receives the CAN data frame, the CAN controller triggers the CPU interrupt while acquiring a first time value of the time control circuit at the current time.

Illustratively, when the CAN controller receives a CAN data frame, a message mailbox (e.g., transceiver) in the CAN controller sends a trigger signal to a counter, which sends the lower 32 bits (first time value) of the counter's count value to a timestamp register in the message mailbox in response to the trigger signal, while generating a CPU interrupt. In some examples, the timestamp register may be 32 bits wide.

In some embodiments, determining the first time value of the time control circuit at the current time may include the CAN controller not only obtaining the first time value of the time control circuit at the current time, but also the CPU reading the first time value from a timestamp register of a message mailbox of the CAN controller.

Step 103, determining a second time value of the time control circuit at the interrupt response time.

Illustratively, since the bit width of the counter in the time control circuit is 64 bits, the number of bits of the second time value may also be 64 bits. The second time value is denoted by t2 in the present disclosure.

In some embodiments, the second time value of the time control circuit at the interrupt response time is determined, and the second time value may be a CPU interrupt triggered by the CAN controller by the CPU to execute an interrupt service routine. The count value of the counter in the time control circuit is read in the interrupt service routine and is taken as a second time value of the interrupt response time.

In some possible embodiments, the interrupt service routine may include:

s1, creating 3 integer variables T_hard_32_bit, T_soft_32_bit and latency of 32 bits, and 2 integer variables T_soft_64_bit and T_real_soft_64_bit of 64 bits.

The T_hard_32_bit is used for representing a 32-bit timestamp stored in a timestamp register in a message mailbox of the CAN controller when the bus controller receives a data frame; t_soft_32_bit is used to represent the lower 32 bits of the 64-bit timestamp read from the counter by the CPU at the interrupt response time; the latency is used to represent the difference between t_hard_32_bit and t_soft_32_bit, i.e., the time difference between the 32-bit timestamp t_hard_32_bit read by the CPU from the timestamp register in the message mailbox of the CAN controller and the lower 32-bit t_soft_32_bit of the 64-bit timestamp read from the counter at the interrupt response time; t_soft_64_bit is used to represent the interrupt response time, the CPU reads the 64-bit timestamp from the counter; t_real_soft_64_bit is used to represent the real time value of the bus controller receiving the data frame, i.e. the timestamp corresponding to the data frame.

S2, the CPU closes the interrupt and the scheduler.

S3, the CPU reads the 32-bit time stamp from the time stamp register in the message mailbox of the CAN controller, and assigns the read 32-bit time stamp to the T_hard_32_bit.

S4, the CPU reads the 64-bit count value from the counter of the time control circuit, and assigns the read 64-bit count value to the T_soft_64_bit.

S5, the CPU re-opens the interrupt and the scheduler.

It will be appreciated that the purpose of the CPU shutdown interrupt and scheduler in S2 is to: so that the CPU continuously performs S3 and S4 without being affected by the interrupt and scheduler to perform or schedule other tasks.

For example, when the CPU turns off the interrupt and the scheduler in S2, the CPU may read the upper 32 bits of the 64-bit count value and then read the lower 32 bits of the 64-bit count value, so as to improve the accuracy of the CPU reading the 64-bit count value. If the CPU does not shut down the interrupt and scheduler, the CPU may be affected by the interrupt and scheduler to schedule other tasks after reading the upper 32 bits of the 64-bit count value. Then, when the lower 32-bit count value of the 64-bit count value is read back after other scheduling tasks are completed, the value of the 64-bit counter is changed, so that the incorrect 64-bit count value is read out, and the accuracy of reading the 64-bit count value by the CPU is affected.

For another example, at the interrupt response time, the 64-bit count value in the counter is 19. Wherein the high 32 bits are 1 and the low 32 bits are 9. If the CPU turns off the interrupt and scheduler, the CPU reads the lower 32 bits 9 after the upper 32 bits 1 are read, and the read 64 is the count value of 19. If the CPU does not turn off the interrupt and the scheduler, after the CPU reads the upper 32 bits 1, the CPU may go to execute other scheduled tasks or interrupt tasks, so that after the scheduled tasks or interrupt tasks are executed, when the lower 32 bits of the 64-bit count value of the counter are read again, at this time, the 64-bit count value in the counter has become 20, and then the lower 32 bits of the 64-bit count value read by the CPU are 0, so that the value of the counter read by the CPU is 10, that is, the erroneous 64-bit count value is read.

Step 104, determining a timestamp corresponding to the data frame based on the first time value and the second time value.

For example, determining the timestamp corresponding to the data frame based on the first time value and the second time value may include performing a logic operation on the first time value and the second time value by executing an interrupt service routine of the CPU to obtain the timestamp corresponding to the data frame, and assigning the timestamp corresponding to the data frame to be t_real_soft_64_bit.

As shown in fig. 2, on the basis of the embodiment shown in fig. 1, step 101 may include the following steps:

in response to the external clock source sending a pulse signal to the time control circuit, a third time value of the time control circuit and a fourth time value of the external clock source sending a pulse signal to the time control circuit are determined 1011.

It will be appreciated that the external clock source may be activated by an activation command from the CPU and that the external clock source, in the activated state, may send a pulse signal to a counter in the time control circuit at a specific period. In one example, the activation command of the CPU may include cycle information of the transmission pulse signal corresponding to a specific cycle.

In the embodiment of the disclosure, a third time value of the time control circuit may be represented by t3, and a fourth time value may be represented by t 4.

Illustratively, the third time value of the time control circuit may be any value when the external clock source first transmits a pulse signal to the time control circuit after the time control circuit is powered up (corresponding to an initial time synchronization of the time control circuit with the external clock source). The third time value of the time control circuit can be determined according to the count value of the power-on initial time of the time control circuit and the duration from the power-on initial time to the time when the external clock source sends the pulse signal to the time control circuit for the first time.

In some embodiments, after the time control circuit is powered up, the external clock source may send the pulse signal to the time control circuit N (greater than or equal to 2) th time (corresponding to the time control circuit being synchronized with the duration of the external clock source), and the third time value of the time control circuit may be a time value having a predictable time error with the time value of the external clock source.

For example, at the first time, the external clock source and the time control circuit perform first time synchronization (the external clock source transmits the pulse signal for the first time), that is, the time values of the external clock source and the time control circuit are the same at the first time. However, since the crystal oscillator of the external clock source is different from the crystal oscillator of the clock control circuit, there is a frequency error between the clock frequency of the external clock source and the clock frequency of the clock control circuit, and thus, there is a predictable time error between the time of the external clock source and the time of the clock control circuit at the time next to the first time.

For example, the predictable time error may be determined based on a frequency error between a clock frequency corresponding to a crystal oscillator of the external clock source and a clock frequency corresponding to a crystal oscillator of the clock control circuit. This frequency error may result in a fixed time error between the time value of the external clock source and the time value of the clock control circuit within a unit time.

For example, the frequency error may result in a 4ms time error between the time value of the external clock source and the time value of the clock control circuit within 1s (second). When the duration from the first time to the next time is 3s, there is a 12ms error between the time of the external clock source and the time of the clock control circuit at the next time, and when the time difference from the first time to the next time is 5s, there is a 20ms error between the time of the external clock source and the time of the clock control circuit.

In the embodiment of the present disclosure, the transmission period of the pulse signal may be an initial transmission period at the initial time of power-up. The initial transmission period may be a user-defined maximum period threshold pps_period_max of the transmission pulse signal. The transmission period of the pulse signal may be any period between the maximum period threshold pps_period_max and the minimum period threshold pps_period_min defined by the user.

In some possible embodiments, the CPU sends an activation command to the external clock source, the external clock source sends a pulse signal to the counter of the time control circuit in a specific period in response to the activation command, the counter is triggered at a rising edge of the pulse signal in response to the pulse signal, automatically stores a count value at a current time (a third time value of the time control circuit) into a count value snapshot register in the time control circuit, and then the CPU reads the third time value of the time control circuit from the count value snapshot register while reading a fourth time value of the pulse signal sent from the external clock source to the time control circuit.

Step 1012, determining a compensation time based on the third time value and the fourth time value.

Illustratively, the compensation time refers to an adjustment time for adjusting a counter in the time control circuit. In some examples, the compensation time may be positive or negative.

In some embodiments, determining the compensation time based on the third time value and the fourth time value may include the CPU performing a logical operation on the third time value and the fourth time value to obtain the compensation time, and writing the compensation time to the time control unit register.

In step 1013, the time control circuit of the system-on-chip is time synchronized with an external clock source of the system-on-chip based on the compensation time.

In some embodiments, time synchronizing the time control circuitry of the system-on-chip with the external clock source of the system-on-chip based on the compensation time may include adjusting a count value of a counter in the time control circuitry based on the compensation time to time synchronize the time control circuitry with the external clock source.

Illustratively, the counter in the time control circuit may be adjusted to synchronize the time of the time control circuit with the time of the external clock source based on the compensation time, and the counter may be included to increment the count value at the current time by the compensation time to obtain the compensated count value so that the compensated count value is synchronized with the time of the external clock source.

In the embodiment of the disclosure, since the time synchronization of the time control circuit and the external clock source is realized by adjusting the count value of the counter in the time control circuit, and the adjusted time is determined according to the compensation time, the count value of the counter in the time control circuit can be more accurately compensated to be the same as the time of the external clock source under the condition that the compensation time can reflect the time difference between the time of the time control circuit and the time of the external clock source, and the time synchronization of the time control circuit and the external clock source is ensured.

In the embodiment of the disclosure, since the time synchronization of the time control circuit and the external clock source is performed according to the compensation time, the compensation time is determined according to the third time value of the time control circuit obtained when the external clock source transmits the pulse signal to the time control circuit and the fourth time value of the time control circuit transmitted by the external clock source. Therefore, the time synchronization according to the compensation time is also performed according to the third time value and the fourth time value, which is closer to the actual one.

As shown in fig. 3, step 1012 may include the following steps, based on the embodiment shown in fig. 2, described above:

step 301, determining a time difference between the third time value and the fourth time value according to the third time value and the fourth time value.

Illustratively, the time difference (t 3-t 4) (denoted by offset in this disclosure) between the third time value and the fourth time value may be positive or negative.

Step 302, determining a compensation time based on the time difference.

In a related embodiment, in order to make the times of the main control chip (e.g., electronic control unit (Electronic Control Unit, ECU) and external sensor) in the auxiliary driving system and the automatic driving system coincide, it is necessary to synchronize the PHC time of the ECU to the PHC time of the CPU by means of ptp time synchronization or the like, and then synchronize the PHC time of the CPU to the system time in the operating system by means of software.

For example, when the PHC time of the CPU is running slower than the system time and the CAN driver receives the second frame CAN data frame, if the PHC time of the slower CPU is synchronized to the system time, the CAN driver may timestamp earlier than the timestamp on the second frame CAN data frame when receiving the CAN data frame (third frame CAN data frame) after the second frame CAN data frame, and a rollback of the timestamp occurs.

In order to solve the above-mentioned problem of rollback of the timestamp, when synchronizing the PHC time of the slower CPU to the system time, the synchronization step (corresponding compensation time) of the system time is required to be smaller than or equal to the frame interval between two adjacent CAN data frames.

Based on the same idea, when the time control circuit is time-synchronized with the external clock source, the compensation time needs to be less than or equal to the minimum frame interval duration (the minimum value of the CAN frame interval, which CAN be denoted by interval in the present disclosure). For example, the offset time may be less than the interval offset, or may be 0.8×interval.

Illustratively, determining the compensation time based on the time difference value may include: determining the time difference as a compensation time in response to the time difference being less than or equal to the minimum frame interval duration; and determining a compensation time based on the minimum frame interval duration and a preset scale parameter in response to the time difference being greater than the minimum frame interval duration, the preset scale parameter being greater than 0 and less than or equal to 1.

For example, in response to the time difference being less than or equal to the minimum frame interval duration, determining the time difference as the compensation time may include writing the offset into a time control unit register when the CPU determines that the offset is less than or equal to the interval, such that the counter automatically increments the count value by the offset, enabling calibration of the counter.

In some embodiments, responsive to the time difference being greater than the minimum frame interval duration, determining the compensation time based on the minimum frame interval duration and the preset scaling parameter may include: when the CPU judges that the offset is larger than the interval, the alpha interval is written into the time control unit register, so that the counter automatically increases the count value by alpha interval, and the calibration of the counter is realized. Wherein alpha is greater than 0 and less than or equal to 1. For example, a may be 0.8.

In the embodiment of the disclosure, when the time difference is smaller than or equal to the minimum frame interval duration, the minimum frame interval duration is determined as the compensation time, and when the time difference is larger than the minimum frame interval duration, the compensation time is determined according to the minimum frame interval duration and a preset proportion parameter which is larger than 0 and smaller than or equal to 1. That is, the compensation time is less than or equal to the minimum frame interval duration, so that the problem of rollback of the timestamp can be solved, and the sense layer is prevented from confusing the sequence of the data frames, thereby preventing accidents caused by wrong decisions made by the controller of the vehicle.

In the embodiment of the disclosure, the compensation time is determined according to the difference value between the third time value and the fourth time value, and the third time value and the fourth time value are both synchronous with the external clock source, so that the time control circuit and the external clock source can be more accurately synchronous based on the compensation time.

In some embodiments of the present disclosure, although the backoff time is less than or equal to the minimum frame interval duration interval, the backoff problem of the time stamp can be solved. However, when the external clock source transmits the pulse signal at a fixed period (the count value of the counter is adjusted at a fixed period), the time difference value offset between the third time value and the fourth time value is large, and is out of a reasonable error range, the time synchronization between the time control circuit and the external clock source cannot be achieved by the compensation time being less than or equal to the minimum frame interval duration interval.

For example, for a time control circuit and an external clock source with different crystal oscillators, under the influence of temperature, a time difference of 8ms is generated between the time of the time control circuit and the time of the external clock source within 2s, and a time difference of 20ms is generated between the time of the time control circuit and the time of the external clock source within 5 s. If interval is 50ms, the single compensation time is 10ms (less than 50 ms), and the period of the external clock source transmitting the pulse signal (the compensation period of the counter) is 5s, the 5s can perform a time compensation to compensate the time difference of 10 ms. However, the time difference between the time of the time control circuit and the time of the external clock source within 5s is 20ms, and therefore, the frequency of the first time compensation of 5s cannot achieve time synchronization between the time control circuit and the external clock source.

Based on the above technical problem, as shown in fig. 4, on the basis of the embodiment shown in fig. 2, step 101 further includes the following steps:

in response to the time difference being greater than the time difference threshold and the current transmission period of the pulse signal being greater than the minimum period threshold, the transmission period of the pulse signal is updated based on the decrementing step size such that the updated transmission period of the pulse signal is less than the current transmission period, step 1014.

For example, the time difference threshold value is used to represent a reasonable range of time difference values, which may be represented by offset_thr, where offset_thr may be greater than interval. The current transmission period of the pulse signal may be represented by a variable pps_period. The decremental step may be a preset fixed step, which may be expressed in pps_period_dec. pps_period_dec may be 1s, i.e., the period in which the external clock source transmits the pulse signal is decremented by 1s each time.

In some embodiments, after the CPU writes the compensation time into the time control unit register of the counter, so that the count value of the counter is automatically increased by the compensation time, and time synchronization between the time control circuit and the external clock source is completed, it is determined whether the time difference value offset between the third time value and the fourth time value is greater than the time difference threshold value offset_thr. When the time difference value offset is determined to be greater than the time difference threshold value offset_thr, it is determined that the clock frequency difference between the external clock source and the time control circuit is greater, and the time compensation frequency for the time error needs to be increased to prevent the continuous increase of the time difference value. The compensation period for the time difference (the period of transmitting the pulse signal is reduced) is reduced to compensate for the time error, so as to prevent the time difference from being excessively large. Then, the CPU judges whether or not the period pps_period of the external clock source transmitting the pulse signal to the counter is greater than the minimum period threshold pps_period_min, and when the period pps_period of the external clock source transmitting the pulse signal is greater than the minimum period threshold pps_period_min, the transmission period of the pulse signal is reduced by a fixed step pps_period_dec, that is, the number of times of time compensation is increased in the same time, and the count value of the counter is subjected to time compensation for a greater number of times.

In some examples, increasing the time compensation frequency for the time error may include sending, by the CPU, an instruction to decrease the period of the pulse signal to an external clock source, which in response to the instruction decreases the period of the transmitted pulse signal to decrease the period of the compensation for the time difference, i.e., increase the time compensation frequency for the time error.

Illustratively, the explanation will be continued taking as an example that a time difference of 8ms is generated between the time of the time control circuit and the time of the external clock source within 2s, and a time difference of 20ms is generated between the time of the time control circuit and the time of the external clock source within 5 s. Similarly, interval is 50ms, and the single compensation time is selected to be 10ms. If the period (compensation period) of the external clock source transmitting the pulse signal is reduced from 5s to 2s, that is, the time difference compensation is performed every 2s, that is, the time difference of 10ms can be compensated in 2 s. And because the time difference generated between the time of the time control circuit and the time of the external clock source within 2s is 8ms and less than 10ms, the compensation of the time difference can be completed.

In the embodiment of the disclosure, when the time difference value is greater than the time difference threshold value offset_thr and the transmission period of the pulse signal at the current time is greater than the minimum period threshold value pps_period_min, the transmission period of the pulse signal is updated in a decremental step, so that the number of times of compensation for the count value of the counter is increased in the same time. That is, compensation for a larger time difference may be performed at the same time. In this way, time synchronization of the time control circuit and the external clock source is facilitated.

As shown in fig. 5, step 104 may include the following steps, based on the embodiment shown in fig. 1, described above:

in step 1041, a first value of a preset bit of the second time value is determined.

Illustratively, in the case where the second time value is 64-bit time data, the preset bit may be the lower 32 bits of the 64-bit time data.

In some embodiments, the first value of the preset bit of the second time value may be determined by executing an interrupt service routine of the CPU to extract the lower 32 bits of t_soft_64_bit from the t_soft_64_bit and assign the extracted lower 32 bits of t_soft_64_bit to the t_soft_32_bit.

Step 1042, determining an interrupt duration based on the difference between the first time value and the first value.

For example, the interrupt duration may also be referred to as a response delay, and may be represented by an integer variable latency. In one example, the interrupt duration refers to a duration from a time when a data frame is received by the bus controller (a time when a CPU interrupt is generated, a first time value of a counter (a low 32-bit count value) is stored in a 32-bit timestamp register) to a time when the CPU responds to the interrupt.

In some embodiments, determining the interrupt duration based on the difference between the first time value and the first value may include calculating, by the CPU, t_soft_32_bit-t_hard_32_bit and determining the value of t_soft_32_bit-t_hard_32_bit (greater than zero) as the interrupt duration.

Illustratively, the value of t_soft_32_bit may be greater than or equal to t_hard_32_bit or may be less than t_hard_32_bit. Wherein, in the case that the value of t_soft_32_bit is smaller than t_hard_32_bit, the CPU can calculate t_soft_32_bit-t_hard_32_bit in a complementary manner.

Step 1043, determining a timestamp corresponding to the data frame based on the interrupt duration and the second time value.

The second time value may be, for example, a time value obtained after the interrupt duration latency delay of the time value when the bus controller receives the data frame. In one example, the second time value is a value assigned to t_soft_64_bit.

In some embodiments, determining the timestamp corresponding to the data frame based on the interrupt duration and the second time value may include: and executing an interrupt service routine by the CPU to calculate a difference value (T_soft_64_bit-latency) between the second time value and the interrupt duration, and assigning the difference value (T_soft_64_bit-latency) to the T_real_soft_64_bit.

In the embodiment of the disclosure, since the interrupt duration is determined according to a difference value between a first value of a preset bit of a second time value and the first time value, the first time value is a time value for generating the interrupt time of the CPU, and the first value is a time value for responding to the interrupt time of the CPU. Therefore, the accuracy of the interruption time period determined from the difference between the first time value and the first value is high. Meanwhile, because the time stamp corresponding to the data frame is determined according to the interrupt duration and the second time value, the accuracy of the time stamp corresponding to the data frame is higher under the condition that the accuracy of the interrupt duration is higher.

On the basis of the above embodiments, the embodiments of the present disclosure provide a system on a chip. As shown in fig. 6, the system-on-chip 60 includes an external clock source 601, a time control circuit 602, a bus controller 603, and a central processor 604.

An external clock source 601 for providing a synchronization time.

The time control circuit 602 is configured to receive a time synchronization signal sent by the central processing unit, and synchronize with the synchronization time based on the time synchronization signal.

The time synchronization signal may be, for example, a compensation time calculated by the CPU.

The bus controller 603 is configured to trigger the central processing unit to interrupt in response to receiving the data frame, and save a first time value of the time control circuit at the current time.

A central processor 604, coupled to the external clock source 601, the time control circuit 602, and the bus controller 603, respectively, the central processor 604 being configured to generate a time synchronization signal; reading a first time value stored by the bus controller 603 and a second time value of the time control circuit 602 at the interrupt response time; based on the first time value and the second time value, a timestamp corresponding to the data frame is determined.

In some embodiments of the present disclosure, an external clock source 601 is used to send a pulse signal to the time control circuit.

The time control circuit 602, coupled between the external clock source 601 and the bus controller 603, is configured to receive and respond to the pulse signal, and store a third time value when the pulse signal is received.

The central processing unit 604 is configured to read a third time value from the time control circuit 602, read a fourth time value from the external clock source 601, send a pulse signal to the time control circuit, determine a compensation time based on the third time value and the fourth time value, and generate a time synchronization signal based on the compensation time.

As shown in fig. 7, the time control circuit 602 may include a counter 701, an internal clock source 702, a count value register 703, and a time control unit register 704 on the basis of the embodiment shown in fig. 6 described above.

The counter 701 is coupled to the external clock source 601 and the central processing unit 604, and is configured to receive and respond to the pulse signal, and store the third time value into the count value register 703.

In the disclosed embodiment, the count value snapshot register may be one implementation of the count value register 703.

An internal clock source 702 is coupled to the counter 701 for driving the counter 701.

The count value register 703 is coupled to the counter 701 and the central processing unit 604, respectively, and is configured to store a third time value.

The time control unit register 704 is coupled to the CPU 604 for storing the compensation time.

As shown in fig. 8, the bus controller 603 may include a receiver 801, and the receiver 801 may include a timestamp register 8011 coupled to a counter 701, as in the embodiment shown in fig. 7 described above.

Wherein the receiver 801 is coupled to the central processor 604 and the counter 701 for reading a first time value from the counter 701 and storing the first time value in the timestamp register 8011 in response to a received data frame.

Illustratively, the receiver 801 may be a message mailbox in the bus controller 603. A register for storing CAN data frames and a register for storing CAN timestamps (e.g., timestamp register 8011) may be included in the message mailbox.

Timestamp register 8011 is used to store a first time value.

As shown in fig. 9, the external clock source 601 may include the RTC 6011, the PHC 6012, the PCIE clock 6013, and the GPS clock 6014 on the basis of the embodiment shown in fig. 6 described above.

It can be seen that the external clock source on the SOC includes a plurality of time sources, and the user can flexibly and conveniently select the required time source according to the service requirements, so as to meet different service requirements.

As shown in fig. 10, the system-on-chip-based time stamp capturing apparatus 1000 includes: a synchronization module 1001, a response module 1002, a first determination module 1003, and a second determination module 1004.

The synchronization module 1001 is configured to perform time synchronization on a time control circuit of the system on chip and a clock source of the system on chip.

The response module 1002 is configured to determine a first time value of the time control circuit at a current time in response to the bus controller of the system-on-chip receiving the data frame, and trigger an interrupt of the central processor of the system-on-chip.

A first determining module 1003 is configured to determine a second time value of the time control circuit at the interrupt response time.

The second determining module 1004 is configured to determine a timestamp corresponding to the data frame based on the first time value and the second time value.

In some embodiments of the present disclosure, as shown in fig. 11, on the basis of the embodiment shown in fig. 10 described above, the synchronization module 1001 includes: a first determination unit 1101, a second determination unit 1102, and a synchronization unit 1103.

Wherein the first determining unit 1101 is configured to determine a third time value of the time control circuit and a fourth time value of the pulse signal sent from the external clock source to the time control circuit in response to the pulse signal sent from the external clock source to the time control circuit.

The second determining unit 1102 is configured to determine a compensation time based on the third time value and the fourth time value.

The synchronization unit 1103 is configured to time synchronize the time control circuit of the system-on-chip with an external clock source of the system-on-chip based on the compensation time.

In some embodiments of the present disclosure, as shown in fig. 12, the second determining unit 1102 may include a first sub-determining unit 1201 and a second sub-determining unit 1202 on the basis of the embodiment shown in fig. 11 described above.

Wherein the first sub-determining unit 1201 is configured to determine a time difference between the third time value and the fourth time value according to the third time value and the fourth time value.

A second sub-determination unit 1202 for determining a compensation time based on the time difference.

In some embodiments of the present disclosure, the second determining unit 1202 is configured to determine the time difference value as the compensation time in response to the time difference value being less than or equal to the minimum frame interval duration; and determining a compensation time based on the minimum frame interval duration and a preset scale parameter in response to the time difference being greater than the minimum frame interval duration, the preset scale parameter being greater than 0 and less than or equal to 1.

In some embodiments of the present disclosure, the synchronization unit 1103 is configured to adjust a count value of a counter in the time control circuit based on the compensation time, so as to synchronize the time control circuit with the time of the external clock source.

In some embodiments of the present disclosure, as shown in fig. 13, the synchronization module 1001 further includes an update unit 1104 on the basis of the embodiment shown in fig. 11 described above.

An updating unit 1104 for updating the transmission period of the pulse signal based on the decreasing step length so that the updated transmission period of the pulse signal is smaller than the current transmission period in response to the time difference value being larger than the time difference threshold and the current transmission period of the pulse signal being larger than the minimum period threshold.

In some embodiments of the present disclosure, as shown in fig. 14, the second determining module 1004 includes a third determining unit 1401, a fourth determining unit 1402, and a fifth determining unit 1403 on the basis of the embodiment shown in fig. 10 described above.

A third determining unit 1401 for determining a first value of preset bits of the second time value.

A fourth determining unit 1402 for determining an interruption time period based on a difference between the first time value and the first value.

A fifth determining unit 1403 is configured to determine a timestamp corresponding to the data frame based on the interrupt duration and the second time value.

Regarding the device for determining the positional relationship between the vehicle and the lane line during the driving in the foregoing embodiment, the specific manner in which each module performs the operation and the corresponding advantageous effects have been described in detail in the foregoing embodiment of the rear-end implementation method portion of the mid-chip system, and the corresponding manner in which the foregoing exemplary method portion performs the operation and the advantageous technical effects may be referred to, which are not described herein again.

Exemplary electronic device

Fig. 15 is a schematic diagram of the composition structure of an electronic device provided in an exemplary embodiment of the present disclosure, and as shown in fig. 15, the electronic device 150 includes one or more processors 1501 and a memory 1502.

The processor 1501 may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device 150 to perform desired functions.

Memory 1502 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random access memory (RandomAccess Memory, RAM) and/or cache memory (cache), among others. The nonvolatile Memory may include, for example, read-Only Memory (ROM), hard disk, flash Memory, and the like. One or more computer program instructions may be stored on a computer readable storage medium and the processor 1501 may execute the program instructions to implement the system-on-chip based timestamp capture method and/or other desired functions of the various embodiments of the present application above.

In one example, the electronic device 150 may further include: an input device 1503 and an output device 1504, interconnected by a bus system and/or other forms of connection mechanisms (not shown).

Of course, only some of the components of the electronic device 150 that are relevant to the present application are shown in fig. 15 for simplicity, components such as buses, input/output interfaces, and the like being omitted. In addition, the electronic device 150 may include any other suitable components depending on the particular application.

Exemplary computer program product and computer readable storage Medium

In addition to the methods and apparatus described above, embodiments of the present application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the steps in a system-on-chip-based timestamp capture method according to various embodiments of the present application described in the "exemplary methods" section of the present specification.

The computer program product may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, embodiments of the present application may also be a computer-readable storage medium, having stored thereon computer program instructions, which when executed by a processor, cause the processor to perform the steps in a system-on-chip-based timestamp capture method according to various embodiments of the present application described in the above "exemplary method" section of the present specification.

A computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-Only Memory (ROM), erasable programmable read-Only Memory (Erasable Programmable Read Only Memory, EPROM or flash Memory), optical fiber, portable compact disk read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not intended to be limited to the details disclosed herein as such.

The block diagrams of the devices, apparatuses, devices, systems referred to in this application are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

It is also noted that in the apparatus, devices and methods of the present application, the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent to the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the application to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. A system-on-chip-based timestamp capture method, comprising:

performing time synchronization on a time control circuit of the system-on-chip and an external clock source of the system-on-chip;

Responding to the bus controller of the system-on-chip receiving a data frame, determining a first time value of the time control circuit at the current moment, and triggering the central processing unit of the system-on-chip to interrupt;

determining a second time value of the time control circuit at an interrupt response time;

and determining a time stamp corresponding to the data frame based on the first time value and the second time value.

2. The method of claim 1, wherein the time synchronizing the time control circuitry of the system-on-chip with an external clock source of the system-on-chip comprises:

determining a third time value of the time control circuit and a fourth time value of the external clock source sending the pulse signal to the time control circuit in response to the external clock source sending the pulse signal to the time control circuit;

determining a compensation time based on the third time value and the fourth time value;

and based on the compensation time, time synchronizing a time control circuit of the system-on-chip with an external clock source of the system-on-chip.

3. The method of claim 2, wherein the determining a compensation time is based on the third time value and the fourth time value;

Determining a time difference value between the third time value and the fourth time value according to the third time value and the fourth time value;

the compensation time is determined based on the time difference.

4. A method according to claim 3, wherein said determining said compensation time based on said time difference value comprises:

determining the time difference as the compensation time in response to the time difference being less than or equal to a minimum frame interval duration;

and determining the compensation time based on the minimum frame interval duration and a preset proportion parameter in response to the time difference value being greater than a minimum frame interval duration, wherein the preset proportion parameter is greater than 0 and less than or equal to 1.

5. The method of any of claims 2-4, wherein the time synchronizing the time control circuitry of the system-on-chip with an external clock source of the system-on-chip based on the compensation time comprises:

based on the compensation time, a count value of a counter in the time control circuit is adjusted to synchronize the time control circuit with the time of the external clock source.

6. The method of claim 3 or 4, further comprising:

And updating the transmission period of the pulse signal based on the decreasing step length so that the updated transmission period of the pulse signal is smaller than the current transmission period in response to the time difference value being larger than the time difference threshold and the current transmission period of the pulse signal being larger than the minimum period threshold.

7. The method of any of claims 1 to 6, wherein the determining a timestamp corresponding to the data frame based on the first time value and the second time value comprises:

determining a first value of a preset bit of the second time value;

determining an interruption duration based on the first time value and a difference value of the first value;

and determining a time stamp corresponding to the data frame based on the interrupt duration and the second time value.

8. A system on a chip, comprising:

an external clock source for providing a synchronization time;

the time control circuit is used for receiving a time synchronization signal sent by the central processing unit and synchronizing with the synchronization time based on the time synchronization signal;

the bus controller is used for responding to the received data frame, triggering the interruption of the central processing unit and storing a first time value of the time control circuit at the current moment;

The central processing unit is respectively coupled with the external clock source, the time control circuit and the bus controller and is used for generating the time synchronization signal; reading the first time value stored by the bus controller and the second time value of the time control circuit at the interrupt response moment; and determining a time stamp corresponding to the data frame based on the first time value and the second time value.

9. The system-on-chip of claim 8, wherein,

the external clock source is used for sending pulse signals to the time control circuit;

the time control circuit is coupled between the external clock source and the bus controller and is used for receiving and responding to the pulse signal and storing a third time value when the pulse signal is received;

the central processing unit is configured to read the third time value from the time control circuit, read a fourth time value from the external clock source that is sent to the time control circuit, determine a compensation time based on the third time value and the fourth time value, and generate the time synchronization signal based on the compensation time.

10. The system-on-chip of claim 9, wherein the time control circuit comprises:

the counter is coupled with the external clock source and the central processing unit and is used for receiving and responding to the pulse signals and storing the third time value into a count value register;

an internal clock source coupled to the counter for driving the counter;

the count value register is coupled with the counter and the central processing unit respectively and is used for storing the third time value;

and the time control unit register is coupled with the central processing unit and used for storing the compensation time.

11. The system on a chip of claim 10, wherein the bus controller comprises: a receiver coupled to the central processor and the counter; the receiver includes a timestamp register coupled with the counter;

the receiver is configured to read the first time value from the counter and store the first time value in the timestamp register in response to the received data frame;

the timestamp register is configured to store the first time value.

12. The system on a chip of any of claims 8 to 11, wherein the external clock source comprises: clock chips, network port clocks, bus board clocks, or global positioning system clocks.

13. A system-on-chip-based timestamp capture apparatus, comprising:

the synchronization module is used for synchronizing the time control circuit of the system on chip with the clock source of the system on chip;

the response module is used for responding to the data frame received by the bus controller of the system-on-chip, determining a first time value of the time control circuit at the current moment and triggering the interruption of the central processing unit of the system-on-chip;

a first determining module, configured to determine a second time value of the time control circuit at an interrupt response time;

and the second determining module is used for determining a timestamp corresponding to the data frame based on the first time value and the second time value.

14. A computer readable storage medium storing a computer program for executing the system-on-chip-based timestamp capture method of any one of the preceding claims 1-7.