JP2007128362A - Clock synchronization of controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller capable of collectively setting clock information of a control section and display section and automatically and regularly synchronizing clocks of the control section and display section. <P>SOLUTION: The integrated controller comprises the control section 1 for controlling an apparatus including a clock having a clock transmitter built in, the display section 2 for including a clock having a clock transmitter built in, and an internal bus 3 for integrating the control section and display section. The control section has a shared memory allowing access to the display section, and has a writing means for writing in the shared memory by reading the clock information at a control section side at regular intervals, a writing means for writing the clock information into an internal memory 25 stored in the display section by reading the clock information at the control section side written into the shared memory, and a clock information updating means for writing the clock information into the clock having the clock transmitter built in the display section in which the clock information of the control section retained in the internal memory of the display section is set up as the clock information of the display section. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a programmable controller as a control device.

  Conventionally, a programmable controller (hereinafter referred to as PLC) as a control device is well known. Similarly, a programmable display in which an operation terminal and a display device are integrated is well known.

  In recent years, an integrated control device has been developed in which the PLC and the programmable display are combined as a single control device. And in manufacturing such a multifunction control apparatus, the following two methods can be considered. (1) In the first place, since PLC and programmable display already exist as separate and independent products, PLC is used as a control unit, and programmable display is used as a display unit. And is configured as an integrated control device. (2) A control device having both functions of the PLC and the programmable display is designed and manufactured from scratch.

  In the case of (1) above, it is only the housing that needs to be newly designed and manufactured, and it is not necessary to redesign the control unit and display unit from scratch. Compared to this, it is possible to manufacture with significantly reduced cost and development time. In addition, companies that manufacture such control devices have the actual situation that they have already developed and manufactured PLCs and programmable displays as a single unit, respectively, and the manufacturing method (1) is more preferred at present. ing.

  However, in the control device manufactured in this way, the control unit that functions as a PLC and the display unit that functions as a programmable display are configured as highly independent modules. For this reason, it is desirable that both the control unit and the display unit have an abnormality detection function, and when an abnormality occurs, the contents of the abnormality that occurred and the time information when the abnormality occurred are stored in each. In order to obtain this time information, a real time clock (hereinafter referred to as RTC) is usually mounted. However, considering the case where data exchange between the control unit and the display unit is interrupted or disconnected for some reason. It is desirable to mount an RTC on each of the control unit and the display unit. That is, there are two independent RTCs in the control device configured as an integrated type. The RTC is a timepiece that includes a clock transmitter and performs a timekeeping operation autonomously.

  However, the RTC performance varies, and an allowable range (monthly difference) is set for how much delay occurs in the month. Therefore, in two RTCs, an error of several seconds occurs every month, especially in different types of RTCs (manufacturers, model numbers, etc.), the setting of this monthly difference is also different, and an error of several seconds or more per month is almost the same. Will definitely occur. And as RTC mounted in a control part and a display part, a ready-made product with high versatility is used conventionally, and the kind is often different. Therefore, in the integrated control device in which the control unit and the display unit are combined, the clock information of the two RTCs may have an error of several seconds per month or more.

  On the other hand, when analyzing the cause of an abnormality that has occurred, information indicating the time at which the abnormality occurred is an important clue. As described above, if there is an error in the information (clock information) indicating the time obtained from the RTC of the control unit and the display unit, the abnormality caused by the same cause is changed to different clock information in the control unit and the display unit. Will be recorded based on. As a result, the user may misunderstand that two different abnormalities have occurred.

Japanese Patent Application Laid-Open No. 2004-133867 discloses a conventional technique in which an RTC is incorporated in a control device to enable reading and setting of clock information. Similarly to Patent Document 1, an RTC is incorporated in a PLC that is a representative example of a control device and a programmable display that is connected to the PLC and constitutes a control system. Conventionally, a PLC RTC is set from a dedicated tool, and a programmable display RTC is set from a maintenance screen of the programmable display.
JP 2003-229760 A

  However, according to the conventional method, the clock information of the control unit and the display unit is set individually, and cannot be set collectively. Further, when synchronizing the respective clocks, it has been pointed out that a dedicated part needs to be arranged on the screen, and the process for performing the synchronization is complicated.

  In addition, when the user wants to synchronize the clock information of the control unit and the display unit periodically, the user needs to execute the synchronization process using a dedicated component each time. It was pointed out that it was cumbersome to deal with.

  The present invention has been made paying attention to such conventional problems, and the object of the present invention is to provide a control unit that functions as a PLC and a display unit that functions as a programmable display. In the control device, a clock control information obtained from the RTC in the control unit is periodically written into the RTC in the display unit, and a control device capable of automatically performing the periodic synchronization processing of the RTC built in each is provided. There is to do.

  Another object of the present invention is that when a communication abnormality occurs between the control unit and the display unit, it is possible to continue operation by providing RTCs that operate independently. It is to provide a control device.

  Other objects and effects of the present invention should be easily understood by those skilled in the art by referring to the following description of the specification.

  According to the embodiment of the present invention, a control unit that functions as a programmable controller including a real time clock that provides clock information, and a function as a programmable display that includes a real time clock that provides clock information And an integrated control device configured by connecting the control unit and the display unit by an internal bus and accommodating the display unit in a single housing. The control unit includes a control unit and a display unit. A shared memory that can be accessed from both sides, means for reading the clock information on the control unit side and writing it to the shared memory at a fixed period, and reading the clock information on the control unit side written in the shared memory to The clock information on the control unit side held in the internal memory of the display unit is used as the clock information of the display unit. And a clock information updating means for writing the clock with a built-in clock generator incorporated in radical 113, thereby characterized in that synchronized to each automatically fixed period of two real-time clock.

  The “clock information” here refers to information for specifying the date and time, and indicates, for example, year (year), month, day, hour, minute, second information. The “real time clock” (hereinafter referred to as “RTC”) is a clock that has a clock generator and performs timekeeping operation autonomously, and means a chip dedicated to timekeeping. It is. With such a configuration, in the integrated control device having two independent RTCs in the control unit and the display unit, it is possible to automatically synchronize the clock information obtained from the two RTCs, Convenience is greatly improved. In addition, by periodically executing the synchronization processing of the clock information of the control unit and the display unit, it is possible to save the user from performing the synchronization processing one by one, and by appropriately adjusting the period of performing the synchronization, It is possible to prevent the occurrence of errors in the clock information obtained from two RTCs.

  According to the embodiment of the present invention, the clock information update means has a means for determining whether or not communication between the control unit and the display unit is possible, and allows communication between the control unit and the display unit. Only when it is determined that the clock information is updated, the clock information updating means is executed.

  With such a configuration, it is possible to identify a case where communication between the control unit and the display unit is disconnected for some reason (communication impossible). When the communication between the control unit and the display unit is impossible, the display unit cannot access the shared memory in the control unit and cannot obtain the clock information of the control unit. Without executing, based on the clock information obtained by the last clock information update means, the RTC in the display unit can operate independently and continue to provide clock information.

  According to the embodiment of the present invention, the clock information update unit further includes a determination unit that determines whether the clock information of the control unit written in the internal memory is within a predetermined range, and is within the predetermined range. The clock information update means is executed only when it is determined.

  With such a configuration, for example, in the case where some abnormality has occurred in the clock information of the control unit and clock information that is clearly not normal is presented, the display unit side displays the incorrect clock information as its own clock information. It is possible to prevent overwriting. In addition, as the “predetermined range” referred to here, various settings can be made such as, for example, determining that the year is over 2100 AD as abnormal.

  According to the embodiment of the present invention, even when it is determined in the clock information update means that the clock information update means is not executed, the clock information is updated when a determination condition for executing the clock information update means is satisfied later. The information updating means is automatically restarted.

  With such a configuration, it is determined that communication between the control unit and the display unit is not possible, and even when the execution of the clock information update process is interrupted, the clock is not restored when communication between the control unit and the display unit is restored. The information update process can be automatically restarted. Even if it is determined that the clock information in the internal memory is not a normal value and the execution of the clock information update process has been interrupted, the clock information is restored when the clock information in the internal memory returns to the normal range. The update process can be automatically restarted. Then, it is found that there is an abnormality in the clock information on the control unit side, and the clock information update process is automatically restarted by correcting the clock information of the control unit to an appropriate value, and the control unit and the display unit The process of synchronizing the clock information is resumed.

  In the control device of the present invention, it is possible to automatically execute a synchronization process that periodically synchronizes the clock information in the control unit and the clock information in the display unit to prevent an error from occurring in each clock information. It becomes possible. Further, by setting the clock information on the control unit side by such a synchronization process, it is automatically reflected in the clock information on the display unit side, and the clock information of both can be set collectively.

  Hereinafter, a preferred embodiment of a control device of the present invention will be described in detail with reference to the accompanying drawings. The embodiment described below is merely an example of the present invention, and the gist of the present invention is defined only by the description of the scope of claims.

  As described above, the control device in the present application is a control device having both a control unit having a PLC function and a display unit having a programmable display function. In the following description, the function of the PLC and the function of the programmable display are used as an integrated control device for convenience, but the electronic device combined with the PLC is not limited to the function of the programmable display.

  A hardware configuration diagram of a control device according to the present invention is shown in FIG. As shown in the figure, a control unit 1 having a PLC function and a display unit 2 having a programmable display function are connected by an internal bus 3. The control unit 1 includes a microprocessor (MPU) 11, an application specific IC (ASIC) 12, an RTC 13, an external interface (external I / F) 14, an input / output memory (IOM) 15, a ROM 16, And a work RAM 17.

  The input / output memory (IOM) 15 is a memory used as an external I / O allocation memory or a data memory used in a user program. The ROM 16 is a memory that stores system firmware. The work RAM 17 is a memory used as a system work. The ASIC 12 has a function of sequentially reading out and executing programs from the user program memory, and writing the execution results to the input / output memory (IOM) 15.

  The microprocessor (MPU) 11 performs overall control of the entire control unit 1. The ROM 16 stores a system program processed by the microprocessor (MPU) 11. The work RAM 17 stores various data over the entire processing of the microprocessor (MPU) 11. The input / output memory (IOM) 15 is a memory that is referred to / rewritten as a substitute for input / output information input / output to / from the input / output device by executing a program. The ASIC 12 sequentially reads and executes programs from the user program memory (UM), and writes the execution results to the input / output memory (IOM) 15. The clock information in the RTC 13 connected to the MPU 11 includes year (year), month, day, hour, minute, and second.

  Next, the display unit 2 includes a CPU 21, an RTC 22, a flash memory 23, a flash memory 24, a work memory 25, and a drawing CPU 26. Here, a system program is stored in the flash memory 23, and drawing data is stored in the flash memory 24. The RTC 22 on the display unit 2 side is the same as the RTC 13 of the control unit 1 and includes year (year), month, day, hour, minute, and second as clock information. And the display part 2 outputs and displays the calculation result etc. which are performed by the control part 1 on the display for display which is not shown in figure.

  As shown in the figure, the ASIC 12 of the control unit 1 and the CPU 21 of the display unit 2 are connected by an internal bus 3. Although not shown, the ASIC 12 has a memory shared by the control unit 1 and the display unit 2 described later.

  As described above, the RTCs 13 and 23 are independently provided in the control unit 1 and the display unit 2 in the control device. One reason for synchronizing the clock information of these two RTCs is to analyze the abnormal state. By synchronizing the clock information of the control unit 1 functioning as a PLC and the display unit 2 functioning as a programmable display, for example, the generation time of an abnormality history stored when an abnormality occurs on the control unit side, and the display unit 2 The analysis work can be facilitated by the coincidence of the detected abnormality occurrence time. In addition, when an abnormality occurs in a networked device group, the cause will be investigated from the abnormality history of each device, but by synchronizing the clock information of each device, It is possible to investigate the cause of the failure without considering the error time.

  Hereinafter, detection and registration processing of an abnormal state executed by the control unit 1 and the display unit 2 in the present embodiment will be described with reference to the flowcharts of FIGS. FIG. 2 shows processing when an abnormality occurs. As shown in the figure, since the abnormal state registration process is based on the assumption that an abnormality has been detected, a determination is made as to whether an abnormality has been detected (step 201). And when abnormality is not detected (step 201, NO), nothing is performed until abnormality is detected. On the other hand, if any abnormality is detected (step 201, YES), then an abnormality code is set (step 202), and an abnormality history registration process described later is executed (step 203).

  Next, FIG. 3 shows a detailed flowchart of the abnormality history registration process in step 203 of FIG. As shown in the figure, the abnormality history registration processing includes related information registration (step 301), clock information setting (step 302), and registration of abnormality history data to the nonvolatile memory (step 303). It is. In the related information registration in step 301, an abnormality flag related to the occurrence of an abnormality is set. In the clock information setting in step 302, the clock information is read from the RTC, and the read clock information is registered as an abnormality occurrence time. In step 303, the abnormality history data obtained in steps 301 and 302 is stored in the nonvolatile memory. In the present embodiment, it is set so that a maximum of 20 abnormality histories can be stored. When the abnormality history exceeds 20, the oldest abnormal data is discarded and the latest data is stored instead. The

  The above-described abnormality detection and registration processing is executed independently by the control unit 1 and the display unit 2, and the RTC referenced in step 302 uses RTC clock information built in each.

  Next, FIG. 4 is a diagram for explaining clock setting and synchronization processing in the present embodiment. As shown in the figure, in the present embodiment, the clock setting 30 set on the display unit 2 side is transmitted to the control unit 1 by a communication command and sets clock information. That is, the clock information of the control unit 1 is set by the user via the maintenance screen of the display unit 2 and the communication command. If the clock information of the control unit 1 is set, the clock information of the control unit 1 and the display unit 2 is automatically reflected in the clock information of the display unit 2 by the clock information synchronization process described later. Can be set in a batch.

  The synchronization process between the RTC 13 of the control unit 1 and the RTC 22 of the display unit 2 will be described below. First, in this embodiment, regarding the relationship between the control unit 1 and the display unit 2, the control unit 1 side is set as a master (master) and the display unit 2 side is set as a slave (slave) considering control as a main. Therefore, clock information transmitted from the RTC 13 of the control unit 1 serving as a master is written as clock information in the RTC 22 on the display unit 2 side, and the clock information in the control unit 1 and the display unit 2 is synchronized.

  As shown in FIG. 4, the control unit 1 is provided with a clock information storage memory 18, which stores clock information obtained from the RTC 13 built in the control unit 1. Yes. A shared memory 19 is provided in the control unit 1. The shared memory 19 is a memory provided in the ASIC 12 in the control unit 1 described above and shared by the control unit 1 and the display unit 2. Then, the control unit 1 copies the clock information stored in the clock information storage memory 18 to the shared memory 19 every predetermined time. The display unit 2 includes an internal memory 28, and the clock information of the control unit 1 stored in the shared memory 19 is periodically reflected in the internal memory 28 by cyclic processing on the display unit 2 side. . The clock information of the control unit 1 is periodically updated in the internal memory 28 by cyclic processing, and the display unit 23 executes clock synchronization processing 29 based on the clock information stored in the internal memory 28. Yes.

  At this time, the clock information in the clock information storage memory of the control unit 1 is periodically reflected in the internal memory 28 of the display unit 2 via the shared memory 19. In the present embodiment, the reflection of the clock information to the internal memory 28 of the display unit 2 is executed at 100 msec intervals. Here, since the clock information in the RTC is limited to the second unit, the clock information held in the internal memory 28 is the same as the clock information stored in the control unit 1 and is the same as the RTC in the control unit. Time will be engraved. Then, the clock information on the display unit 2 is synchronized with the clock information in the internal memory 28. In this embodiment, the clock information on the display unit 2 is synchronized with the clock information in the internal memory 28 every 5 seconds. The interval of this synchronization process can be set to an arbitrary interval by the user.

  First, a process of storing clock information in the shared memory 19 on the control unit 1 side will be described with reference to FIG. The control unit 1 executes connection confirmation of the display unit 2 after powering on the apparatus (step 501). At this time, when the connection of the display unit 2 cannot be confirmed (step 501, NO), the process is not executed until the connection of the display unit 2 is confirmed. When the connection of the display unit 2 is confirmed (step 501, YES), the display unit initialization process is subsequently executed (step 502). After completion of the initialization process, it is determined whether or not communication with the display unit 2 is possible (step 503). If communication is not possible (step 503, NO), nothing is executed until it becomes possible. . On the other hand, if communication with the display unit 2 is possible, cyclic processing (step 504) and event processing (step 505) are executed, and the processing returns to step 503 and is repeated.

  In the cyclic processing in step 505, the channel data of the control unit 1 is block copied to the shared memory 19. At this time, the clock information of the control unit 1 is also read and copied to the shared memory 19, which is realized by writing control information and clock data in a specific area on the shared memory 19. When the cyclic processing is completed, the control unit 1 releases the access right to the shared memory 19 so that the shared memory 19 can be accessed from the display unit 2 side. The event processing in step 506 is communication between the control unit 1 and the display unit 2 using a communication command. Even after execution of this event processing, the access right of the shared memory 19 is released, and the shared memory 19 can be accessed from the display unit 2 side.

  Next, processing on the display unit 2 side will be described with reference to FIG. First, initial processing on the display unit 2 side is executed (step 601), and then it is confirmed that the access right to the shared memory 19 is released (step 602). If the access right is not released (step 602, NO), the control unit 1 waits until the access right is released. If it is confirmed that the access right is released (step 602, YES), cyclic processing on the display unit 2 side is executed (step 603). The cyclic processing on the display unit 2 side copies the channel data and clock information of the control unit 1 copied to the shared memory 19 by the control unit 1 to the internal memory 28 in the display unit 2. By the cyclic processing of the control unit 1 and the cyclic processing of the display unit 2, a data link between the control unit 1 side and the display unit 2 side is realized once per cycle. Subsequently, it is determined again whether or not the access right is released (step 604). If the access right is released (step 604, YES), event processing on the display unit 2 side is executed (step 605). If the access right is not released (step 604, NO), the process waits until the access right is released. The event process on the display unit 2 side is the same as the event process on the control unit 1 side, and communication is performed between the control unit 1 and the display unit 2 using a communication command. Two systems (0/1) are prepared, and two communication commands can be transmitted and received simultaneously. In addition, communication commands used for communication between devices connected via a serial cable or an Ethernet (registered trademark) cable can be used as they are.

  As described above, the clock information of the RTC 13 in the control unit 1 is cyclically written to the internal memory 28 in the display unit 2 via the shared memory 19. As described above, in this embodiment, since the cyclic processing is executed at 100 msec intervals, the clock information in the internal memory 28 of the display unit 2 is periodically refreshed.

  Next, the clock synchronization process in the display unit 2 will be described with reference to the flowchart of FIG. As already described with reference to FIGS. 4 to 6, the clock information of the control unit 1 is periodically updated by the cyclic processing in the internal memory 28 in the display unit 2. For this reason, in the clock synchronization process of the display unit 2, first, an initial process associated with power-on is executed (step 701), and then it is determined whether communication with the control unit 1 is possible (step 702). .

  Here, as a background for determining whether or not communication is possible, if the control unit 1 and the display unit 2 are connected by an internal bus 3 and the internal bus 3 is disconnected for some reason. As a result, the communication between the control unit 1 and the display unit 2 is interrupted, and as a result, the cyclic refresh of the clock information executed between the control unit 1 and the display unit 2 is not normally executed. That is, the display unit 2 cannot access the shared memory 19 in the control unit 1, and as a result, clock information cannot be obtained. In such a situation where communication is disconnected, the clock information update means is not executed.

  Returning to the flowchart of FIG. 7, if it is determined that the communication is disconnected (NO in step 702), the subsequent clock synchronization processing is not executed until the communication is restored. By doing in this way, when communication is cut off, the display unit 2 loses clock information due to the RTC 22 built in the display unit 2 operating independently based on the last updated clock information. It becomes possible to prevent this.

  When it is determined in step 702 that communication is possible (step 702, YES), clock information reading processing for reading clock information from the internal memory 28 is executed (step 703). Subsequently, it is determined whether or not the read clock information is normal (step 704). Here, various determination logics can be adopted in accordance with the application, but in the present embodiment, by determining whether or not the read clock information is within a predetermined range (range). Executed. Of course, this range can also be set to a desired range. By incorporating such a determination logic, it is possible not to execute the synchronization process when the RTC 13 of the control unit 1 clearly shows abnormal clock information.

  In step 704, if the read clock information is normal (within a predetermined range) (YES in step 704), clock information update processing for setting the clock information as clock information of the display unit 2 is executed. (Step 705). On the other hand, when the read clock information is not normal (outside the predetermined range) (step 704, NO), the process returns to step 702 and the process is continued until it is determined that the read clock information is normal. repeat. Then, when the read clock information returns to a predetermined range and is determined to be normal, the subsequent clock information update process is resumed at that time.

  After completion of the clock information update process in step 705, it is subsequently determined whether or not the synchronization waiting time has elapsed (step 706). If the synchronization waiting time has elapsed (step 706, YES), the process proceeds to step 702. Return and repeat the clock synchronization process. On the other hand, if the synchronization waiting time has not elapsed (step 706, NO), the clock synchronization processing is repeated after the synchronization waiting time has elapsed. The synchronization waiting time referred to here is an interval for executing a synchronization process arbitrarily set by the user. In this embodiment, the synchronization waiting time is set to 5 seconds. Therefore, the clock information on the control unit 1 side and the clock information on the display unit 2 side are synchronized every 5 seconds. In this example, the synchronization waiting time is set to 5 seconds, but the user can freely set it in accordance with the purpose and environment.

  As described above, according to the present invention, when the clock information is set on the display unit 2, the clock information on the control unit 1 and the display unit 2 can be collectively set, and the control unit 1 can be periodically set at arbitrary intervals. And the clock information of the display unit 2 can be synchronized, and convenience is greatly improved. Further, even when a communication abnormality occurs between the control unit 1 and the display unit 2, it is possible to continue the operation by operating each timepiece independently.

  In the present embodiment, in the control device in which the PLC and the programmable display are integrated, the clock information set in the shared memory is used for synchronization, but by using the communication command, It can be synchronized even in a network environment where a PLC and a programmable display are mixed. In this case, the timing of clock synchronization is performed every fixed period (5 seconds in the present embodiment), but the user can change it to an arbitrary period. The display unit serving as the slave uses the communication command to read the master (main) clock information for each specified period and set the clock information in the local RTC. Even in a network environment where a PLC and a programmable display are mixed, it is possible to correct the clock information of all the PLCs (programmable displays) on the network by correcting the clock information of the PLC serving as the master clock. I can do it.

  In the above-described embodiment, the control function is the main, the control unit 1 is mainly the display unit 2 and the clock information on the display unit 2 is synchronized with the clock information on the control unit 1 side. It is not limited. Moreover, in this embodiment, although the control part which has the function of PLC, and the display part which fulfill | performs the function as a programmable display are made into one integrated control apparatus, the control part as a PLC, and a programmable display Needless to say, the clock information synchronization process of the present invention can be applied to synchronize the RTC built in each of the other RTC built-in electronic devices as an integrated control device. .

  As is clear from the above description, according to the present invention, when clock information is set from the maintenance screen of the programmable display, the clock information of the PLC and the programmable display can be set at once, and more regularly. It becomes possible to automatically synchronize the clock of the PLC and the programmable display.

It is a block diagram which shows the hardware constitutions of the control apparatus of this embodiment. It is a flowchart which shows the process at the time of abnormality occurrence. It is a flowchart which shows the detail of abnormality log | history registration processing. It is a figure for demonstrating the synchronous process of clock information. It is a flowchart which shows the clock information acquisition process by the side of a control part. It is a flowchart which shows the clock information acquisition process by the side of a display part. It is a flowchart which shows a clock synchronization process.

Explanation of symbols

1 Control Unit 2 Display Unit 3 Internal Bus 11 MPU
12 ASIC
13 RTC (control unit side)
14 External I / F
15 IOM
16 ROM
17 Work RAM
18 Clock information storage memory 19 Inner work area 21 CPU
22 RTC (Display side)
23 Flash memory (system program)
24 Flash memory (drawing data)
25 Work memory 26 Drawing CPU
28 Internal memory 29 Clock synchronization processing 30 Clock setting

Claims (4)

A control unit that functions as a programmable controller including a real time clock that provides clock information, a display unit that functions as a programmable display including a real time clock that provides clock information, and the control An integrated control device configured by connecting a display unit and a display unit via an internal bus and accommodating the display unit in a single housing,
The control unit further includes a shared memory that is accessible from both the control unit and the display unit,
Means for reading the clock information on the control unit side in a certain cycle and writing it to the shared memory; and means for reading the clock information on the control unit side written in the shared memory and writing it to the internal memory provided in the display unit,
Clock information updating means for writing clock information on the control unit side held in the internal memory of the display unit to a clock incorporating a clock oscillator built in the display unit as clock information of the display unit,
Thus, a control device that automatically synchronizes two real time clocks at fixed intervals.   The clock information updating means has means for determining whether communication between the control unit and the display unit is possible, and only when it is determined that communication between the control unit and the display unit is possible The control device according to claim 1, wherein update means is executed.   The clock information update means further includes a determination means for determining whether the clock information on the control unit side written in the internal memory is within a predetermined range, and only when the clock information is determined to be within the predetermined range The control device according to claim 1, wherein the updating unit is executed.   Even when it is determined in the clock information update means that the clock information update means is not executed, the clock information update means is automatically restarted when a determination condition for executing the clock information update means is satisfied later. The control device according to claim 2 or 3, characterized by the above.

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