CN117153822B - Three-dimensional stacking structure and detection method thereof - Google Patents
Three-dimensional stacking structure and detection method thereof Download PDFInfo
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Abstract
The invention discloses a three-dimensional stacking structure and a detection method thereof, wherein the three-dimensional stacking structure comprises: a plurality of chips stacked and connected through an interconnection structure; the interconnection structure comprises a functional interconnection structure for connecting a functional circuit and a protection interconnection structure for protecting the functional interconnection structure; the protection interconnection structure and active devices on the chips are connected in series to form N self-oscillation loops, N is an integer greater than 1, the N self-oscillation loops are connected to the same ground terminal, and oscillation signals used for representing the connection state of the interconnection structure are generated. To provide a three-dimensional stacked structure detection scheme with low cost, low chip area and low power consumption.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a three-dimensional stacking structure and a detection method thereof.
Background
The test is a key process of the semiconductor chip, is a key analysis means for design quality, casting quality and product yield, and plays a vital role in time, material cost control and other aspects for subsequent processes such as packaging. Reliability testing of interconnect structures is an important loop for three-dimensional stacked structures.
Currently, testing of interconnect structures requires designing dedicated test circuitry for each interconnect structure. However, with the development of advanced manufacturing processes and the increase of complexity of current integrated circuits, the integration density of three-dimensional stacked structures is continuously increased, and the number of interconnection structures included in the three-dimensional stacked structures is also significantly increased, so that the occupation area of a test circuit is large, the cost is wasted, the leakage of the test circuit is caused, and the additional power consumption in the working process of a chip is also caused.
Disclosure of Invention
The present invention has been made in view of the above problems, and has as its object to provide a three-dimensional stacked structure and a detection method thereof that overcome or at least partially solve the above problems.
In a first aspect, there is provided a three-dimensional stacked structure comprising:
a plurality of chips stacked and connected through an interconnection structure; the interconnection structure comprises a functional interconnection structure for connecting a functional circuit and a protection interconnection structure for protecting the functional interconnection structure;
the protection interconnection structure and active devices on the chips are connected in series to form N self-oscillation loops, N is an integer greater than 1, and the N self-oscillation loops are connected to the same ground terminal to generate oscillation signals used for representing the connection state of the interconnection structure.
Optionally, the total number of active devices connected in series in each self-oscillation loop is an odd number.
Optionally, the active device is any one or a combination of the following: an NOT gate, a transmission gate, an equivalent circuit of an NOT gate, and an equivalent circuit of a transmission gate.
Optionally, the self-oscillation loop includes a control device connected in series with the protective interconnect structure; the control device is used for controlling the oscillation state of the self-oscillation loop.
Optionally, the control device is an and gate, an equivalent circuit of an and gate or a switching device.
Optionally, the three-dimensional stacked structure further includes: the detection module is connected with the N self-oscillation loops to acquire the frequency of the oscillation signals, so that the connection state of the interconnection structure is judged according to the frequency.
Optionally, the detection module includes a frequency dividing circuit and a detection circuit, and the frequency dividing circuit reduces the frequency of the oscillation signal for detection by the detection circuit.
Optionally, the N self-oscillation loops include at least two adjacent loops, and the protection interconnection structure of any one of the two adjacent loops is disposed adjacent to the protection interconnection structure of the other adjacent loop.
Optionally, the protection interconnection structure of any one of the two adjacent loops is arranged adjacent to the protection interconnection structure of the other adjacent loop in parallel; alternatively, the protection interconnection structure of any one of the two adjacent loops is alternately adjacent to the protection interconnection structure of the other adjacent loop.
In a second aspect, a method for detecting a three-dimensional stacked structure, where the three-dimensional stacked structure is the three-dimensional stacked structure according to the first aspect, is provided, and the method includes:
obtaining oscillation signals of the N self-oscillation loops;
if the oscillation signals with the frequency of zero exist, determining that the N self-excited oscillation loops have open circuits according to the detection results;
if the oscillation signals with the frequencies conforming to the preset short-circuit frequency range exist, determining that the detection results are that the N self-oscillation loops have short circuits;
and judging the connection state of the interconnection structure according to the detection result.
The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:
the three-dimensional stacked structure and the detection method thereof provided by the embodiment of the invention consider that the interconnection structure for connecting each chip comprises a functional interconnection structure for connecting functional circuits of the chips and a protective interconnection structure for protecting the functional interconnection structure, wherein the functional interconnection structure is positioned in the middle area of the chip. All or part of the protection interconnection structure and the active device are connected in series to form N self-oscillation loops, so as to generate oscillation signals. The oscillation signals generated by the self-oscillation loops are related to the connection relation of the structures connected in series in the corresponding self-oscillation loops, so that the connection state of the protection interconnection structure can be judged according to the oscillation signals of the self-oscillation loops, and whether the connection state of the functional interconnection structure is reliable or not can be deduced according to the connection state of the protection interconnection structure due to the consistency of the chip preparation process, especially the local consistency, without arranging a detection circuit for each interconnection structure, the chip area cost required by testing is greatly reduced, the testing cost is saved, and the testing speed is also improved. And compared with the traditional method for detecting the interconnection structure one by one, the method uses few active circuits, and obviously reduces the static power consumption generated by standby of the test circuit in the normal working process of the device, thereby reducing the power consumption in the working state of the system.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of a three-dimensional stacked structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a three-dimensional stacked structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a three-dimensional stacked structure according to an embodiment of the present invention;
FIG. 4 (a) is a schematic diagram showing the arrangement of two adjacent loops according to an embodiment of the present invention;
FIG. 4 (b) is a second schematic diagram illustrating the arrangement of two adjacent loops according to an embodiment of the present invention;
FIG. 5 (a) is a third schematic diagram of the arrangement of two adjacent loops according to an embodiment of the present invention;
FIG. 5 (b) is a schematic diagram showing the arrangement of two adjacent loops according to an embodiment of the present invention;
FIG. 6 is a schematic diagram I of a series arrangement of protection interconnections in a self-oscillating loop in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram II of a series arrangement of protection interconnections in a self-oscillating loop according to an embodiment of the present invention;
FIG. 8 is a schematic diagram III of a series arrangement of protection interconnects in a self-oscillating loop in accordance with an embodiment of the present invention;
FIG. 9 is a schematic diagram I of a connection mode and a trace shape of a self-oscillation loop according to an embodiment of the present invention;
FIG. 10 is a second schematic diagram of the connection mode and the trace shape of the self-oscillation loop in the embodiment of the present invention;
FIG. 11 is a schematic diagram I of an active device in a self-oscillation loop in series with a protective interconnect structure in an embodiment of the present invention;
FIG. 12 is a second schematic diagram of an active device in a self-oscillating loop in series with a protective interconnect structure in an embodiment of the present invention;
FIG. 13 is a schematic diagram of a control device in a self-oscillation loop in series with a protective interconnect structure in an embodiment of the present invention;
FIG. 14 is a schematic diagram of a detection module disposed in a self-oscillation loop according to an embodiment of the present invention;
fig. 15 is a flowchart of a method for detecting a three-dimensional stacked structure according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
Referring to fig. 1 and 2 (fig. 1 is a top view example of fig. 2), a three-dimensional stacked structure includes: a plurality of chips 101 connected by an interconnect structure 1 are stacked, the interconnect structure 1 including a functional interconnect structure 11 (in a square filled circle) connecting functional circuits and a protective interconnect structure 12 (in a hollow circle) for protecting the functional interconnect structure 11. The protective interconnect structure 12 is wholly or partially connected in series to form a free running oscillation loop 2 to generate an oscillation signal for testing the connection state of the interconnect structure 1.
Specifically, as shown in fig. 1, the central region of the chip is provided with a functional interconnect structure 11 for functional circuit interconnection, which is a circuit for realizing the electrical function of the chip, such as a memory circuit, a logic calculation circuit, an image processing circuit, a power supply, or the like; the power supply is used to power the three-dimensional stacked structure across the chip. A protective interconnect structure 12 is also provided on the chip for protecting functional circuitry during the manufacturing process and assuming the function of other conventional redundancy cells. The functional interconnect structure 11 connects functional circuits and/or power supplies between different chips as channels for signal and current transmission. The protection interconnect structure 12 is used to protect the functional interconnect structure 11. The protective interconnection structure 12 may be disposed in a vicinity of the functional interconnection structure 11, and as the chip integration increases, the number of the functional interconnection structure 11 and the protective interconnection structure 12 in the three-dimensional stacked structure is huge, which can reach more than ten thousand. All or a portion of the protective interconnect structure 12 is connected in series to form a self-oscillating loop. The self-oscillation loop contains abundant harmonic waves, the self-oscillation loop contains a protective interconnection structure 12 mainly in a serial form, and the distribution parameters, the interconnection number and the connection mode of the protective interconnection structure determine the oscillation signal frequency of the filtering output of the self-oscillation loop. Therefore, the connection state of the protection interconnection structure 12 can be judged according to the frequency of the oscillation signal, and the connection state of the functional interconnection structure 11 can be deduced and tested according to the connection state of the protection interconnection structure 12 due to the consistency of the chip preparation process, especially the local consistency, without arranging a detection circuit for each functional interconnection structure 11, so that the chip area cost required by the test is greatly reduced, the test cost is saved, and the test speed is also improved.
For example, assuming that the frequency of the oscillation signal of the self-oscillation loop 2 is detected to be zero, i.e., oscillation is lost, it can be determined that the self-oscillation loop is broken. In this way, it can be deduced from the process consistency that the functional interconnect structure 11 has a high probability of breaking failure. Assuming that the frequency of the oscillation signal of the self-oscillation loop 2 is detected to be in a preset normal range (which may be a range preset according to the number and connection relation of the protection interconnect structures 12 included in the self-oscillation loop 2), it is determined that the self-oscillation loop has no problem of disconnection. It can thus be deduced from the process consistency that there is less likelihood of a break in the functional interconnect structure 11. The method can find out the open circuit failure of most of the functional interconnection structures 11 in the chip mass production link and provide analysis data with failure fault types and position labels; even though special cases not found by the method may occur, the method can still be found through subsequent conventional Test links, such as a probe Test (Chip Probing), a DFT Test (Design For Testability) and a package Test (Final Test), and the effectiveness of the method is not affected.
The three-dimensional stacked structure shown in fig. 1 can detect the free-running oscillation loop disconnection from the frequency of the oscillation signal of the free-running oscillation loop 2, and thus the possibility of disconnection of the functional interconnection structure 11 can be inferred. However, it cannot detect whether the functional interconnection structure 11 is short-circuited, because the number of the protection interconnection structures 12 is large, when the short-circuit of the protection interconnection structures 12 occurs in the self-oscillation loop 2, the influence on the oscillation signal generated by the self-oscillation loop 2 is small and can be basically ignored, so that whether the self-oscillation loop 2 is short-circuited cannot be detected according to the oscillation signal, and further, the short-circuit condition of the functional interconnection structure 11 cannot be deduced, and therefore, a circuit for detecting the short-circuit needs to be additionally provided for each interconnection structure, resulting in chip area and cost loss.
An embodiment of the present application provides a three-dimensional stacked structure, as shown in fig. 3, including: a plurality of chips connected by the interconnect structure 1 are stacked, and the interconnect structure 1 includes a functional interconnect structure 11 (in a square filled circle in fig. 3) connecting functional circuits and a protective interconnect structure 12 for protecting the functional interconnect structure 11. The protection interconnect structure 12 may be disposed around the functional interconnect structures 11 or interposed between the functional interconnect structures 11. All or part of the protection interconnection structure 12 is connected in series with active devices arranged on a plurality of chips to form N self-oscillation loops 2 (in fig. 3, the protection interconnection structure 12 marked by a circle with a hollow in series on one self-oscillation loop 2, and the protection interconnection structure 12 marked by a circle with a diagonal line filled in series on the other self-oscillation loop 2), N is an integer greater than 1, and the N self-oscillation loops 2 are connected to the same ground terminal to generate an oscillation signal for representing the connection state of the interconnection structure 1.
Wherein, each self-oscillation loop 2 is independent logically, and the circuits or devices are independent, so that the open circuit and the short circuit failure of the self-oscillation loop can be judged simultaneously by comparing the frequencies of oscillation signals of each self-oscillation loop 2 through the common ground arrangement of a plurality of self-oscillation loops 2.
Specifically, since the number of the protection interconnections 12 included in each self-oscillation loop 2 tends to be large, if the protection interconnections 12 are short-circuited inside a single self-oscillation loop, the interference to the oscillation signal generated by the single self-oscillation loop is negligible. However, if there is a short circuit between two or more self-oscillation loops 2, the number and connection manner of the protection interconnections 12 in each self-oscillation loop 2, which causes a short circuit problem, are greatly fluctuated, resulting in that the frequency of the oscillation signal generated thereby is greatly deviated from the frequency of the oscillation signal generated when it is not short-circuited, so that it is possible to determine whether or not the self-oscillation loop 2 is short-circuited by comparing the detected frequency of the oscillation signal with a preset frequency range when there is no short circuit problem. Due to the consistency of the process, the probability of the occurrence of short circuit of the self-oscillation loop 2 is positively correlated with the probability of the occurrence of short circuit of the functional interconnection structure 11, and the probability of the occurrence of short circuit of the functional interconnection structure 11 can be deduced, so that a circuit for detecting the short circuit is not required to be additionally arranged on each interconnection structure, and the chip area and the cost are saved.
It should be noted that the three-dimensional stacked structure may be chip-on-interposer (D2I), chip-on-chip (D2D), chip-on-wafer (D2W), or wafer-on-wafer (W2W), which is not limited herein. The chips stacked in the three-dimensional stacked structure may be the same type of chips (for example, all memory chips), or may be different types of chips (for example, memory chips and logic chips, respectively), which is not limited herein. The chips in the three-dimensional stacked structure may be connected by, for example, hybrid bonding (Hyrid bonding), re-wiring layers (Redistribution Layer, RDL), and through silicon vias (Through Silicon Via, TSV) techniques, and the like, which are not limited herein. The interconnect structure 1 includes, among others, a structure for inter-chip interconnection such as a pad, a solder ball, a bonding wire, a through silicon via, a hybrid bond, or the like.
It should be further noted that, fig. 3 is only a top view example of a three-dimensional stacked structure, where the identified interconnection structure 1 is a perspective example, that is, the interconnection structure 1 may be disposed on any one or multiple stacked layers of chips, the self-oscillation loop 2 may also be disposed on a top layer, a bottom layer, a redistribution layer of an interlayer, a metal layer, an active layer, or the like of the chip, and the self-oscillation loop 2 may also be disposed across the chip or across a structural layer in the chip, which is not limited herein.
For example, assuming that an oscillation signal having a frequency of zero is detected in N self-oscillation loops 2, it can be determined that the self-oscillation loops are open. In this way, it can be deduced from the process consistency that the functional interconnect structure 11 has a high probability of breaking failure. And if the oscillation signals with the frequencies conforming to the preset short-circuit frequency range are detected to exist in the N self-oscillation loops 2, determining that the self-oscillation structure of the self-oscillation loops is damaged and short-circuit failures exist in other self-oscillation loops. Since the chip short circuit is often caused by contamination particles such as dust impurities, the probability of short circuit occurrence in the functional interconnection structure 11 is high from the locality of the short circuit failure. Assuming that the detection results are that the frequencies of the oscillation signals of the N self-oscillation loops 2 are all within a preset normal range (the normal range may be a range preset according to the number and connection relation of the protection interconnection structures 12 included in the self-oscillation loops 2), it is determined that the self-oscillation loops have no problem of disconnection and short circuit. It can thus be deduced from the process consistency that there is less likelihood of open and short circuits in the functional interconnect structure 11.
The method can find out the failure of the circuit breaking and the short circuit of most functional interconnection structures 11 in the mass production link of the chip, and can form the component part of the self-oscillation loop 2 by designing and inserting a protective interconnection structure 12 between the functional interconnection structures 11 and mainly connecting the functional interconnection structures in series so as to increase the failure discovery probability of the short circuit and provide analysis data with failure fault types and position labels; even though special cases not found by the method may occur, the method can still be found through subsequent conventional Test links, such as a probe Test (Chip Probing), a DFT Test (Design For Testability) and a package Test (Final Test), and the effectiveness of the method is not affected.
In a specific implementation process, after deriving the connection state of the functional interconnect structure 11 according to the connection state of the protection interconnect structure 12, product screening or more refined detection may be performed according to the derivation result. For example, if it is deduced from the oscillation signal that there is a high possibility of short-circuit or open-circuit failure of the functional interconnection structure 11, the three-dimensional stacked structure may be identified as defective and eliminated, or a finer connectivity test may be performed on the functional interconnection structure 11 of the three-dimensional stacked structure to determine whether a short-circuit or open-circuit problem is actually present.
In an alternative embodiment, in order to increase the accuracy of the short-circuit failure determination, the N self-oscillating loops 2 may be provided to include at least two adjacent loops, the protection interconnect structure 12 of any one of the two adjacent loops being provided adjacent to the protection interconnect structure 12 of the other adjacent loop. Because the reasons for causing the chip short circuit are usually the attachment of dust or impurities, the arrangement of two adjacent loops is adjacent and close, and the attached dust or impurities are easier to cause the short circuit between the two adjacent loops, so that whether the environmental factors which are easy to cause the short circuit exist or not is more favorable for finding out, the missing detection caused by the condition that the short circuit occurs between the functional interconnection structures 11 due to the environmental factors, but the short circuit does not occur in the two adjacent loops is avoided as much as possible, and the short circuit probability of the functional interconnection structures 11 can be deduced more accurately.
The two adjacent loops in the N self-oscillation loops 2 can be arranged in various ways, so that the distance between the two adjacent loops can meet the preset proximity distance requirement, and three examples are listed below:
first, the protective interconnect structure 12 of any one of two adjacent loops is disposed adjacent in parallel with the protective interconnect structure 12 of the other adjacent loop.
As shown in fig. 3, for the top view example of the three-dimensional stacked structure, the functional interconnection structure 11 is marked as a square filled circle, the protection interconnection structure 12 is marked by a hollow circle connected in series on one of two adjacent loops, and the protection interconnection structure 12 is marked by a diagonal filled circle connected in series on the other adjacent loop, so as to realize adjacent parallel arrangement, so that the two adjacent loops have a distance of loops with enough length to be close enough to detect the short circuit problem more accurately. Of course, there may be more than two adjacent loops disposed adjacent in parallel, without limitation.
Second, the protective interconnect structure 12 of any one of two adjacent loops is alternately disposed adjacent to the protective interconnect structure 12 of the other adjacent loop.
As shown in fig. 4 (a), in the top view example of the three-dimensional stacked structure, the functional interconnection structure 11 is marked as a square filled circle, a hollow circle is connected in series on one of two adjacent loops to identify the protective interconnection structure 12, and a diagonal circle is connected in series on the other adjacent loop to identify the protective interconnection structure 12, as shown in fig. 4 (b), in the routing example of two adjacent loops which are alternately arranged adjacently, so that the two adjacent loops have a distance of loops with a sufficient length close enough to detect a short circuit problem more accurately. Of course, there may be more than two adjacent loops alternately arranged adjacent to each other, without limitation. In an alternative embodiment, the self-oscillation loop 2 can be formed by connecting the protective interconnection structure 12 of the same layer chip in series, so that an additional protective interconnection structure 12 is not needed to be added, and the complexity of the circuit of the self-oscillation loop 2 is reduced.
Third, the first and second arrangements are combined.
As shown in fig. 5 (a), which is a top view example of a three-dimensional stacked structure, the functional interconnect structure 11 is identified as a square filled circle, one of the two adjacent loops is connected in series with a hollow circle identified as a protective interconnect structure 12, and the other adjacent loop is connected in series with a diagonal filled circle identified as a protective interconnect structure 12 to achieve a combination of parallel and alternating adjacent arrangements such that the two adjacent loops are sufficiently close in distance to each other for a short circuit problem to be more accurately detected.
As shown in fig. 5 (b), in the top view example of the three-dimensional stacked structure, the functional interconnection structure 11 is marked as a square filled circle, the protection interconnection structure 12 is marked as a hollow circle connected in series on one of two adjacent loops, the protection interconnection structure 12 is marked as a diagonal filled circle connected in series on the other adjacent loop, and the protection interconnection structure 12 not connected into the self-oscillation loop 2 is marked as a hollow triangle. That is, not only a part of the protection interconnect structures 12 may be skipped from being connected to the free running oscillation loop 2, but also the protection interconnect structures 12 may be provided in the region between the functional interconnect structures 11, and the protection interconnect structures 12 located between the functional interconnect structures 11 may be connected to the free running oscillation loop 2 so as to detect whether there is a short circuit or a short circuit failure in the dense region of the functional interconnect structures 11, thereby improving the accuracy of the subsequent deriving of the connection reliability of the functional interconnect structures 11 from the detection result of the free running oscillation loop 2.
Of course, the arrangement mode of two adjacent loops in the N self-oscillation loops 2 is not limited to the three modes, and the distance between the two adjacent loops with enough length meets the preset proximity distance requirement.
In the implementation, there may be various ways of protecting the interconnection structure 12 in series in each self-oscillating loop 2 of the three-dimensional stacked structure. For example, as shown in fig. 6, all or part of the protective interconnect structure 12 (an equivalent circuit example of the protective interconnect structure 12 in a cylinder) may be connected in series; as shown in fig. 7, there may be a hybrid parallel and series arrangement of protective interconnect structures 12; as shown in fig. 8, the protection interconnect structure 12 may be connected in series or in series-parallel with other devices (e.g., not gates), without limitation. In an alternative embodiment, the total number of the not gates or equivalent not gates of the protection interconnect structure 12 connected in series in the single self-oscillation loop 2 may also be set to be odd, so as to enhance the oscillation signal, and facilitate detection.
In the implementation process, the connection mode and the wiring mode of each self-oscillation loop 2 of the three-dimensional stacked structure can be various. For example, as shown in fig. 9, the self-oscillation loop 2 may skip part of the protection interconnect structure 12 to connect (wherein, the functional interconnect structure 11 is marked as a square filled circle, the protection interconnect structure 12 connected in series on the self-oscillation loop 2 is marked as a hollow circle, and the protection interconnect structure 12 not connected into the self-oscillation loop 2 is marked as a hollow triangle); as shown in fig. 10, the self-oscillation loop 2 may be connected to only a few sides of the protection interconnection structure 12 (wherein, the functional interconnection structure 11 is marked as a square filled circle, and the protection interconnection structures 12 connected in series on the self-oscillation loop 2 are marked as hollow circles), and the rest sides may be the protection interconnection structure 12 not provided or the protection interconnection structure 12 not connected in series into the self-oscillation loop 2; self-oscillating loop 2 may also be placed across multiple chips or across multiple structural layers within a chip, none of which are limiting.
Each self-oscillation loop 2 is also provided with an active device connected in series with the protective interconnection structure 12, and the oscillation signal of the self-oscillation loop is enhanced by the active device. In an alternative embodiment, the total number of active devices connected in series with each self-oscillation loop 2 can be set to be odd, so that the oscillation signal is further enhanced, and the detection accuracy is improved.
In a specific implementation, the active device may be any one or a combination of the following: an NOT gate, a transmission gate, an equivalent circuit of an NOT gate, and an equivalent circuit of a transmission gate. For example, as shown in fig. 11 to 12, it is assumed that the active device is a not gate 1101, the protection interconnection structure 12 is connected in series, and a plurality of not gates 1101 are connected in series in a penetrating manner, and the penetrating manner and the number of the not gates 1101 are not limited, and may be disposed in a main loop of the self-oscillation loop 2 in series as shown in fig. 11, or may be disposed in a parallel circuit as shown in fig. 12. The oscillation signal is enhanced by the logical negation function of the not gate.
The number, types and connection modes of the active devices included in each self-oscillation loop 2 may be the same or different, and are not limited herein.
It should be noted that, the active device in the self-oscillation loop 2 may be disposed in any layer chip of the three-dimensional stacked structure or any structural layer within the chip, which is not limited herein.
In an alternative embodiment, the self-oscillating loop 2 may further comprise a control device connected in series with the protective interconnect structure 12 for controlling the oscillation state of the self-oscillating loop 2. Thus, when the inspection of the interconnection structure 1 is completed, the self-oscillation loop 2 can be disconnected by the control device to stop generating the oscillation signal, thereby saving power consumption.
In the implementation process, the control device may be an and gate, an equivalent circuit of the and gate, or a switching device. For example, as shown in fig. 13, assume that the control device is an and gate 1301, an output terminal and one input terminal of the and gate 1301 are connected in series to the free-running oscillation loop 2, and the other input terminal of the and gate 1301 is configured to receive the control signal osc_en. In detecting the connection state of the interconnect structure in the three-dimensional stacked structure, the self-oscillation loop 2 can be caused to generate an oscillation signal by setting the control signal osc_en, thereby facilitating the detection. In the normal operation mode of the device, the self-oscillation loop 2 can stop oscillation by setting the control signal OSC_en, so that energy loss caused by oscillation is reduced, and energy saving is realized.
The self-oscillation loops 2 may be respectively provided with a control device, or a part of the self-oscillation loops 2 may be provided with a control device, and if the self-oscillation loops 2 all adopt control signals to control the control device, the same control signals may be shared, or the control signals may be respectively provided, which is not limited herein.
It should be noted that the control device in the self-oscillation loop 2 may be disposed in any layer chip of the three-dimensional stacked structure or any structure layer within the chip, which is not limited herein. Of course, the control device may not be provided, and is not limited thereto.
In an alternative embodiment, the self-oscillation loop 2 may further include a detection module connected to the self-oscillation loop 2 to acquire a frequency of the oscillation signal, so as to determine the connection state of the interconnect structure 1 according to the acquired frequency.
In the implementation process, the detection module may be any circuit with a frequency detection function, which is not limited herein. In an alternative embodiment, as shown in fig. 14, the detection module may further include a frequency dividing circuit 1401 and a detection circuit 1402, where the frequency dividing circuit 1401 reduces the frequency of the oscillation signal for detection by the detection circuit 1402, so that a higher hardware requirement caused by high-frequency detection can be avoided, and the detection cost is effectively reduced. The frequency dividing circuit 1401 may be implemented as a multi-stage flip-flop as shown in fig. 14 or as other circuits having a frequency dividing function.
The self-oscillation loops 2 may be respectively provided with a detection module, or may be partially provided with a detection module, which is not limited herein.
It should be noted that, the detection module in the self-oscillation loop 2 may be disposed in any layer of the chip of the three-dimensional stacked structure or any structural layer in the chip, which is not limited herein. Of course, the frequency of the self-oscillation loop 2 may be reduced by not providing a detection module or only providing a frequency dividing circuit, and the frequency detection is performed by an external detection device, which is not limited herein.
Specifically, the invention sets all or part of the protection interconnection structures to form N self-oscillation loops in series to generate oscillation signals. The oscillation signals generated by the self-oscillation loops are related to the connection relation of the structures connected in series in the corresponding self-oscillation loops, so that the connection state of the protection interconnection structure can be judged according to the oscillation signals of the self-oscillation loops, and due to the consistency of the chip preparation process, the connection state of the functional interconnection structure can be deduced according to the connection state of the protection interconnection structure, a detection circuit is not required to be arranged on each interconnection structure, and the chip area cost required by testing is greatly reduced. And because the interconnection structures can be prevented from being tested one by one, the connection and disconnection of the interconnection structures can be tested in batches, the testing speed is also improved, and the cost of a testing machine is saved. Compared with the traditional method for detecting the interconnection structure one by one, the method provided by the invention uses few active circuits, and the static power consumption generated by standby of the test circuit in the normal working process of the device is obviously reduced, so that the power consumption in the working state of the system is reduced.
Based on the same inventive concept, the embodiment of the present invention further provides a method for detecting a three-dimensional stacked structure, where the three-dimensional stacked structure is provided by the foregoing embodiment and includes N self-oscillation loops, as shown in fig. 15, and the method includes:
step S1501, obtaining oscillation signals of the N self-oscillation loops;
step S1502, if the oscillation signal with the frequency of zero exists, determining that the detection result is that the N self-oscillation loops have open circuits;
step S1503, if the oscillation signal with the frequency conforming to the preset short-circuit frequency range exists, determining that the detection result is that the N self-oscillation loops have short circuits;
step S1504, determining the connection state of the interconnection structure according to the detection result.
It should be noted that the inspection method may be applied to an inspection apparatus for chips or wafers, and the inspection apparatus may be an independent inspection device, or may be an apparatus integrated on a chip manufacturing line, which is not limited herein.
In an alternative embodiment, in step S1501, the oscillation signal of the self-oscillation loop may be obtained before the three-dimensional stacked structure leaves the factory, or after the three-dimensional stacked structure leaves the factory, or before or after the wafer is cut, which is not limited herein.
In an alternative embodiment, in step S1503, the preset short-circuit frequency range may be a range that is preset according to the number of protection interconnections 12 and the connection manner in the respective oscillation loop, or may be a range that is set empirically, or a range that is determined by a pre-test, which is not limited herein.
In an optional embodiment, in step S1504, the determining, according to the detection result, the connection state of the interconnection structure may be: if the detection result is that the N self-oscillation loops have the disconnection problem, namely lose oscillation, the possibility that the functional interconnection structure is disconnected is also higher according to the process consistency. If the detection result is that the N self-oscillation loops have a short circuit problem, the possibility that the functional interconnection structure has a short circuit is also higher due to the fact that the chip short circuit is often caused by dust, impurities and other pollution particles and the consistency of the polluted environment can be deduced. If the detection result shows that all the N self-oscillation loops have no problems of open circuit and short circuit, the possibility that the functional interconnection structure has open circuit and short circuit is less according to the process consistency.
In a specific implementation process, after deriving the connection state of the functional interconnection structure according to the connection state of the protection interconnection structure, product screening or more refined detection can be performed according to the derivation result. For example, if it is deduced from the oscillation signal that the functional interconnection structure has a high possibility of short-circuit or open-circuit failure, the three-dimensional stacked structure may be identified as defective and eliminated, or a finer connectivity test may be performed on the functional interconnection structure of the three-dimensional stacked structure to determine whether a short-circuit or open-circuit problem is actually present.
The detection method of the three-dimensional stacked structure described in the embodiment of the present invention is a detection method corresponding to the three-dimensional stacked structure described in the embodiment of the present invention, and the principle and structure of the three-dimensional stacked structure have been described in detail, so that the description thereof will not be repeated here. All detection methods corresponding to the three-dimensional stacking structure of the embodiment of the invention belong to the scope of protection of the invention.
The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:
the three-dimensional stacked structure and the detection method thereof provided by the embodiment of the invention consider that the interconnection structure for connecting each chip comprises a functional interconnection structure for connecting functional circuits of the chips and a protective interconnection structure for protecting the functional interconnection structure, wherein the functional interconnection structure is positioned in the middle area of the chip. All or part of the protection interconnection structure and the active device are connected in series to form N self-oscillation loops, so as to generate oscillation signals. The oscillation signals generated by the self-oscillation loops are related to the connection relation of the structures connected in series in the corresponding self-oscillation loops, so that the connection state of the protection interconnection structure can be judged according to the oscillation signals of the self-oscillation loops, and whether the connection state of the functional interconnection structure is reliable or not can be deduced and tested according to the connection state of the protection interconnection structure due to the consistency of the chip preparation process, especially the local consistency, without arranging a detection circuit for each interconnection structure, the chip area cost required by testing is greatly reduced, the testing cost is saved, and the testing speed is also improved. And compared with the traditional method for detecting the interconnection structure one by one, the method uses few active circuits, and obviously reduces the static power consumption generated by standby of the test circuit in the normal working process of the device, thereby reducing the power consumption in the working state of the system.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present invention is not directed to any particular programming language. It will be appreciated that the teachings of the present invention described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including the abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including the accompanying abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention. Any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the invention. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In an embodiment in which several means are recited, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
Claims (9)
1. A three-dimensional stacked structure, comprising:
a plurality of chips stacked and connected through an interconnection structure; the interconnection structure comprises a functional interconnection structure for connecting a functional circuit and a protection interconnection structure for protecting the functional interconnection structure;
the protection interconnection structure and active devices on the chips are connected in series to form N self-oscillation loops, wherein N is an integer greater than 1; the N self-oscillation loops comprise at least two adjacent loops, and the protection interconnection structure of any one of the two adjacent loops is arranged adjacent to the protection interconnection structure of the other adjacent loop; the N self-oscillation loops are connected to the same ground terminal, so that whether the self-oscillation loops are broken or short-circuited can be determined by comparing the frequencies of oscillation signals generated by the self-oscillation loops, and the connection state of the interconnection structure is judged.
2. The three-dimensional stacked structure of claim 1, wherein:
the total number of active devices connected in series in each self-oscillation loop is an odd number.
3. The three-dimensional stacked structure of claim 2, wherein the active device is any one or a combination of:
an NOT gate, a transmission gate, an equivalent circuit of an NOT gate, and an equivalent circuit of a transmission gate.
4. The three-dimensional stacked structure of claim 1, wherein:
the self-oscillation loop comprises a control device connected in series with the protective interconnection structure; the control device is used for controlling the oscillation state of the self-oscillation loop.
5. The three-dimensional stacked structure of claim 4, wherein the control device is an and gate, an equivalent circuit of an and gate, or a switching device.
6. The three-dimensional stacked structure of any one of claims 1-5, further comprising:
the detection module is connected with the N self-oscillation loops to acquire the frequency of the oscillation signals, so that the connection state of the interconnection structure is judged according to the frequency.
7. The three-dimensional stacked structure of claim 6, wherein:
the detection module comprises a frequency dividing circuit and a detection circuit, wherein the frequency dividing circuit reduces the frequency of the oscillating signal for detection by the detection circuit.
8. The three-dimensional stacked structure of claim 1, wherein:
the protection interconnection structure of any one adjacent loop of the two adjacent loops is arranged adjacently and parallelly with the protection interconnection structure of the other adjacent loop;
alternatively, the protection interconnection structure of any one of the two adjacent loops is alternately adjacent to the protection interconnection structure of the other adjacent loop.
9. A method for detecting a three-dimensional stacked structure, wherein the three-dimensional stacked structure is the three-dimensional stacked structure according to any one of claims 1 to 8, the method comprising:
obtaining oscillation signals of the N self-oscillation loops;
if the oscillation signals with the frequency of zero exist, determining that the N self-excited oscillation loops have open circuits according to the detection results;
if the oscillation signals with the frequencies conforming to the preset short-circuit frequency range exist, determining that the detection results are that the N self-oscillation loops have short circuits;
and judging the connection state of the interconnection structure according to the detection result.
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