CN116996590B - Ethernet speed reducer of FPGA prototype verification platform and data transmission method - Google Patents
Ethernet speed reducer of FPGA prototype verification platform and data transmission method Download PDFInfo
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Abstract
The invention discloses an Ethernet speed reducer for FPGA prototype verification and a data transmission method, wherein the Ethernet speed reducer comprises the following components in sequence: the data receiving module is used for receiving the Ethernet data output by the external Ethernet test instrument; the receiving control module is used for converting the clock domain of the Ethernet data into the FPGA slow clock domain, storing the Ethernet data into the data caching unit and monitoring the data storage state of the data caching unit in real time; the MII interface conversion module is used for converting the working protocol rate of the Ethernet data into a target protocol rate and acquiring the Ethernet conversion data; the encoding module is used for encoding and scrambling the Ethernet converted data to obtain encoded data; the bit width conversion module is used for converting the bit width of the coded data into the bit width of a preset interface; the invention solves the problem of connection between the FPGA verification tool with low clock frequency and the real Ethernet test tool.
Description
Technical Field
The invention relates to the technical field of FPGA prototype verification, in particular to an Ethernet speed reducer of an FPGA prototype verification platform and a data transmission method.
Background
In the field of chip design, as the scale of integrated circuits is increasingly larger, functions are increasingly complex, and the cost of streaming is increasingly higher, so that the design must be sufficiently verified before streaming. The FPGA prototype verification is a common verification method in the field of chip design, and can improve the reliability of the design and reduce the development cost.
In the field of prototype verification, for large chip design, multiple FPGAs are often required to be interconnected, and a large amount of deep combinational logic exists in the chip design, so that the FPGAs cannot operate according to the clock originally designed by the chip, and only a few megahertz or tens of megahertz clock can be met, and the down-conversion processing is required. The common Ethernet tester needs to meet the standard clock of the Ethernet protocol, and cannot perform speed reduction processing; therefore, the current Ethernet tester cannot be directly connected with the FPGA prototype verification platform.
Disclosure of Invention
The technical problem to be solved by the invention is that the prior FPGA prototype verification platform with low clock frequency cannot be directly connected with an Ethernet test tool due to different clock frequencies.
In order to solve the technical problem, the invention provides an Ethernet speed reducer for FPGA prototype verification, which comprises the following components in sequence:
the data receiving module is used for receiving the Ethernet data output by the external Ethernet test instrument;
the receiving control module is used for converting the clock domain of the Ethernet data into an FPGA slow clock domain, storing the Ethernet data converted by the clock domain into the data caching unit, and monitoring the data storage state of the data caching unit in real time;
the MII interface conversion module is used for converting the working protocol rate of the Ethernet data converted by the clock domain into a target protocol rate and obtaining the Ethernet conversion data;
the encoding module is used for encoding and scrambling the Ethernet converted data to obtain encoded data;
the bit width conversion module is used for converting the bit width of the coded data into a preset interface bit width;
the preset interface bit width is the data interface bit width of an external user netlist, and the target protocol rate is the working protocol rate of test data required by the external user netlist.
Preferably, a detection module is further included between the receiving control module and the MII interface conversion module:
the detection module is used for counting the number of Ethernet packets in the Ethernet data converted by the clock domain and recording the Ethernet packets and error packets which do not accord with the Ethernet standard length in the Ethernet data converted by the clock domain.
Preferably, a virtual channel sequence adjusting module is further included between the encoding module and the bit width converting module, and a delay module connected with the bit width converting module is further included behind the bit width converting module;
the coding module is further configured to distribute the coded data into a plurality of virtual channels and insert a preset flag value into each virtual channel when the target protocol rate is greater than a preset threshold value;
the virtual channel sequence adjusting module is used for adjusting the arrangement sequence of the virtual channels based on the virtual channel adjusting instruction;
the bit width conversion module is also used for converting a plurality of virtual channels into a preset number of actual physical channels;
the delay module is used for carrying out delay adjustment on the actual physical channels with the preset number;
the preset mark value corresponds to the target protocol rate, and the number of data channels of the external user netlist is a preset number.
Preferably, the encoding module is further configured to calculate a check value of each virtual channel, so as to detect whether an error exists when the encoded data is distributed into a plurality of virtual channels.
Preferably, the system further comprises a data conversion module, a decoding module and a sending control module, wherein the data conversion module is connected with the MII interface conversion module through the decoding module, and the sending control module is connected between the data receiving module and the MII interface conversion module;
the data conversion module is used for converting the data bit width of the test result output by the external user netlist into a preset data bit width;
the decoding module is used for descrambling and decoding the test result data after bit width conversion to obtain decoded data;
the MII interface conversion module is also used for converting the working protocol rate of the decoded data into an original protocol rate to obtain conversion data to be detected;
the sending control module is used for converting the FPGA slow clock domain of the conversion data to be detected into an Ethernet clock domain and storing the conversion data to be detected after the clock domain conversion into the data cache unit;
the data receiving module is also used for transmitting the to-be-detected conversion data to the external Ethernet test instrument;
the original protocol rate is the working protocol rate of the data output by the external Ethernet test instrument.
Preferably, the data conversion module is further configured to convert a preset number of actual physical channels into a plurality of virtual channels;
the decoding module is further used for aligning all virtual channels based on a preset mark value, adjusting all virtual channels to be in a correct sequence, and finally converging data in all virtual channels into test result data;
the number of the data channels of the external user netlist is a preset number.
Preferably, when the receiving control module monitors that the data stored in the data buffer unit reaches a storage threshold, the receiving control module sends a pause frame enabling signal to the sending control module, and the sending control module sends a pause frame signal to the external ethernet test instrument through the data receiving module so as to avoid data overflow in the data buffer unit.
Preferably, when the receiving control module monitors that the data stored in the data caching unit reaches a storage threshold, the receiving control module performs packet loss operation.
In order to solve the technical problem, the invention also provides a data transmission method of the Ethernet speed reducer for the FPGA prototype verification, which comprises the following steps:
the data receiving module of the Ethernet speed reducer for the FPGA prototype verification receives Ethernet data output by an external Ethernet test instrument;
the receiving control module converts the clock domain of the Ethernet data into an FPGA slow clock domain, stores the Ethernet data converted by the clock domain into the data caching unit, and monitors the data storage state of the data caching unit in real time;
the MII interface conversion module reads the Ethernet data converted by the clock domain from the data cache unit, converts the working protocol rate of the Ethernet data converted by the clock domain into a target protocol rate, acquires the Ethernet conversion data and transmits the Ethernet conversion data to the coding module;
the encoding module encodes and scrambles the Ethernet converted data to obtain encoded data, the bit width conversion module converts the bit width of the encoded data into a preset interface bit width, and the encoded data after the bit width conversion is transmitted to an external user netlist;
the preset interface bit width is the data interface bit width of an external user netlist, and the target protocol rate is the working protocol rate of test data required by the external user netlist.
In order to solve the technical problem, the invention also provides a data transmission method of the Ethernet speed reducer for the FPGA prototype verification, which comprises the following steps:
the data conversion module of the Ethernet speed reducer for the FPGA prototype verification converts the data bit width of the test result output by the external user netlist into the Ethernet data bit width, and realizes the data synchronization of the test result data;
the decoding module descrambles and decodes the bit-width converted test result data to obtain decoded data, and sends the decoded data to the MII interface conversion module;
the MII interface conversion module converts the working protocol rate of the decoded data into an original protocol rate to obtain conversion data to be detected;
the sending control module converts the FPGA slow clock domain of the to-be-converted data into an Ethernet clock domain, and stores the to-be-converted data converted by the clock domain into a data cache unit;
the data receiving module reads the conversion data to be tested after clock domain conversion from the storage unit and transmits the conversion data to be tested after clock domain conversion to an external Ethernet test instrument;
the original protocol rate is the working protocol rate of the data output by the external Ethernet test instrument.
One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:
the Ethernet speed reducer for the FPGA prototype verification provided by the embodiment of the invention realizes clock domain conversion of the Ethernet data and the data between the FPGA prototype verification platforms through the receiving control module and the sending control module; the MII interface conversion module provides support and conversion for a plurality of Ethernet protocols; the standard bit width of the interface of the bit width conversion module and the data conversion module supports the conversion from 10bit to 64 bit; aiming at the condition that the working protocol rate of test data required by an external user netlist is higher than a preset threshold value, different virtual channel arrangements and the deflection sizes among virtual channels are configured online, and a real Ethernet environment is simulated; the connection problem of the FPGA verification tool with low clock frequency and the real Ethernet test tool is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of an Ethernet speed reducer for FPGA prototype verification according to an embodiment of the invention;
fig. 2 is a flow chart of a data transmission method of an ethernet speed reducer based on FPGA prototype verification according to an embodiment of the present invention;
fig. 3 is a flow chart of a data transmission method of an ethernet speed reducer based on FPGA prototype verification according to an embodiment of the present invention.
Detailed Description
The following will describe embodiments of the present invention in detail with reference to the drawings and examples, thereby solving the technical problems by applying technical means to the present invention, and realizing the technical effects can be fully understood and implemented accordingly. It should be noted that, as long as no conflict is formed, each embodiment of the present invention and each feature of each embodiment may be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.
Example 1
In order to solve the technical problems in the prior art, the embodiment of the invention provides an Ethernet speed reducer for FPGA prototype verification.
In the process of FPGA prototype verification, an external user netlist is a verification subject of an FPGA prototype verification platform and is usually transmitted to the interior of the FPGA prototype verification platform; the external Ethernet test instrument is used for providing test data for the external user netlist and verifying the correctness of the output data of the external user netlist.
FIG. 1 is a schematic diagram of an Ethernet speed reducer for FPGA prototype verification according to an embodiment of the invention; referring to fig. 1, the ethernet speed reducer for FPGA prototype verification according to the embodiment of the present invention includes a data receiving module, a receiving control module, an MII interface conversion module, an encoding module, a bit width conversion module, a data conversion module, a decoding module, and a transmitting control module. The data receiving module, the receiving control module, the MII interface conversion module, the coding module and the bit width conversion module are sequentially connected to form a data transmission channel for the external Ethernet test instrument to send test data to an external user netlist in the FPGA prototype verification platform. The data conversion module, the decoding module, the MII interface conversion module, the sending control module and the data receiving module are sequentially connected to form a data transmission channel for sending test result data to an external Ethernet test instrument by an external user netlist (namely DUT).
Further, the data receiving module is connected with the PHY chip, and the PHY chip is connected with an external Ethernet testing instrument through a network cable; the data receiving module is mainly used for receiving the Ethernet data output by the external Ethernet testing instrument through the PHY chip. The data receiving module is also used for transmitting the to-be-detected conversion data in the data caching unit to an external Ethernet testing instrument. Further, the data receiving module can be set to be a Sgmii interface module or a XAUI interface module based on the working protocol rate corresponding to the output data of the external Ethernet test instrument, and the external interface packaged by the data receiving module is in a GMII interface format or an XGMII interface format.
The receiving control module is mainly used for converting the clock domain of the Ethernet data into the FPGA slow clock domain, storing the Ethernet data converted by the clock domain into the built-in data caching unit, and monitoring the data storage state of the data caching unit in real time. Because the Ethernet data transmission rate output by the external Ethernet test instrument is higher than the data transmission rate of the FPGA prototype verification platform, the processing rate of the FPGA prototype verification platform on the data is necessarily slower than the Ethernet data transmission rate, and the normal transmission necessarily leads to the overflow of the data in the data buffer unit. Therefore, when the receiving control module monitors that the data stored in the data caching unit reaches the storage threshold value, a pause frame enabling signal can be sent to the sending control module, and the sending control module sends the pause frame signal to an external Ethernet test instrument through the data receiving module to control the flow, so that the data in the data caching unit is prevented from overflowing.
When the receiving control module monitors that the data stored in the data caching unit reaches the storage threshold value, the receiving control module can also directly perform packet loss operation, and the receiving control module performs packet loss operation and does not have great influence on the verification result of the FPGA prototype verification platform due to huge Ethernet data quantity and faster data transmission rate.
In order to acquire the information of the data packet in the Ethernet data and ensure the accuracy of the data packet in the Ethernet data, the Ethernet speed reducer for the FPGA prototype verification can be further provided with a connection detection module after receiving the control module. The detection module is mainly used for carrying out packet counting statistics, packet length detection, CRC (cyclic redundancy check) and MAC (media access control) address extraction functions after clock domain conversion. Further counting and counting the total number of the Ethernet packets input to the FPGA prototype verification platform by an external Ethernet testing instrument; the packet length detection is mainly used for recording Ethernet packets which are input to the FPGA prototype verification platform by an external Ethernet test instrument and do not accord with the Ethernet standard length; the CRC mainly records error packets input to the FPGA prototype verification platform by an external Ethernet testing instrument; the MAC address extraction function is mainly used for completing the MAC address latching of the external Ethernet test instrument so as to be changed for other modules to use.
It should be noted that, when the data receiving module sends a pause frame signal to the external ethernet testing instrument and the data receiving module reads the converted data to be tested from the data buffer unit and transmits the converted data to the external ethernet testing instrument, the data receiving module is realized based on the stored MAC address.
The MII interface conversion module is used for realizing data conversion among different MII interfaces. The MII interface conversion module is used for converting the working protocol rate of the Ethernet data converted by the clock domain into a target protocol rate and obtaining the Ethernet conversion data; and the method is also used for converting the working protocol rate of the decoded data into the original protocol rate and obtaining the converted data to be detected. The target protocol rate is the working protocol rate of the test data required by the external user netlist, namely the external Ethernet test instrument sends the Ethernet data based on the test requirement of the external user netlist, and the MII interface conversion module is used for converting the working protocol rate of the Ethernet data into the protocol rate required by the external user netlist based on the test requirement in the data transmission process. The original protocol rate is the working protocol rate of the data output by the external Ethernet test instrument, namely, the external user netlist sends the test result data to the Ethernet test instrument for testing, and the MII interface conversion module is used for converting the working protocol rate of the test result data into the protocol rate which can be processed by the Ethernet test instrument in the data transmission process. The MII interface conversion module is internally packaged with a plurality of MII (Media Independent Interface) interface formats, including an XGMII standard package, a CGMII standard package and the like. The XGMII standard package is used for realizing the test of the user on the 10Gbps Ethernet data, and the CGMII standard package is used for realizing the test of the user on the 100Gbps Ethernet data. The MII interface conversion module may enable a corresponding MII interface format based on user requirements. The encoding module is used for carrying out 64B/66B encoding on the Ethernet converted data and recording encoding error values; and meanwhile, scrambling the encoded Ethernet converted data to obtain encoded data with the encoded scrambling. Meanwhile, the coding module is used for distributing coded data into a plurality of virtual channels according to the protocol when the target protocol rate is greater than a preset threshold value; inserting preset mark values (i.e. marker values) at corresponding positions in all virtual channels according to a protocol for marking; and meanwhile, check values are calculated at corresponding positions in all virtual channels so as to detect whether errors exist when the coded data are distributed into a plurality of virtual channels, and if the errors exist or reach a certain threshold value, an alarm indication can be set. Preferably, the preset threshold is 25G. The preset flag value corresponds to the target protocol rate, i.e., different target protocol rates correspond to different preset flag values.
The bit width conversion module is mainly used for converting the bit width of the coded data into the bit width of a preset interface. The preset interface bit width is the data interface bit width of the external user netlist. The bit width conversion module of the embodiment can provide a 10bit to 64bit interface and can realize corresponding conversion of the bit width of the interface required by a user. When the target protocol rate is greater than a preset threshold value, the bit width conversion module is also used for converting the virtual channels into actual physical channels with preset numbers; the data channel conversion is realized, and the number of the data channels of the external user netlist is a preset number. For example: if the user needs to test 10 actual physical channels, the number of 100G virtual channels is 20 according to the protocol, and the bit width conversion module needs to aggregate 20 data of the channels to 10 actual physical channel data.
The Ethernet speed reducer for the FPGA prototype verification further comprises a virtual channel sequence adjustment module connected between the coding module and the bit width conversion module, and a delay module connected with the bit width conversion module. The virtual channel sequence adjustment module and the delay module are operated when the target protocol rate is greater than a preset threshold.
The virtual channel sequence adjustment module can be connected with the external processor, and a worker sends a virtual channel adjustment instruction to the virtual channel sequence adjustment module based on the external processor; meanwhile, the virtual channel adjustment instruction can also be a preset instruction. The virtual channel sequence adjusting module adjusts the arrangement sequence of a plurality of virtual channels based on the virtual channel adjusting instruction so as to simulate different Ethernet hardware scenes.
Meanwhile, the delay module can also be connected with an external processor, and a worker sends a delay adjustment instruction to the delay module based on the external processor; meanwhile, the delay adjustment instruction can also be a preset instruction. The delay module carries out delay adjustment on a preset number of actual physical channels based on the received delay adjustment instruction so as to manufacture the channel dyssynchrony among the actual physical channels, thereby realizing the simulation of different Ethernet delay scenes. Preferably, the delay maximum setting can be set for each channel separately, to test whether the test is successful in the case of the delay maximum. When the target protocol rate is not greater than the preset threshold, the coded data after the external width conversion is the test data required by the external user netlist, and when the target protocol rate is greater than the preset threshold, the data output by the actual physical channels with the preset number after delay adjustment is the test data required by the external user netlist.
The data conversion module is mainly used for converting the data bit width of the test result output by the external user netlist into the preset data bit width. For example, the data bit width of the output data of the external user netlist is 10 bits, the data conversion module can convert the bit width of the output data into 32 bits or 64 bits when receiving test result data, then convert the 32 bits or 64 bits into preset data bit width, and the preset data bit width is 66 bits and 128 bits, so that data alignment and synchronization are realized. Meanwhile, when the working protocol rate of the test result data output by the external user netlist is larger than a preset threshold, the external user netlist is actually data transmission realized through a preset number of actual physical channels and a data conversion module, and at the moment, the data conversion module also needs to realize channel conversion, namely, the preset number of actual physical channels are converted into a plurality of virtual channels according to the protocol.
The decoding module is mainly used for descrambling and decoding the test result data after the bit width conversion so as to obtain decoded data. Further, after descrambling the test result data, the data is subjected to 64B/66B decoding, and the decoding error value is recorded. When the working protocol rate of the test result data output by the external user netlist is greater than a preset threshold, the decoding module is further used for identifying preset mark values in all channels to be tested, and performing alignment and sequential adjustment operations on all virtual channels based on the preset mark values, so that all virtual channels are restored to the correct arrangement sequence based on the preset mark values, and finally, the data in all virtual channels are converged into single test result data.
The sending control module is mainly used for realizing clock domain conversion of the FPGA slow clock domain and the Ethernet clock domain of the conversion data to be detected, and storing the conversion data to be detected after the clock domain conversion into the data caching unit. And the receiving control module is also used for receiving a pause frame enabling signal sent by the receiving control module when monitoring that the stored data in the data caching unit reaches a storage threshold value, sending a pause frame signal to an external Ethernet test instrument through the data receiving module, and controlling the flow so as to avoid data overflow in the data caching unit.
According to the Ethernet speed reducer for the FPGA prototype verification, provided by the embodiment of the invention, clock domain conversion of Ethernet data and data between the FPGA prototype verification platforms is realized through the receiving control module and the sending control module; the MII interface conversion module provides support and conversion for a plurality of Ethernet protocols; the standard bit width of the interface of the bit width conversion module and the data conversion module supports the conversion from 10bit to 64 bit; aiming at the condition that the working protocol rate of test data required by an external user netlist is higher than a preset threshold value, different virtual channel arrangements and the deflection sizes among virtual channels are configured online, and a real Ethernet environment is simulated; the connection problem of the FPGA verification tool with low clock frequency and the real Ethernet test tool is solved.
Example two
In order to solve the technical problems in the prior art, the embodiment of the invention provides a data transmission method of an Ethernet speed reducer for FPGA prototype verification.
The specific structure of the ethernet speed reducer for prototype verification of the FPGA adopted in the present embodiment is described in the first embodiment, and will not be described herein. And the module units and the like adopted in the embodiment are all of the Ethernet speed reducers for the prototype verification of the FPGA.
Fig. 2 is a flow chart of a data transmission method of an ethernet speed reducer based on FPGA prototype verification according to an embodiment of the present invention; referring to fig. 2, the data transmission method of the ethernet speed reducer based on the FPGA prototype verification according to the embodiment of the present invention includes the following steps.
Step S201, a data receiving module of the FPGA prototype-verified Ethernet speed reducer receives Ethernet data output by an external Ethernet test instrument through an external phy chip.
Step S202, a receiving control module in the FPGA prototype-verified Ethernet speed reducer performs clock domain conversion on Ethernet data, stores the Ethernet data converted by the clock domain into a data caching unit, and monitors the data storage state of the data caching unit in real time.
Specifically, a receiving control module in the Ethernet speed reducer for the prototype verification of the FPGA converts a clock domain of Ethernet data into an FPGA slow clock domain, stores the Ethernet data converted by the clock domain into a data caching unit, and simultaneously monitors the data storage state of the data caching unit in real time. When the receiving control module monitors that the data stored in the data caching unit reaches a storage threshold value, a pause frame enabling signal is sent to the sending control module, and the sending control module sends the pause frame signal to an external Ethernet test instrument through the data receiving module to control the flow, so that data overflow in the data caching unit is avoided.
Or when the receiving control module monitors that the data stored in the data caching unit reaches the storage threshold, the receiving control module directly performs packet loss operation until the data stored in the data caching unit is lower than the storage threshold.
In step S203, the MII interface conversion module reads the ethernet data converted by the clock domain from the data buffer unit, and converts the working protocol rate converted by the ethernet data converted by the clock domain into the target protocol rate by adopting the corresponding MII interface format based on the transmission rate of the original ethernet data, so as to obtain ethernet converted data and transmit the ethernet converted data to the encoding module. The target protocol rate is the working protocol rate of the test data required by the external user netlist.
In step S204, the encoding module encodes and scrambles the ethernet converted data to obtain encoded data, and the bit width conversion module converts the bit width of the encoded data into a preset interface bit width and transmits the encoded data after the bit width conversion to the external user netlist.
Specifically, the encoding module encodes and scrambles the ethernet converted data to obtain encoded data. When the target protocol rate is not greater than the preset threshold, the encoding module can directly transmit the encoded data to the bit width conversion module, and the bit width conversion module can convert the bit width of the encoded data into the bit width of the preset interface, so that the encoded data can be transmitted to an external user netlist.
When the target protocol rate is greater than a preset threshold, the coding module distributes coded data into a plurality of virtual channels according to the protocol; and inserting preset mark values at corresponding positions in all virtual channels according to the protocol, and calculating check values at corresponding positions in all virtual channels.
The virtual channel sequence adjusting module adjusts the arrangement sequence of a plurality of virtual channels based on the virtual channel adjusting instruction so as to simulate different Ethernet hardware scenes. And the bit width conversion module firstly converts the virtual channels into the actual physical channels with the preset number, and then realizes the bit width conversion of the data in the actual physical channels. And finally, the delay module carries out delay adjustment on the actual physical channels with the preset number based on the delay adjustment instruction, and sends the data to an external user netlist.
The data transmission method of the Ethernet speed reducer for the FPGA prototype verification of the embodiment provides a data transmission channel for an external Ethernet test instrument to send data to an external user netlist in an FPGA prototype verification platform, and realizes that the Ethernet data output by the external Ethernet test instrument is sent to the external user netlist for the FPGA prototype verification platform to realize the test of the external user netlist.
The data transmission method of the Ethernet speed reducer based on the FPGA prototype verification provided by the embodiment of the invention realizes the clock domain conversion of the Ethernet data to the data transmission between the FPGA prototype verification platforms; support and conversion of multiple Ethernet protocols; aiming at the condition that the working protocol rate of test data required by an external user netlist is higher than a preset threshold value, different virtual channel arrangements and the deflection sizes among virtual channels are configured online, and a real Ethernet environment is simulated; the connection problem of the FPGA verification tool with low clock frequency and the real Ethernet test tool is solved.
Example III
In order to solve the technical problems in the prior art, the embodiment of the invention provides a data transmission method of an Ethernet speed reducer for FPGA prototype verification.
The specific structure of the ethernet speed reducer for prototype verification of the FPGA adopted in the present embodiment is described in the first embodiment, and will not be described herein. And the module units and the like adopted in the embodiment are all of the Ethernet speed reducers for the prototype verification of the FPGA.
Fig. 3 is a flow chart of a data transmission method of an ethernet speed reducer based on FPGA prototype verification according to an embodiment of the present invention; referring to fig. 3, the data transmission method of the ethernet speed reducer based on the FPGA prototype verification according to the embodiment of the present invention includes the following steps.
Step S301, a data conversion module of the Ethernet speed reducer for the FPGA prototype verification converts the data bit width of the test result output by the external user netlist into a preset data bit width.
It should be noted that, when the working protocol rate of the test result data output by the external user netlist is greater than the preset threshold, the external user netlist is actually data transmission realized through the preset number of actual physical channels and the data conversion module, and at this time, the data conversion module also needs to realize channel conversion, that is, converts the preset number of actual physical channels into multiple virtual channels according to the protocol
In step S302, the decoding module descrambles and decodes the test result data after bit width conversion to obtain decoded data, and sends the decoded data to the MII interface conversion module.
Specifically, after descrambling the test result data, the data is subjected to 64B/66B decoding while recording the decoding error value. And when the working protocol rate of the test result data output by the external user netlist is greater than a preset threshold, the decoding module is required to identify preset mark values in all channels, and perform alignment and sequential adjustment operations on all virtual channels based on the preset mark values, so that all virtual channels are restored to a correct arrangement sequence based on the preset mark values, and finally the data in all virtual channels are converged into a single test result data. And sends the decoded data to the MII interface conversion module.
In step S303, the MII interface conversion module converts the working protocol rate converted from the decoded data into the original protocol rate, and obtains the converted data to be tested. The original protocol rate is the working protocol rate of the data output by the external Ethernet test instrument.
Step S304, the sending control module converts the FPGA slow clock domain of the conversion data to be tested into the Ethernet clock domain, and stores the conversion data to be tested after the clock domain conversion into the data buffer unit.
In step S305, the data receiving module reads the converted data to be tested after the clock domain conversion from the storage unit, and transmits the converted data to be tested after the clock domain conversion to the external ethernet testing instrument.
The data transmission method of the Ethernet speed reducer for the FPGA prototype verification in the embodiment provides a data transmission channel for transmitting data from an external user netlist to an external Ethernet test instrument in the FPGA prototype verification platform, and can be used for verifying the correctness of the output data of the external user netlist.
The data transmission method of the Ethernet speed reducer based on the FPGA prototype verification provided by the embodiment of the invention realizes the clock domain conversion of the FPGA prototype verification platform to the data transmission between Ethernet data; support and conversion of multiple Ethernet protocols; the connection problem of the FPGA verification tool with low clock frequency and the real Ethernet test tool is solved.
Although the embodiments of the present invention are disclosed above, the embodiments are only used for the convenience of understanding the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the present disclosure as defined by the appended claims.
Claims (9)
1. An ethernet speed reducer for FPGA prototype verification, comprising:
the data receiving module is used for receiving the Ethernet data output by the external Ethernet test instrument;
the receiving control module is used for converting the clock domain of the Ethernet data into an FPGA slow clock domain, storing the Ethernet data converted by the clock domain into the data caching unit, and monitoring the data storage state of the data caching unit in real time;
the MII interface conversion module is used for converting the working protocol rate of the Ethernet data converted by the clock domain into a target protocol rate and obtaining the Ethernet conversion data;
the encoding module is used for encoding and scrambling the Ethernet converted data to obtain encoded data;
the bit width conversion module is used for converting the bit width of the coded data into a preset interface bit width;
the preset interface bit width is the data interface bit width of an external user netlist, and the target protocol rate is the working protocol rate of test data required by the external user netlist;
the virtual channel sequence adjusting module is further arranged between the coding module and the bit width converting module, and the delay module connected with the bit width converting module is further arranged behind the bit width converting module;
the coding module is further configured to distribute the coded data into a plurality of virtual channels and insert a preset flag value into each virtual channel when the target protocol rate is greater than a preset threshold value;
the virtual channel sequence adjusting module is used for adjusting the arrangement sequence of the virtual channels based on the virtual channel adjusting instruction;
the bit width conversion module is also used for converting a plurality of virtual channels into a preset number of actual physical channels;
the delay module is used for carrying out delay adjustment on the actual physical channels with the preset number;
the preset mark value corresponds to the target protocol rate, and the number of data channels of the external user netlist is a preset number.
2. The speed reducer of claim 1, further comprising a detection module between the receive control module and the MII interface conversion module:
the detection module is used for counting the number of Ethernet packets in the Ethernet data converted by the clock domain and recording the Ethernet packets and error packets which do not accord with the Ethernet standard length in the Ethernet data converted by the clock domain.
3. The speed reducer of claim 1, wherein the encoding module is further configured to calculate a check value for each of the virtual channels to detect whether there is an error in distribution of the encoded data into the plurality of virtual channels.
4. The speed reducer of claim 1, further comprising a data conversion module, a decoding module, and a transmission control module, wherein the data conversion module is connected with the MII interface conversion module through the decoding module, and the transmission control module is connected between the data receiving module and the MII interface conversion module;
the data conversion module is used for converting the data bit width of the test result output by the external user netlist into a preset data bit width;
the decoding module is used for descrambling and decoding the test result data after bit width conversion to obtain decoded data;
the MII interface conversion module is also used for converting the working protocol rate of the decoded data into an original protocol rate to obtain conversion data to be detected;
the sending control module is used for converting the FPGA slow clock domain of the conversion data to be detected into an Ethernet clock domain and storing the conversion data to be detected after the clock domain conversion into the data cache unit;
the data receiving module is also used for transmitting the to-be-detected conversion data to the external Ethernet test instrument;
the original protocol rate is the working protocol rate of the data output by the external Ethernet test instrument.
5. The speed reducer of claim 4, wherein the data conversion module is further configured to convert a preset number of actual physical channels into a plurality of virtual channels;
the decoding module is further used for aligning all virtual channels based on a preset mark value, adjusting all virtual channels to be in a correct sequence, and finally converging data in all virtual channels into test result data;
the number of the data channels of the external user netlist is a preset number.
6. The speed reducer of claim 4, wherein when the receiving control module monitors that the data stored in the data buffer unit reaches a storage threshold, the receiving control module sends a pause frame enable signal to the sending control module, and the sending control module sends a pause frame signal to the external ethernet test instrument through the data receiving module to avoid data overflow in the data buffer unit.
7. The speed reducer of claim 4, wherein the receiving control module performs a packet loss operation when the receiving control module monitors that the data stored in the data buffer unit reaches a storage threshold.
8. A data transmission method of an ethernet speed reducer based on FPGA prototype verification according to any one of claims 1 to 7, comprising:
the data receiving module of the Ethernet speed reducer for the FPGA prototype verification receives Ethernet data output by an external Ethernet test instrument;
the receiving control module converts the clock domain of the Ethernet data into an FPGA slow clock domain, stores the Ethernet data converted by the clock domain into the data caching unit, and monitors the data storage state of the data caching unit in real time;
the MII interface conversion module reads the Ethernet data converted by the clock domain from the data cache unit, converts the working protocol rate of the Ethernet data converted by the clock domain into a target protocol rate, acquires the Ethernet conversion data and transmits the Ethernet conversion data to the coding module;
the encoding module encodes and scrambles the Ethernet converted data to obtain encoded data, the bit width conversion module converts the bit width of the encoded data into a preset interface bit width, and the encoded data after the bit width conversion is transmitted to an external user netlist;
the preset interface bit width is the data interface bit width of an external user netlist, and the target protocol rate is the working protocol rate of test data required by the external user netlist.
9. A data transmission method of an ethernet speed reducer based on FPGA prototype verification according to any one of claims 1 to 7, comprising:
the data conversion module of the Ethernet speed reducer for the FPGA prototype verification converts the data bit width of the test result output by the external user netlist into a preset data bit width;
the decoding module descrambles and decodes the bit-width converted test result data to obtain decoded data, and sends the decoded data to the MII interface conversion module;
the MII interface conversion module converts the working protocol rate of the decoded data into an original protocol rate to obtain conversion data to be detected;
the sending control module converts the FPGA slow clock domain of the to-be-converted data into an Ethernet clock domain, and stores the to-be-converted data converted by the clock domain into a data cache unit;
the data receiving module reads the conversion data to be tested after clock domain conversion from the storage unit and transmits the conversion data to be tested after clock domain conversion to an external Ethernet test instrument;
the original protocol rate is the working protocol rate of the data output by the external Ethernet test instrument.
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