CN116867314A

CN116867314A - Display panel manufacturing method, display panel and display terminal

Info

Publication number: CN116867314A
Application number: CN202311127122.2A
Authority: CN
Inventors: 曹尚操; 谢俊烽
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2023-09-04
Filing date: 2023-09-04
Publication date: 2023-10-10
Anticipated expiration: 2043-09-04
Also published as: CN116867314B

Abstract

The embodiment of the application discloses a manufacturing method of a display panel with better display effect, which comprises the following steps: providing a first substrate, sequentially forming a plurality of pixel units and a planarization layer covering the pixel units on the surface of the first substrate, wherein each pixel unit comprises a first electrode, an organic material layer and a second electrode which are sequentially stacked, the pixel units are separated from each other through the planarization layer, and the second electrode and the first electrode are used for driving the organic material layer to emit light; forming an opening in the planarization layer corresponding to the position of the second electrode, wherein part of the second electrode is exposed from the opening; and forming a third electrode on the surface of the planarization layer and the surface of the opening, wherein the third electrode is connected with the second electrode at the position of the opening. The embodiment of the application also provides a display panel manufactured by the method and a display terminal comprising the display panel.

Description

Display panel manufacturing method, display panel and display terminal

Technical Field

The present application relates to the field of display technologies, and in particular, to a display panel manufacturing method, a display panel, and a display terminal.

Background

The OLED display panel is widely used in various display products such as mobile phones, displays, televisions, etc. due to technical advantages such as self-luminescence, lightness, thinness, high contrast, etc. In the current OLED technology, each OLED pixel unit in an OLED display panel includes: a light transmissive first electrode (transparent electrode), an OLED organic material layer deposited on the first electrode, and a second electrode (metal electrode) located over the OLED medium. The transparent electrode serves as the anode layer of the device, and the metal electrode serves as the cathode of the device. And applying voltages to the transparent electrode and the metal electrode respectively to form an electric field so that the OLED pixel unit can be used as a light emitting device to emit light.

When the evaporation forms the organic material layer, a high-definition metal mask (FMM) is needed, the FMM is utilized to form a pixel light-emitting unit through evaporation, when the evaporation is carried out, the FMM needs high alignment precision, the success rate is relatively low in practical operation, so that the production efficiency is reduced, and the OLED display panel formed through the manufacturing is easy to cause crosstalk of electron flow between adjacent pixels when image display is carried out, so that chromatic aberration occurs, and meanwhile, the FMM also limits the resolution and brightness of the OLED display panel under the large size and the same size, so that the display effect of the OLED display panel is poor.

Disclosure of Invention

In view of the above-mentioned shortcomings, the present application provides a method for manufacturing a display panel with good display effect, and a display panel and a display terminal manufactured by the method.

In a first aspect, the present application provides a method for manufacturing a display panel, including:

providing a first substrate, sequentially forming a plurality of pixel units and a planarization layer covering the pixel units on the surface of the first substrate, wherein each pixel unit comprises a first electrode, an organic material layer and a second electrode which are sequentially stacked, the pixel units pass through the planarization layer, and the second electrode and the first electrode are used for driving the organic material layer to emit light;

Forming an opening in the planarization layer corresponding to the position of the second electrode, wherein part of the second electrode is exposed from the opening;

and forming a third electrode on the surface of the planarization layer and the surface of the opening, wherein the third electrode is connected with the second electrode at the position of the opening.

In an embodiment, sequentially forming a plurality of pixel units and a planarization layer covering the pixel units on the surface of the first substrate includes:

forming a first conductive layer on the surface of the first substrate, and patterning the first conductive layer through a photoetching process to form a plurality of first electrodes with preset intervals;

sequentially laminating and manufacturing an organic material layer, a second conductive layer and a first insulating layer on the surface of the first electrode;

forming a first opening in the first insulating layer, the second conductive layer and the organic material layer at a position corresponding to a spacing region between the two adjacent first electrodes, wherein the first substrate is exposed from the first opening, and the second conductive layer forms a plurality of second electrodes with preset spacing distances through the first opening;

and forming a second insulating layer on the surface of the first insulating layer, wherein the second insulating layer also fills the first opening, and the first insulating layer and the second insulating layer form the planarization layer.

In an embodiment, forming the first opening includes:

performing a photoetching process on the first insulating layer to form a first sub-opening;

and continuing dry etching the second conductive layer and the organic material layer corresponding to the first sub-opening to form the first opening.

forming a first conductive layer, an organic material layer, a second conductive layer and a first insulating layer on the surface of the first substrate;

patterning the first insulating layer, the second conductive layer, the organic material layer and the first conductive layer through a mask and forming a first opening, wherein the first substrate is exposed from the first opening, the first conductive layer forms a plurality of first electrodes with preset intervals through the first opening, and the second conductive layer forms a plurality of second electrodes with preset intervals through the first opening;

In an embodiment, forming the first opening includes:

performing a photoetching process on the first insulating layer to form a first sub-opening, wherein the second electrode is exposed from the first sub-opening;

continuing dry etching the second conductive layer and the organic material layer corresponding to the first sub-opening to form a second sub-opening, wherein the first conductive layer is exposed from the second sub-opening;

and continuing to perform wet etching on the first conductive layer corresponding to the second sub-opening to form the first opening.

In one embodiment, forming a third electrode on the surface of the planarization layer and the opening surface includes:

forming a second opening in the second insulating layer and the first insulating layer corresponding to the position of the second electrode, wherein part of the second electrode is exposed from the second opening;

and forming the third electrode on the surface of the second insulating layer and the surface of the second opening.

In one embodiment, the third electrode is further formed by:

and a packaging layer and a photoresist layer are sequentially formed on the surface of the third electrode, the second electrode and the first electrode are matched to drive the organic material layer to emit white light, the photoresist layer comprises a plurality of color filtering units with different colors, and the color filtering units are used for filtering the white light to emit light with different colors.

forming a first conductive layer on the surface of the first substrate, wherein the first conductive layer comprises a plurality of first sub-electrodes, second sub-electrodes and third sub-electrodes which are spaced at preset distances;

sequentially manufacturing a first sub-organic material layer, a second conductive layer and a first insulating layer on the surface of the first conductive layer;

etching the first sub-organic material layer, the second conductive layer and the first insulating layer corresponding to the second sub-electrode and the third sub-electrode, so that the second conductive layer forms a plurality of second electrodes with preset intervals, the first insulating layer is divided into a plurality of first sub-insulating layers, and the first sub-electrode, the first sub-organic material layer and the second electrode form a first sub-pixel unit;

forming a second sub-organic material layer, a second electrode and a second sub-insulating layer on the surface of the second sub-electrode, wherein the second sub-electrode, the second sub-organic material layer and the second electrode form a second sub-pixel unit;

forming a third sub-organic material layer, a second electrode and a third sub-insulating layer on the surface of the third sub-electrode, wherein the third sub-electrode, the third sub-organic material layer and the second electrode form a third sub-pixel unit;

And forming the planarization layer on the first substrate surfaces among the first sub-insulating layer, the second sub-insulating layer, the third sub-insulating layer, the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit.

forming a plurality of openings corresponding to the positions of the planarization layer, the first sub-insulating layer, the second sub-insulating layer and the third sub-insulating layer, where each second electrode is located, and exposing the second electrodes from the openings;

and forming the third electrode on the surface of the planarization layer and the surface of the opening.

In an embodiment, an encapsulation layer is formed on the surface of the third electrode, the first sub-electrode cooperates with the second electrode to drive the first sub-organic material layer to emit light of a first color, the second sub-electrode cooperates with the second electrode to drive the second sub-organic material layer to emit light of a second color, and the third sub-electrode cooperates with the second electrode to drive the third sub-organic material layer to emit light of a third color.

In a second aspect, there is provided a display panel formed by the foregoing method, comprising:

the organic light emitting diode comprises a first substrate, wherein a plurality of pixel units with preset intervals are arranged on the surface of the first substrate, each pixel unit comprises a first electrode, an organic material layer and a second electrode which are arranged in a stacked mode, and the second electrode is matched with the first electrode and used for driving the organic material layer to emit light;

the planarization layer covers the first substrate surface and the second electrode surface between the pixel units, the pixel units pass through the planarization layer and are separated from each other, the planarization layer comprises an opening at a position corresponding to the second electrode, a third electrode is arranged on the surface of the planarization layer and the surface of the opening, and the third electrode is connected with the second electrode at the position of the opening.

In an embodiment, the planarization layer includes a first insulating layer and a second insulating layer, the first insulating layer covers the second electrode, the first insulating layer and the organic material layer are provided with a first opening in a region corresponding to between the second electrode and the first electrode, and the second insulating layer fills the opening.

In one embodiment, the first electrode includes a plurality of first sub-electrodes, second sub-electrodes and third sub-electrodes spaced apart by a predetermined distance;

the surface of the first sub-electrode comprises a first sub-organic material layer, a second electrode and a first sub-insulating layer and forms a first sub-pixel unit;

the surface of the second sub-electrode comprises a second sub-organic material layer, a second electrode and a second sub-insulating layer and forms a second sub-pixel unit;

the surface of the third sub-electrode comprises a third sub-organic material layer, a second electrode and a third sub-insulating layer and forms a third sub-pixel unit;

the first sub-pixel electrode, the second sub-pixel electrode and the third sub-pixel electrode are provided with a first opening therebetween, the planarization layer is filled in the first opening, the first sub-electrode and the second electrode are matched to drive the first sub-organic material layer to emit light rays of a first color, the second sub-electrode and the second electrode are matched to drive the second sub-organic material layer to emit light rays of a second color, and the third sub-electrode and the second electrode are matched to drive the third sub-organic material layer to emit light rays of a third color.

In a third aspect, a display terminal is provided, including the foregoing display panel, where the display panel further includes a data driving circuit, a scan driving circuit, and a plurality of pixel units arranged in an array, where the data driving circuit is connected to the plurality of pixel units through a plurality of data lines, the scan driving circuit is connected to the pixel units through a plurality of scan lines, and the scan driving circuit outputs a scan signal to the pixel units to control the pixel units to receive the data signal output by the data driving circuit, and the pixel units perform image display according to the data signal.

Compared with the prior art, the third electrode connected to the second electrode is arranged on the planarization layer, and the occupied area of the third electrode is large, so that the cross section area of the second electrode can be effectively increased through the third electrode, the integral impedance of the second electrode serving as the cathode in the pixel unit is effectively reduced, the impedance loss of the pixel unit in each different position can be effectively improved, and the uniformity of image display is ensured.

Further, the plurality of pixel units are separated from each other through the planarization layer, so that the first electrode and the organic material layer in the two adjacent pixel units are separated from each other, the light emitted by the adjacent pixel units is prevented from being crosstalked, meanwhile, the leakage or crosstalk of electron flow is prevented from occurring between the adjacent pixel electrodes, the color cast of a displayed image is prevented, and the brightness of characteristic display is effectively improved.

Further, when the second electrode is formed, the insulating layer and the second conductive layer are subjected to matching of a photoetching process and a dry etching process or a wet etching process through a photoetching process, so that the distance between the second electrodes can be finer, the distance between each pixel unit can be kept in a smaller range, the number of the pixel units in the display panel can be further increased, and a larger luminous area and higher brightness are maintained.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display terminal according to an embodiment of the present application;

FIG. 2 is a schematic plan layout of the display panel shown in FIG. 1;

FIG. 3 is a schematic diagram of a manufacturing process of the display panel shown in FIG. 2 according to a first embodiment of the present application;

FIG. 4 is a schematic side view of the display panel shown in FIG. 3 in a first step in the manufacturing process;

FIG. 5 is a schematic side view of a second step in the manufacturing process of the display panel shown in FIG. 3;

FIG. 6 is a schematic side view of a third step in the manufacturing process of the display panel shown in FIG. 3;

FIG. 7 is a schematic side view of a fourth step in the manufacturing process of the display panel shown in FIG. 3;

FIG. 8 is a schematic side view of a step one of the display panel shown in FIG. 3 according to a second embodiment of the present application;

FIG. 9 is a schematic side view of a second step in the manufacturing process of the display panel shown in FIG. 3 according to the second embodiment of the present application;

FIG. 10 is a schematic side view illustrating a third step in the manufacturing process of the display panel shown in FIG. 3 according to the second embodiment of the present application;

FIG. 11 is a schematic side view of a fourth step in the manufacturing process of the display panel shown in FIG. 3 according to the second embodiment of the present application;

FIG. 12 is a schematic diagram illustrating a manufacturing process of the display panel shown in FIG. 2 according to a third embodiment of the present application;

FIG. 13 is a schematic side view of the display panel shown in FIG. 12 in a first step in the manufacturing process;

FIG. 14 is a schematic side view of the display panel shown in FIG. 12 in a second step in the manufacturing process;

FIG. 15 is a schematic side view of a third step in the manufacturing process of the display panel shown in FIG. 12;

Fig. 16 is a schematic side view of a fourth step in the manufacturing process of the display panel shown in fig. 12.

Reference numerals illustrate:

display terminal-100, display panel-10, 30, power module-20, display area-10 a, m data lines-D1-Dm, n scan lines-G1-Gn, first direction-F1, second direction-F2, timing control circuit-11, data driving circuit-12, scan driving circuit-13, pixel unit-P, first Sub-pixel unit-PR, second Sub-pixel unit-PG, third Sub-pixel unit-PB, first substrate-Sub, first conductive layer-C1, second conductive layer-C2, first electrode-P1, first Sub-electrode-P11, second Sub-electrode-P12 the third Sub-electrode-P13, the first insulating layer-S1, the first Sub-insulating layer-S11, the second Sub-insulating layer-S12, the third Sub-insulating layer-S13, the second insulating layer-S2, the organic material layer-R, the first Sub-organic material layer-R1, the second Sub-organic material layer-R2, the third Sub-organic material layer-R3, the planarization layer-TD, the second electrode-P2, the third electrode-P3, the encapsulation layer-EN, the photoresist layer-PH, the first opening-H1, the first Sub-opening-H11, the second Sub-opening-H12, and the second opening-H2.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the application may be practiced. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., in the present application are merely referring to the directions of the attached drawings, and thus, directional terms are used for better, more clear explanation and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, the terms "comprises," "comprising," "includes," "including," or "having," when used in this specification, are intended to specify the presence of stated features, operations, elements, etc., but do not limit the presence of one or more other features, operations, elements, etc., but are not limited to other features, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the application, use of "may" means "one or more embodiments of the application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display terminal 100 according to a first embodiment of the present application. The display terminal 100 includes a display panel 10 and a power module 20, wherein the power module 20 is disposed on a back surface of the display panel 10, i.e. a non-display surface of the display panel 10. The power module 20 is used for providing driving voltage for image display of the display panel 10 to maintain the display panel 10 to perform image display.

Referring to fig. 2, fig. 2 is a schematic plan layout of the display panel 10 shown in fig. 1. As shown in fig. 2, the display area 10a of the display panel 10 includes a plurality of m×n pixel units P, m data lines D1-Dm and n scan lines G1-Gn, where m and n are natural numbers greater than 1.

The n scan lines G1 to Gn extend along a first direction F1 and are mutually insulated and arranged in parallel along a second direction F2, the m data lines D1 to Dm extend along the second direction F2 and are mutually insulated and arranged in parallel along the first direction F1, and the first direction F1 and the second direction F2 are mutually perpendicular.

The display terminal 100 further includes a timing control circuit 11 for driving the pixel units to display an image, a data driving circuit 12, and a scan driving circuit 13 provided in the display panel 10 corresponding to the non-display region of the display panel 10.

The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used for controlling the working timings of the data driving circuit 12 and the scan driving circuit 13, i.e. outputting corresponding timing control signals to the data driving circuit 12 to the scan driving circuit 13, so as to control when to output corresponding scan signals and data signals.

The Data driving circuit 12 is electrically connected to the m Data lines D1 to Dm, and is configured to transmit a Data signal (Data) for display to the plurality of pixel units P in the form of Data voltages through the m Data lines D1 to Dm.

The scan driving circuit 13 is electrically connected to the n scan lines G1 to Gn, and is configured to output a scan signal through the n scan lines G1 to Gn for controlling when the pixel unit P receives a data signal. The scan driving circuit 13 sequentially outputs scan signals from the n scan lines G1 to Gn in the position arrangement order from the scan lines G1, G2, … …, gn in the scan period.

Referring to fig. 3-7, fig. 3 is a schematic diagram illustrating a manufacturing process of the display panel 10 shown in fig. 2 according to the first embodiment of the application.

As shown in FIG. 3, the display panel 10 includes steps 1000-4000. Specifically:

referring to fig. 3 and 4, fig. 4 is a schematic side view of a side structure of a display panel in a first step in the manufacturing process of the display panel shown in fig. 3, in step 1000, a first substrate Sub is provided, a plurality of pixel units P with predetermined intervals and a planarization layer TD covering the pixel units P are formed on the surface of the first substrate Sub, and the pixel units P include a first electrode P1, an organic material layer R, and a second electrode P2. That is, one of the first electrodes P1, the organic material layer R, and one of the second electrodes P2 form one pixel unit P, and the second electrode P2 cooperates with the first electrode P1 to drive the organic material layer R to emit light.

In this embodiment, more specifically, step 1000 further includes:

in step A1, a plurality of first electrodes P1 spaced apart from each other by a predetermined distance are disposed on the surface of the first substrate Sub.

Specifically, as shown in fig. 4, the first substrate Sub may be made of transparent plastic, glass, or metal foil, and is used for the subsequent whole layer structure. The first substrate Sub has a driving circuit formed thereon for driving the pixel unit of the OLED, wherein the driving circuit includes electronic components such as a thin film transistor (Thin Film transistor TFT) and a capacitor.

In this embodiment, the first electrode P1 may be an N-type oxide semiconductor material, such as transparent Indium Tin Oxide (ITO). The first electrode P1 may be formed by patterning an ITO layer or a transparent metal layer on the first substrate Sub, and of course, the ITO layer or the transparent metal layer may be formed by magnetron sputtering, and then patterned by an etching lithography process (photo) through a Mask (Mask) including a pattern. In this embodiment, the first electrode P1 serves as an anode of the pixel unit. The photolithography process mainly includes steps of photoresist coating (PR coating), exposing (exposing), developing (developing), and yellow etching on a substrate, thereby forming a plurality of first electrodes P1 spaced a predetermined distance on the ITO layer.

Specific ways to pattern the first electrode P1 by a photolithography process include, for example:

and cleaning the raw material silicon wafer serving as the first substrate Sub to ensure the surface cleanliness. Cleaning may include washing with pure water and nitrogen purge drying in a water washer.

Particles are emitted from the raw materials (through processes of evaporation, sublimation, sputtering, decomposition and the like) and are transported to a silicon wafer (collision occurs among the particles, ionization, recombination and reaction are generated, and energy exchange and movement direction change are generated). The particles coagulate, nucleate, grow up and film on the silicon wafer. Under the action of a magnetic field and an electric field, the target material (Mg, ag, ti, mo) is bombarded by accelerated charged gas ions (Ar, N2) to enable target material atoms to escape from the surface and precipitate on a silicon wafer to form an ITO film or a metal film (physical vapor deposition, chemical reaction does not occur), most of the ITO material or the metal material is deposited on a substrate, and part of the ITO material or the metal material is deposited on the inner wall of a cavity of the equipment. This Process (PVD) is done in an OLED coater.

And (3) distributing the photoresist dropped on the silicon wafer on the surface of the silicon wafer by virtue of centrifugal force and gravity generated during the rotation of the silicon wafer. The photoresist mainly comprises a high molecular polymer and an organic solvent, wherein the high molecular polymer is a main body of the photoresist, the main component of the high molecular polymer is phenolic resin, and the organic solvent is a medium of the photoresist. In order to firmly attach the photoresist on the silicon wafer, the photoresist is heated and baked by an electric heating plate of the equipment after the photoresist is coated.

And carrying out illumination photoetching on the glued silicon wafer by using a photoetching machine and through a photomask, namely, enabling part of the photoresist to be illuminated and the other part of the photoresist to be not illuminated, so that the property of the photoresist is selectively changed. And removing the exposed photoresist by using TMAH developing solution in a spraying mode to carry out photoetching, namely, the photoresist after illumination is dissolved in the developing solution, the photoresist without illumination is not dissolved in the developing solution, a groove is formed on the photoresist, and the lower metal layer is exposed so as to facilitate the etching of the next process, and the photoresist without exposure is not cleaned, so that the lower surface is extremely protected. After development, the substrate is sprayed and washed by pure water and is purged and dried by nitrogen (the developing machine integrates the functions of development, water washing and drying).

The unexposed photoresist is removed, for example, washed with pure water after immersion stripping using a stripping solution, and dried by nitrogen purging (stripper integrated with stripping, water washing, drying functions), thereby forming the patterned first electrode P1.

In step A2, an organic material layer R, a second conductive layer C2, and a first insulating layer S1 are sequentially formed on the surface of the first electrode P1.

In this embodiment, the organic material layer R includes a hole transport layer (not labeled), a light emitting layer (not labeled), and an electron transport layer (not labeled) sequentially stacked from bottom to top. Wherein the hole transport layer, the light emitting layer and the electron transport layer are each composed of n-type or p-type organic material molecules.

For example, the organic material layer R may be formed by thermal evaporation, in which the organic material is changed from solid state to vapor state by sublimation or melting in a vacuum environment through heating, and the gaseous molecules moving at high speed reach the glass substrate and are deposited and solidified on the substrate, and then are changed back into a solid film of OLED material. Specifically, the small molecular material is placed in an electron beam evaporator, energy is transferred to the small molecular material through an electric heating device, the small molecular material is changed into gaseous molecules and deposited on the surface of the layer structure where the first electrode P1 is located, and an organic film is formed.

The second conductive layer C2 is formed on the surface of the organic material layer R, and in this embodiment, the material of the second conductive layer C2 may be a metal material, for example, a low work function metal material (or alloy), such as magnesium alloy.

The first insulating layer S1 may be formed on the surface of the second conductive layer C2 by coating (coating) to protect the organic material layer R and simultaneously achieve the effect of a planarization layer. The material of the first insulating layer S1 may be silicon nitride or a resin material.

In step A3, a first opening H1 is formed in the first insulating layer S1, the second conductive layer C2 and the organic material layer R corresponding to the region between two adjacent first electrodes P1, the surface of the first substrate Sub is exposed from the first opening H1, and the second conductive layer C2 is separated by the first opening H1 and forms a plurality of second electrodes P2 spaced apart by a predetermined distance.

Specifically, forming the first opening H1 includes:

the first insulating layer S1 is subjected to a photolithography process (photo) through a mask corresponding to the position of the spaced region between the adjacent two first electrodes P1 to form a first sub-opening H11. In this embodiment, the first insulating layer S1 is patterned through a photolithography process and a mask, thereby forming the first sub-opening H11.

The dry etching of the second conductive layer C2 and the organic material layer R is continued corresponding to the first sub-opening H11, thereby forming a first opening H1. The organic material layer R is etched in a dry etching mode, so that pollution to the organic material can be effectively avoided.

And A4, forming a second insulating layer S2 on the surface of the first insulating layer S1, wherein the second insulating layer S2 also fills the first opening H1, and the first insulating layer S1 and the second insulating layer S2 are matched together to form a planarization layer TD.

The second insulating layer S2 is formed on the surface of the first insulating layer S1 by a coating process, and meanwhile, the second insulating layer S2 also fills the first opening H1 at the same time, so that the plurality of first electrodes P1 and the plurality of second electrodes P2 are isolated from each other, that is, the pixel units P formed by the first electrodes P1, the organic material layer R and the second electrodes P2 are all spaced apart from each other by the second insulating layer S2 filled in the first opening H1, thereby preventing interference of light rays emitted between adjacent pixel units P.

In this embodiment, the first electrode P1 is used as an anode of the OLED pixel unit, and the second electrode P2 is used as a cathode of the OLED pixel unit, that is, the first electrode P1, the organic material layer R and the second electrode P2 form an OLED light emitting device, which is also used as a pixel electrode for emitting light in the pixel unit. The principle of light emission of the pixel unit P is as follows: electrons and holes of the electron transport layer in the organic material layer R are injected from the second electrode P2 as a cathode and the first electrode P1 as an anode and are conducted to the light emitting layer, and are combined in the light emitting layer to emit light. In this embodiment, the light emitted from the pixel electrode formed by the first electrode P1, the organic material layer R and the second electrode P2 is white.

Referring to fig. 3 and fig. 5, in step 2000, an opening is formed in the planarization layer TD corresponding to the position of the second electrode P2, and a portion of the second electrode P2 is exposed from the second opening H2.

In this embodiment, please refer to fig. 5, which is a schematic side view of a second step in the manufacturing process of the display panel shown in fig. 3, the second insulating layer S2 and the first insulating layer S1 are etched by a photolithography process and a mask at a position corresponding to the second electrode P2 to form a second opening H2, and a portion of the second electrode P2 is exposed from the second opening H2.

Referring to fig. 3 and 6, in step 3000, a third electrode P3 is formed on the surface of the second insulating layer S2 and the second opening H2 in the planarization layer TD, where the third electrode P3 is further connected to the second electrode P2 at the position of the second opening H2.

In this embodiment, please refer to fig. 6, which is a schematic side structure of step three in the manufacturing process of the display panel shown in fig. 3, the third electrode P3 covers the surface of the second insulating layer S2 and the surface of the second opening H2 with a metal material serving as a cathode through a mask and evaporation, and the second electrode P2 is electrically connected with the third electrode P3, meanwhile, the area of the third electrode P3 is larger, so that all the second electrodes P2 are connected with the same potential through the third electrode P3, meanwhile, the on-resistance is reduced through the third electrode P3 with a larger area, and the second electrode P2 and the third electrode P3 are effectively disconnected through the buffering of the first insulating layer S1 and the second insulating layer S2, so that the safety and reliability of the second electrode P2 are ensured.

Referring to fig. 3 and 7, in step 4000, an encapsulation layer EN and a photoresist layer PH are sequentially formed on the surface of the third electrode P3.

In this embodiment, please refer to fig. 7, which is a schematic side view of a fourth step in the manufacturing process of the display panel shown in fig. 3, wherein an encapsulation layer EN is formed on the surface of the third electrode P3 by coating, vapor deposition or printing, and the encapsulation layer EN is used for protecting the third electrode P3.

The packaging layer EN is formed by packaging the first substrate Sub after the electrodes and the organic thin film functional layers are manufactured, for example, an epoxy resin is cured by ultraviolet to form a closed screen cover for the components on the first substrate Sub, so that the functional layers of the components are separated from air, and the components on the first substrate Sub are effectively prevented from being damaged by components such as water and oxygen in the air.

The photoresist layer PH includes a plurality of color filter units of different colors, which are periodically arranged, and the color filter units are used for filtering white light emitted from the organic material layer to emit light of different colors. In this embodiment, the color filter units of different colors are a Red filter unit (Red), a Green filter unit (Green) and a Blue filter unit (Blue), and the Red filter unit (Red), the Green filter unit (Green) and the Blue filter unit (Blue) are taken as a group and are arranged periodically, so that the light emitted from each pixel electrode is filtered to form a color image.

The formation of the photoresist layer PH also includes photoresist coating, exposure, development, and other photolithography processes. For example, a red photoresist is coated, then a red photoresist corresponding to the pixel is formed as a red filter layer through exposure, development and baking, and the process is repeated to manufacture a green, blue and other photoresist filter layers.

With continued reference to fig. 7, in the display panel 10 shown in fig. 7, a third electrode P3 connected to the second electrode P2 is disposed on the planarization layer TD, so that the area occupied by the third electrode P3 is larger, the cross-sectional area of the second electrode P2 can be effectively increased by the third electrode P3, the impedance of the whole second electrode P2 as the cathode in the pixel unit P can be effectively reduced, the impedance loss of the second electrode P2 in each different position can be effectively improved, the impedance loss (IR-drop) of the pixel unit P in each different position can be effectively improved, and the uniformity of image display can be ensured.

Further, the pixel units P are isolated by the planarization layer TD, that is, different pixel areas are defined by the second insulating layer S2 and the first opening H1 in the planarization layer TD, that is, the first electrode P1 and the organic material layer R in each pixel unit are separated by the planarization layer TD, so that no leakage or crosstalk of electron flow exists between the organic material layers R in adjacent pixel units, thereby preventing color shift of a displayed image.

Further, when the second electrode P2 is formed, the first insulating layer S1 and the second conductive layer C2 are subjected to a photolithography process and dry etching, so that the distance between the second electrodes P2 can be finer, the distance between the pixel units P can be kept within a smaller range, the number of the pixel units P in the display panel 10 can have a larger lifting space, and a larger light emitting area and higher brightness can be maintained. Meanwhile, when the organic material layer R is etched, the first insulating layer S1 adopts a photoetching process, so that pollution is brought when the organic material layer R is etched by a wet method, and the performance safety and stability of the organic material layer R are ensured.

Fig. 3 and fig. 8-11 are schematic side views of a display panel according to a second embodiment of the application.

Specifically, referring to fig. 3 and 8, fig. 8 is a schematic side view of a step one in the manufacturing process of the display panel shown in fig. 3 in a second embodiment of the present application, in step 1000, a first substrate Sub is provided, a plurality of pixel units P with a predetermined distance and a planarization layer TD covering the pixel units P are formed on the surface of the first substrate Sub, and the pixel units P include a first electrode P1, an organic material layer R, and a second electrode P2. That is, one of the first electrodes P1, the organic material layer R, and one of the second electrodes P2 form one pixel unit P, and the second electrode P2 cooperates with the first electrode P1 to drive the organic material layer R to emit light.

In this embodiment, more specifically, step 1000 further includes:

in step B1, a first substrate Sub is provided, and a first conductive layer C1 is disposed on a surface of the first substrate Sub.

In this embodiment, as shown in fig. 8, the first substrate Sub may be made of transparent plastic, glass or metal foil, and is used for the subsequent whole layer structure. The first substrate Sub is pre-formed with a driving circuit for driving the pixel unit of the OLED, wherein the driving circuit comprises a thin film transistor (Thin Film transistor TFT) and a capacitor and other components.

The first conductive layer C1 is an N-type oxide semiconductor material, such as transparent Indium Tin Oxide (ITO). The first conductive layer C1 may be an ITO layer formed on the first substrate Sub by magnetron sputtering or the like.

In step B2, an organic material layer R, a second conductive layer C2, and a first insulating layer S1 are sequentially formed on the surface of the first conductive layer C1.

The surface of the organic material layer R forms a second conductive layer C2, and the second conductive layer C2 is matched with the first conductive layer C1 to drive the organic material layer R to emit light. In this embodiment, the material of the second conductive layer C2 may be a metal material, such as a low work function metal material (or alloy), for example, magnesium alloy.

In step B3, the first insulating layer S1, the second conductive layer C2, the organic material layer R and the first conductive layer C1 are patterned through a mask to form a first opening H1, the surface of the first substrate Sub is exposed from the first opening H1, and the second conductive layer C2 forms a plurality of second electrodes P2 spaced apart from each other by a predetermined distance through the first opening H1.

Specifically, forming the first opening H1 includes:

the first sub-opening H11 is formed by performing a photolithography process (photo) on the first insulating layer S1 through a mask. In this embodiment, the first insulating layer S1 is patterned through a photolithography process and a mask, thereby forming the first sub-opening H11.

The second conductive layer C2 and the organic material layer R are continuously dry etched corresponding to the first sub-opening H11 to form a second sub-opening H12. Thereby, the second conductive layer C2 is spaced apart through the second sub-openings H12 to form a plurality of second electrodes P2 spaced apart by a preset distance.

The first conductive layer C1 is continuously wet etched corresponding to the second Sub-opening H12, so as to form a first opening H1, wherein the first substrate Sub is exposed from the first opening H1. Thereby, the first conductive layer C1 is spaced apart through the first opening H1 to form a plurality of first electrodes P1 spaced apart by a preset distance.

And B4, forming a second insulating layer S2 on the surface of the first insulating layer S1, wherein the second insulating layer S2 also fills the first opening H1, and the first insulating layer S1 and the second insulating layer S2 are matched together to form a planarization layer TD.

The second insulating layer S2 is formed on the surface of the first insulating layer S1 through a coating (coating) process, and meanwhile, the second insulating layer S2 also fills the first opening H1 at the same time, so that the plurality of first electrodes P1 and the plurality of second electrodes P2 are isolated from each other. That is, the pixel units P formed of the first electrode P1, the organic material layer R and the second electrode P2 are spaced apart from each other by the second insulating layer S2 filled in the first opening H1, so that interference of light emitted between adjacent pixel units P is prevented.

Referring to fig. 3 and 9, in step 2000, an opening is formed in the planarization layer TD corresponding to the position of the second electrode P2, and a portion of the second electrode P2 is exposed from the second opening H2.

Specifically, as shown in fig. 9, a schematic side structure of a second step in the manufacturing process of the display panel shown in fig. 3 in the second embodiment of the present application is that the second insulating layer S2 and the first insulating layer S1 in the planarization layer TD are etched to form a second opening H2, and a portion of the second electrode P2 is exposed from the second opening H2. In this embodiment, the second insulating layer S2 and the first insulating layer S1 may be etched by a photolithography process and a mask to form a second opening H2, so that a portion of the second electrode P2 is exposed from the second opening H2.

Referring to fig. 3 and 10, in step 3000, a third electrode P3 is formed on the surface of the second insulating layer S2 and the second opening H2 in the planarization layer TD, where the third electrode P3 is further connected to the second electrode P2 at the position of the second opening H2.

Specifically, as shown in fig. 10, which is a schematic side view of a third step in the manufacturing process of the display panel shown in fig. 3 in the second embodiment of the present application, a third electrode P3 is formed on the surface of the second insulating layer S2 and the second opening H2, wherein the third electrode P3 is further connected to the second electrode P2 at the position of the second opening H2.

In this embodiment, the third electrode P3 covers the surface of the second insulating layer S2 and the surface of the second opening H2 with a metal material serving as a cathode in a mask and vapor deposition manner, and since the second electrode P2 is directly connected with the third electrode P3 to be electrically conducted, the area of the third electrode P3 is larger, so that all the second electrodes P2 are ensured to be connected to the same potential through the third electrode P3, on-resistance is reduced through the third electrode P3 with a larger area, and disconnection between the second electrode P2 and the third electrode P3 is effectively ensured through buffering of the first insulating layer S1 and the second insulating layer S2, so that safety and reliability of the second electrode P2 are ensured.

Referring to fig. 3 and 11, in step 4000, a packaging layer EN and a photoresist layer PH are sequentially formed on the surface of the third electrode P3.

Specifically, as shown in fig. 11, which is a schematic side view of a fourth step in the manufacturing process of the display panel shown in fig. 3 in the second embodiment of the present application, an encapsulation layer EN is formed on the surface of the third electrode P3 by coating, vapor deposition or printing, and the encapsulation layer EN is used for protecting the third electrode P3.

The photoresist layer PH includes a plurality of color filter units of different colors, which are periodically arranged, and the color filter units are used for filtering white light emitted from the organic material layer to emit light of different colors. In this embodiment, the color filter units of different colors are a Red filter unit (Red), a Green filter unit (Green) and a Blue filter unit (Blue) B, and the Red filter unit (Red), the Green filter unit (Green) and the Blue filter unit (Blue) are taken as a group and are arranged periodically, so that the light emitted from each pixel electrode is filtered to form a color image.

In this embodiment, the first electrode P1 is etched in one process along with the organic material layer R, the second electrode P2 and the planarization layer TD, so that the photolithography process for the first conductive layer C1 can be omitted, and the complexity of the process is reduced effectively.

Referring to fig. 12, fig. 12 is a flow chart illustrating a manufacturing process of the display panel shown in fig. 2 according to a third embodiment of the application.

As shown in fig. 12, the manufacturing of the display panel 30 (as shown in fig. 16) includes steps 1000 to 4000. Specifically:

referring to fig. 12 and 13, fig. 13 is a schematic side view of a first step in the manufacturing process of the display panel shown in fig. 12, in step 1000, a first substrate Sub is provided, a plurality of pixel units P with predetermined intervals and a planarization layer TD covering the pixel units P are formed on the surface of the first substrate Sub, and the pixel units P include a first electrode P1, an organic material layer R, and a second electrode P2. That is, one of the first electrodes P1, the organic material layer R, and one of the second electrodes P2 form one pixel unit P, and the second electrode P2 cooperates with the first electrode P1 to drive the organic material layer R to emit light.

In this embodiment, more specifically, step 1000 further includes:

In step C10, as shown in fig. 13, a first substrate Sub is provided, and a first conductive layer C1 is formed on the surface of the first substrate Sub, where the first conductive layer C1 includes a plurality of first electrodes P1 spaced apart by a predetermined distance. In the present embodiment, the first electrode P1 includes a plurality of first sub-electrodes P11, second sub-electrodes P12 and third sub-electrodes P13.

In this embodiment, the first substrate Sub may be made of transparent plastic, glass, or metal foil, and is used for the subsequent whole layer structure. The first substrate Sub is pre-formed with a driving circuit for driving the pixel unit of the OLED, wherein the driving circuit comprises a thin film transistor (Thin Film transistor TFT) and a capacitor and other components.

The first conductive layer C1 is an N-type oxide semiconductor material, such as transparent Indium Tin Oxide (ITO). The first conductive layer C1 may be an ITO layer formed on the first substrate Sub by magnetron sputtering or the like. In this embodiment, the first electrode P1 may be formed by patterning after the ITO layer is disposed on the first substrate Sub, for example, by performing an etching lithography process (photo) patterning using a Mask (Mask) including a pattern. In this embodiment, the first electrode P1 serves as an anode of the pixel unit. The photolithography process mainly includes steps of photoresist coating (PR coating), exposing (exposing), developing (developing), and yellow etching on a substrate, thereby forming a plurality of first electrodes P1 spaced a predetermined distance on the ITO layer.

The first electrode P1 includes a first sub-electrode P11, a second sub-electrode P12, and a third sub-electrode P13 that are sequentially and periodically arranged, where the first sub-electrode P11, the second sub-electrode P12, and the third sub-electrode P13 respectively correspond to one pixel unit.

In step C20, a first sub-organic material layer R1, a second conductive layer C2 and a first insulating layer S1 are sequentially formed on the surface of the first electrode P1.

The first sub-organic material layer R1 includes a hole transport layer (not labeled), a light emitting layer (not labeled), and an electron transport layer (not labeled) sequentially stacked from bottom to top. Wherein the hole transport layer, the light emitting layer and the electron transport layer are each composed of n-type or p-type organic material molecules. In this embodiment, the light emitting layer in the first sub-organic material layer R1 emits the light of the first color. For example, to emit red light.

In step C30, the first sub-organic material layer R1, the second conductive layer C2 and the first insulating layer S1 are etched at positions corresponding to the second sub-electrode P12 and the third sub-electrode P13.

That is, the first insulating layer S1, the second conductive layer C2 and the first Sub-organic material layer R1 are etched and formed in the region corresponding to the interval between the adjacent two first Sub-electrodes P11 to form a first auxiliary opening HL1, a part of the surface of the first substrate Sub and the second Sub-electrode P12 and the third Sub-electrode P13 are exposed from the first auxiliary opening HL1, the second conductive layer C2 is separated by the first auxiliary opening HL1 to form a plurality of second electrodes P2 separated by a predetermined distance, the first insulating layer S1 and the first Sub-organic material layer R1 are separated by the first auxiliary opening HL1, and the first insulating layer S1 is separated by the first auxiliary opening HL1 to form the first Sub-insulating layer S11 on the first Sub-electrode P11.

In this embodiment, the first sub-electrode P11, the first sub-organic material layer R1 and the second electrode P2 form a first sub-pixel unit PR, and the light emitting layer in the first sub-organic material layer R1 of the first sub-pixel unit emits the light of the first color under the driving of the first sub-electrode P11 and the second electrode P2.

In step C40, a second sub-organic material layer R2, a second electrode P2, and a second sub-insulating layer S12 are formed on the surface of the second sub-electrode P12.

The second sub-organic material layer R2 includes a hole transport layer (not labeled), a light emitting layer (not labeled), and an electron transport layer (not labeled) sequentially stacked from bottom to top. Wherein the hole transport layer, the light emitting layer and the electron transport layer are each composed of n-type or p-type organic material molecules. In this embodiment, the light emitting layer emits the light of the second color under the driving of the second sub-electrode P12 and the second electrode P2. For example, green light.

In this embodiment, the second sub-electrode P12, the second sub-organic material layer R2 and the second electrode P2 form a second sub-pixel unit PG, and the light emitting layer in the second sub-organic material layer R2 of the second sub-pixel unit PG emits light of the second color under the driving of the second sub-electrode P12 and the second electrode P2.

In step C50, a third sub-organic material layer R3, a second electrode P2, and a third sub-insulating layer S13 are formed on the surface of the third sub-electrode P13.

The third sub-organic material layer R3 includes a hole transport layer (not labeled), a light emitting layer (not labeled), and an electron transport layer (not labeled) sequentially stacked from bottom to top. Wherein the hole transport layer, the light emitting layer and the electron transport layer are each composed of n-type or p-type organic material molecules. In this embodiment, the light emitting layer in the third sub-organic material layer R3 emits the light of the third color under the driving of the third sub-electrode P13 and the second electrode P2. For example, green light.

In this embodiment, the third sub-electrode P13, the third sub-organic material layer R3 and the second electrode P2 form a third sub-pixel unit PB, and the light emitting layer in the third sub-organic material layer R3 of the third sub-pixel unit PB emits the light of the second color under the driving of the third sub-electrode P13 and the second electrode P2.

The first sub-pixel unit PR, the second sub-pixel unit PG, and the third sub-pixel unit PB are spaced by a predetermined distance, that is, a first opening H1 having a predetermined distance between the first sub-pixel unit PR, the second sub-pixel unit PG, and the third sub-pixel unit PB.

In step C60, the second insulating layer S2 is formed on the first substrate Sub surface between the first Sub-insulating layer S11, the second Sub-insulating layer S12, and the third Sub-insulating layer S13 and the first Sub-electrode P11, the second Sub-electrode P12, and the third Sub-electrode P13, that is, the first substrate Sub surface between the first Sub-pixel unit PR, the second Sub-pixel unit PG, and the third Sub-pixel unit PB is also covered with the second insulating layer S2. In this embodiment, the second insulating layer S2 constitutes the planarization layer TD. In other words, the second insulating layer S2 covers the first sub-insulating layer S11, the second sub-insulating layer S12 and the third sub-insulating layer S13 and fills the region of the first opening H1 spaced between the first sub-pixel unit PR, the second sub-pixel unit PG and the third sub-pixel unit PB, so that the first sub-pixel unit PR, the second sub-pixel unit PG and the third sub-pixel unit PB are spaced apart from each other, and particularly, the first sub-organic material layer R1, the second sub-organic material layer R2 and the third sub-organic material layer R3 are completely electrically isolated from each other by the second insulating layer S2, thereby effectively preventing current flow between adjacent sub-pixel units and ensuring accurate image display between the sub-pixel units.

The second insulating layer S2 is formed on the surfaces of the first sub-insulating layer S11, the second sub-insulating layer S12 and the third sub-insulating layer S13 through a coating (coating) process, and meanwhile, the second insulating layer S2 also fills the first opening H1 area spaced between the first sub-pixel unit PR, the second sub-pixel unit PG and the third sub-pixel unit PB, so that the first electrodes P1 and the second electrodes P2 are isolated from each other, that is, the first sub-pixel unit PR, the second sub-pixel unit PG and the third sub-pixel unit PB are isolated from each other through the second insulating layer S2 filled in the openings, thereby preventing interference of light rays emitted between the adjacent pixel units P.

Referring to fig. 12 and 14, in step 2000, an opening is formed in the planarization layer TD corresponding to the position of the second electrode P2, and a portion of the second electrode P2 is exposed from the second opening H2.

In this embodiment, as shown in fig. 14, which is a schematic side structure of a second step in the manufacturing process of the display panel shown in fig. 12, the second insulating layer S2 and the first insulating layer S1 are etched by a photolithography process and a mask at a position corresponding to the second electrode P2 to form a second opening H2, and a portion of the second electrode P2 is exposed from the second opening H2.

Specifically, a plurality of second openings H2 are formed at the positions of the second insulating layer S2, the first sub-insulating layer S11, the second sub-insulating layer S12 and the third sub-insulating layer S13 corresponding to the positions of the first sub-pixel unit PR, the second sub-pixel unit PG and the third sub-pixel unit PB, and the second openings H2 are formed on the surface of the second electrode P2 and are exposed from the openings.

Referring to fig. 12 and 15, in step 3000, fig. 15 is a schematic side view of a third step in the manufacturing process of the display panel shown in fig. 12, a third electrode P3 is formed on the surface of the second insulating layer S2 and the second opening H2 in the planarization layer TD, wherein the third electrode P3 is further connected to the second electrode P2 at the position of the second opening H2.

Referring to fig. 12 and 16, in step 4000, an encapsulation layer EN is formed on the surface of the third electrode P3, and the encapsulation layer EN is used for protecting the third electrode P3.

In this embodiment, as shown in fig. 16, which is a schematic side structure of a fourth step in the manufacturing process of the display panel shown in fig. 12, in the first sub-pixel unit PR, the first sub-electrode P11 and the second electrode P2 cooperate to drive the first sub-organic material layer R1 to emit light of the first color; in the second sub-pixel unit PG, the second sub-electrode P12 cooperates with the second electrode P2 to drive the second sub-organic material layer R2 to emit light of the second color; in the third sub-pixel unit PB, the third sub-electrode P13 cooperates with the second electrode P2 to drive the third sub-organic material layer R3 to emit light of the third color. In this embodiment, the light of the first color is Red (Red) light, the light of the second color is Green (Green) light, and the light of the third color is Blue (Blue) light. Compared with the first embodiment and the second embodiment, in this embodiment, each pixel unit can emit light with different colors, and accordingly the display panel 30 does not need to be provided with a photoresist layer, which simplifies the structure of the display panel 30.

With continued reference to fig. 16, in the display panel 30 after the fabrication shown in fig. 16, the first sub-pixel unit PR, the second sub-pixel unit PG and the third sub-pixel unit PB in the pixel unit P are isolated by the planarization layer TD, that is, different pixel areas are defined by the second insulating layer S2 and the first opening in the planarization layer TD, so that the light emitted from the pixel electrodes in the two adjacent pixel areas will not cross, and further, the pixel electrodes between the adjacent pixel units P are isolated from the first sub-organic material layer R1, the second sub-organic material layer R2 and the third sub-organic material layer R3 by the second insulating layer S2, so that no leakage or crosstalk of electron flow exists between the first sub-organic material layer R1, the second sub-organic material layer R2 and the third sub-organic material layer R3 in the adjacent pixel units P, thereby preventing the color shift of the displayed image.

The second electrode P2 is electrically connected with the third electrode P3, and the third electrode P3 is formed by a large-area whole-layer structure, so that cathodes of all pixel electrodes in a display area are electrically connected to the same potential, the third electrode P3 effectively increases the cross-sectional area of the cathode serving as the pixel electrode, further effectively reduces the overall impedance of the cathode, effectively improves the impedance loss (IR-drop) of the pixel electrode in each different position, and ensures the uniformity of image display.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims

1. A method for manufacturing a display panel, comprising:

providing a first substrate, sequentially forming a plurality of pixel units and a planarization layer covering the pixel units on the surface of the first substrate, wherein each pixel unit comprises a first electrode, an organic material layer and a second electrode which are sequentially stacked, the pixel units pass through the planarization layer and are separated from each other, and the second electrode and the first electrode are used for driving the organic material layer to emit light;

2. The method of manufacturing a display panel according to claim 1, wherein sequentially forming a plurality of pixel units and a planarization layer covering the pixel units on the surface of the first substrate comprises:

forming a first opening in the first insulating layer, the second conductive layer and the organic material layer at a position corresponding to a spacing region between two adjacent first electrodes, wherein the first substrate is exposed from the first opening, and the second conductive layer forms a plurality of second electrodes with preset spacing distances through the first opening;

3. The method of manufacturing a display panel according to claim 2, wherein forming the first opening comprises:

4. The method of manufacturing a display panel according to claim 1, wherein sequentially forming a plurality of pixel units and a planarization layer covering the pixel units on the surface of the first substrate comprises:

5. The method of manufacturing a display panel according to claim 4, wherein forming the first opening comprises:

6. The method of any one of claims 2 to 5, wherein forming a third electrode on the surface of the planarization layer and the opening surface comprises:

7. The method of manufacturing a display panel according to claim 6, wherein forming the third electrode further comprises:

8. The method of manufacturing a display panel according to claim 1, wherein sequentially forming a plurality of pixel units and a planarization layer covering the pixel units on the surface of the first substrate comprises:

9. The method of manufacturing a display panel according to claim 8, wherein forming a third electrode on the surface of the planarization layer and the opening surface comprises:

10. The method of claim 9, wherein an encapsulation layer is formed on the surface of the third electrode, the first sub-electrode cooperates with the second electrode to drive the first sub-organic material layer to emit light of a first color, the second sub-electrode cooperates with the second electrode to drive the second sub-organic material layer to emit light of a second color, and the third sub-electrode cooperates with the second electrode to drive the third sub-organic material layer to emit light of a third color.

11. A display panel, comprising:

and a planarization layer covering the first substrate surface and the second electrode surface between the pixel units, wherein a plurality of the pixel units pass through the planarization layer and comprise openings at positions corresponding to the second electrodes, third electrodes are arranged on the surfaces of the planarization layer and the surfaces of the openings, and the third electrodes are connected with the second electrodes at the positions of the openings.

12. The display panel according to claim 11, wherein the planarization layer includes a first insulating layer and a second insulating layer, the first insulating layer covering the second electrode, the first insulating layer and the organic material layer being provided with a first opening in a region corresponding to between the second electrode and the first electrode, the second insulating layer filling the opening.

13. The display panel of claim 11, wherein the display panel comprises,

the first electrode comprises a plurality of first sub-electrodes, second sub-electrodes and third sub-electrodes which are spaced at preset distances;

14. A display terminal comprising the display panel according to any one of claims 11 to 13, wherein the display panel further comprises a data driving circuit, a scanning driving circuit and a plurality of pixel units arranged in an array, the data driving circuit is connected to the plurality of pixel units through a plurality of data lines, the scanning driving circuit is connected to the pixel units through a plurality of scanning lines, the scanning driving circuit outputs scanning signals to the pixel units to control the pixel units to receive data signals output by the data driving circuit, and the pixel units execute image display according to the data signals.