CN116825045A

CN116825045A - Display panel and display device

Info

Publication number: CN116825045A
Application number: CN202310794114.7A
Authority: CN
Inventors: 邹芬香
Original assignee: Xiamen Tianma Display Technology Co Ltd
Current assignee: Xiamen Tianma Display Technology Co Ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2023-09-29

Abstract

The invention discloses a display panel and a display device, which belong to the technical field of display, wherein the display panel comprises a display area and a non-display area at least partially surrounding the display area; the non-display area comprises a scanning driving circuit and a plurality of first signal lines connected with the scanning driving circuit; the scanning driving circuit comprises a plurality of cascaded shift register units, wherein each shift register unit comprises a plurality of signal input ends, and the signal input ends are connected with a first signal line; the shift register unit includes a plurality of thin film transistors; the display panel comprises a substrate and a transistor array layer positioned on one side of the substrate, wherein the thin film transistor is positioned on the transistor array layer; the first signal line is positioned on one side of the film layer, which is far away from the substrate, of the transistor array layer. The display device comprises the display panel. The invention can realize the design of a narrow frame, ensure the driving effect and improve the display quality.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.

Background

With the continuous development of liquid crystal display technology, organic Light-Emitting Diode (OLED) panels or liquid crystal display panels and the like have been widely used in electronic terminals such as mobile phones and tablet computers to realize Light and thin, high-quality display effects and the like.

The display device comprises a grid driving circuit positioned in the frame area and a scanning line positioned in the display area, wherein the grid driving circuit comprises a multi-stage shift register circuit (Vertical Shift Register, VSR), and the shift register circuit is connected with the scanning line and is used for providing scanning signals for the scanning line. The existing grid driving circuit has a plurality of devices, a complex structure and large occupied space, so that a large space is reserved in a non-display area generally, and the narrow frame design is not facilitated.

In order to realize the narrow frame design at present, the area of a non-display area is generally required to be compressed, if the size of a part of the non-display area is compressed, the size of the part easily exceeds the limit of the current manufacturing process, the performance of other parts is influenced, and the problem of poor display effect is caused; if the dimensions of the components in the non-display area are guaranteed, the space between the different conductive structures in the non-display area needs to be compressed, the distances between the different conductive structures may be closer, signal coupling is easy to occur, and risks of poor driving are likely to be caused, so that the display effect is affected.

Therefore, the display panel and the display device which can realize the design of a narrow frame and ensure the driving effect and improve the display quality are technical problems to be solved by the technicians in the field.

Disclosure of Invention

In view of the above, the present invention provides a display panel and a display device, so as to solve the problem that the display quality of the display device with narrow frame design in the prior art is easily affected.

The invention discloses a display panel, comprising: a display region and a non-display region disposed at least partially around the display region; the non-display area comprises a scanning driving circuit and a plurality of first signal lines connected with the scanning driving circuit; the scanning driving circuit comprises a plurality of cascaded shift register units, wherein each shift register unit comprises a plurality of signal input ends, and the signal input ends are connected with a first signal line; the shift register unit includes a plurality of thin film transistors; the display panel comprises a substrate and a transistor array layer positioned on one side of the substrate, wherein the thin film transistor is positioned on the transistor array layer; the first signal line is positioned on one side of the film layer, which is far away from the substrate, of the transistor array layer.

Based on the same inventive concept, the invention also discloses a display device, which comprises the display panel.

Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:

the display panel provided by the invention comprises a display area and a non-display area at least partially arranged around the display area, wherein the non-display area comprises a scanning driving circuit, the scanning driving circuit comprises a plurality of cascaded shift register units, and the plurality of cascaded shift register units of the scanning driving circuit can scan display sub-pixels in the display area of the display panel line by line so as to display pictures. The display panel comprises a substrate, wherein a transistor array layer is arranged on one side of the substrate, and a thin film transistor included in a scanning driving circuit is positioned on the transistor array layer. The film layer for manufacturing the first signal line is arranged on one side of the transistor array layer far away from the substrate, namely, in the direction perpendicular to the plane of the substrate, the film layer where the first signal line connected with the signal input end of the shift register unit is different from the film layer where the thin film transistor is located, and the film layer where the first signal line is located avoids the transistor array layer where the thin film transistor is located, so that the space of the transistor array layer can be saved, the size of the thin film transistor of the transistor array layer can be guaranteed through enough space, the width of the non-display area in the direction parallel to the plane of the substrate can be compressed as much as possible while the driving performance is guaranteed, the layout of the first signal line does not occupy the space of the transistor array layer in the direction parallel to the plane of the substrate, and the width of the non-display area in the direction parallel to the plane of the substrate can be compressed as much as possible, and the narrower frame effect of the display panel can be realized.

Of course, it is not necessary for any one product to practice the invention to achieve all of the technical effects described above at the same time.

Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic view of a partial cross-sectional structure of the J1 region in FIG. 1;

fig. 3 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram showing a partial cross-sectional structure of a portion of the area where the shift register unit is located and a portion of the display area in FIG. 3;

FIG. 5 is a schematic diagram showing a partial cross-sectional structure of a portion of the display area and a portion of the region where the shift register unit of FIG. 1 is located;

FIG. 6 is a schematic diagram showing another partial cross-sectional structure of a portion of the display area and a portion of the region where the shift register unit of FIG. 3 is located;

fig. 7 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 8 is a schematic diagram showing a partial cross-sectional structure of a portion of the area where the shift register unit is located and a portion of the display area in FIG. 7;

FIG. 9 is a schematic diagram of an electrical connection structure of a pixel circuit and a light emitting element included in the display region of FIG. 7;

FIG. 10 is a schematic diagram showing another partial cross-sectional structure of a portion of the area where the shift register unit is located and a portion of the display area in FIG. 7;

fig. 11 is a schematic plan view of a display device according to an embodiment of the invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present invention may be combined with each other without contradiction.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Referring to fig. 1 and fig. 2 in combination, fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic partial cross-sectional view of a region J1 in fig. 1, where a display panel 000 according to the embodiment includes: a display area AA and a non-display area NA disposed at least partially around the display area AA;

the non-display area NA includes a scan driving circuit 10, a plurality of first signal lines 20 connected to the scan driving circuit 10; the scan driving circuit 10 includes a plurality of cascaded shift register units 101, the shift register units 101 including a plurality of signal input terminals 1011, the signal input terminals 1011 being connected to the first signal lines 20;

the shift register unit 101 includes a plurality of thin film transistors T;

the display panel 000 includes a substrate 01 and a transistor array layer 02 on one side of the substrate 01, and the thin film transistor T is located in the transistor array layer 02;

the first signal line 20 is located on the side of the film layer located on the transistor array layer 02 away from the substrate 01.

Specifically, the display panel 000 provided in this embodiment includes a display area AA and a non-display area NA at least partially surrounding the display area AA, where the display area AA may be provided with display sub-pixels and scan lines or data lines electrically connected to the display sub-pixels, etc. to realize a display screen of the display panel 000. The non-display area NA may be used for setting a driving circuit and a driving chip or a flexible circuit board to be subsequently bound, etc. The non-display area NA includes a scan driving circuit 10, the scan driving circuit 10 includes a plurality of cascaded shift register units 101, and the plurality of cascaded shift register units 101 of the scan driving circuit 10 can scan display sub-pixels in the display area AA of the display panel 000 line by line, thereby displaying a picture.

In this embodiment, the shift register unit 101 of the scan driving circuit 10 may include a plurality of signal input terminals 1011, optionally, the shift register unit 101 may further include a plurality of signal output terminals 1012, and may further include a plurality of thin film transistors T and capacitors (not shown in the drawing, the capacitors may be made of a film layer where the thin film transistors T are located, it may be understood that the thin film transistors T in the non-display area NA may be made of the same film layer as the thin film transistors in the display area AA), and at least part of the signal output terminals 1012 are electrically connected to the scan lines G of the display area AA to realize progressive scanning by using the scan driving signals provided by the scan driving circuit 10 to the scan lines G of the display area AA.

It should be understood that, in the present embodiment, the circuit connection structure of each shift register unit 101 is not specifically limited, and in fig. 1, only the shift register unit 101 is shown in a block diagram, and when the shift register unit 101 includes at least one thin film transistor T, the circuit structure of the shift register unit 101 in the related art is understood.

In this embodiment, the non-display area NA of the frame area includes circuit elements of the scan driving circuit 10, and a plurality of first signal lines 20 connected to the scan driving circuit 10 are required, the signal input terminal 1011 of the shift register unit 101 is connected to the first signal lines 20, and the plurality of first signal lines 20 can transmit signals such as voltage signals and clock signals to each stage of the shift register unit 101 of the scan driving circuit 10 through the signal input terminal 1011. It is understood that, if the number of thin film transistors in the circuit structure of the shift register unit 101 is large, the number of the first signal lines 20 may also be increased, which is not beneficial to implementation of the narrow frame.

In order to solve the above-described problem, the display panel 000 of the present embodiment includes the substrate 01, the substrate 01 is used as a carrier substrate for other film layers of the display panel 000, and the substrate 01 may be any of a hard material or a flexible material, which is not limited in this embodiment. A transistor array layer 02 is provided on the substrate 01 side, and a thin film transistor T included in the scan driving circuit 10 (or a thin film transistor included in the display area AA) is provided on the transistor array layer 02. Alternatively, the transistor array layer 02 may include a plurality of metal conductive layers and a plurality of insulating layers, which is not limited in this embodiment. In this embodiment, the film layer for manufacturing the first signal line 20 is disposed on the side of the transistor array layer 02 far away from the substrate 01, that is, in the direction Z perpendicular to the plane of the substrate 01, the film layer on which the first signal line 20 connected to the signal input end 1011 of the shift register unit 101 is different from the film layer on which the thin film transistor T is disposed, and the film layer on which the first signal line 20 is disposed avoids the transistor array layer 02 on which the thin film transistor T is disposed, so that the space of the transistor array layer 02 can be saved, the size of the thin film transistor T of the transistor array layer 02 can be ensured by enough space, the width of the non-display area NA in the direction parallel to the plane of the substrate 01 can be compressed as much as possible while the driving performance is ensured, so that the layout of the first signal line 20 does not occupy the space of the transistor array layer 02 in the direction parallel to the plane of the substrate 01, and the narrower frame effect of the display panel 000 can be realized.

It should be understood that the signal transmitted on the first signal lines 20 is not limited in this embodiment, the plurality of first signal lines 20 may include a start shift signal line (STV) connected to the shift register unit 101, may further include a clock control signal line (CK) connected to the shift register unit 101, may further include a RESET signal line (RESET) connected to the shift register unit 101 and providing a RESET signal to the shift register unit 101, may further include a positive voltage signal line (VGH) or a negative voltage signal line (VGL) connected to the shift register unit 101 and providing a voltage signal to the shift register unit 101, and may further include other types of signal lines providing a voltage signal to the shift register unit 101.

It should be noted that, in the drawings of the present embodiment, the structure of the display panel 000 is only illustrated as an example, and in the specific implementation, the structure of the display panel 000 includes, but is not limited to, other structures capable of implementing a display function, such as a pixel circuit, a light emitting element, etc. of the display area AA, which is not described herein, and the specific reference to the structure of the display panel in the related art will be understood.

In some alternative embodiments, please refer to fig. 3 and fig. 4 in combination, fig. 3 is a schematic plan view of another plane structure of the display panel provided in the embodiment of the present invention, and fig. 4 is a schematic partial cross-sectional view of a portion of the display area and a portion of the area where the shift register unit is located in fig. 3, in which the display area AA includes a plurality of data lines S extending along the first direction Y;

the non-display area NA comprises a binding area BA, and the binding area BA is positioned at one side of the display area AA in the first direction Y;

the binding area BA comprises a plurality of conductive pads 30, the conductive pads 30 are electrically connected with fan-out wires 40, and the fan-out wires 40 are located in the non-display area NA;

the data line S includes a first data line S1, the first data line S1 is electrically connected to the fan-out trace 40 through at least one first connection line 50, and the first connection line 50 is located in the display area AA.

The present embodiment illustrates that the display area AA of the display panel 000 may include a plurality of data lines S, the display area AA may include a plurality of display sub-pixels, the display sub-pixels may include light emitting elements and pixel circuits electrically connected thereto, and the plurality of data lines S extending in the first direction Y are used to provide data voltage signals for the pixel circuits of the respective display sub-pixels, i.e., to provide driving signals for the display panel 000 to realize a display function. It will be appreciated that the present embodiment is not limited to the structure of the pixel circuit in the display sub-pixel, and may be specifically understood with reference to the sub-pixel structure of the display panel in the related art.

The data lines S include first data lines S1, and optionally, the display area AA includes a second display area AA2 and first display areas AA1 located at opposite sides of the second display area AA2 along a second direction X in the display panel 000, where the first direction Y and the second direction X intersect in a direction parallel to a plane of the display panel 000, and fig. 3 of this embodiment only illustrates an example in which the first direction Y and the second direction X are perpendicular to each other in a direction parallel to the plane of the display panel 000. The first display area AA1 of the present embodiment can be understood as a display area near both sides of the edge of the display panel 000 in the second direction X, and the second display area AA2 can be understood as an area of the display area AA relatively near the center. The non-display area NA includes a bonding area BA, where the bonding area BA includes a plurality of conductive pads 30, and the conductive pads 30 are used for subsequent bonding electrical connection with a driving chip or a flexible circuit board, so as to provide driving signals for display for the display panel 000 through the driving chip or the flexible circuit board, and so on. The conductive pad 30 is electrically connected with the fan-out wire 40, the fan-out wire 40 is also located in the non-display area NA, the first data line S1 of the first display area AA1 is electrically connected with the fan-out wire 40 through at least one first connecting wire 50, the first connecting wire 50 is located in the display area AA, and two ends of the first connecting wire 50 are respectively connected with the fan-out wire 40 of the non-display area NA and the first data line S1 of the display area AA; the fanout wire 40 is electrically connected with the conductive pad 30 of the bonding area BA, enabling signal transmission between the first data line S1 and the conductive pad 30. Alternatively, the second display area AA2 of the display panel 000 may include a plurality of second data lines S2, and one end of the second data line S2 may be directly electrically connected to the other fanout lines 40 of the non-display area NA within a region corresponding to the second display area AA 2.

In this embodiment, when the first connection line 50 is disposed in the display area AA, that is, in the second direction X of the embodiment, the first data line S1 in the first display area AA1 located near two side edges of the display panel 000 is electrically connected with the conductive pad 30 of the bonding area BA, the first connection line 50 is electrically connected with the first display area AA, so that the first connection line 50 can be prevented from occupying the space of the non-display area NA, as shown in fig. 3, a portion of the first connection line 50 can gradually extend in the direction near the second display area AA2 within the range of the display area AA, and further extend to the boundary position of the display area AA and the non-display area NA, so that the connection between the first connection line 50 and the fan-out routing line 40 is located as far as possible from the first display area AA1 in the second direction X.

It can be appreciated that, in the design structure of the first connection line 50 in the display area AA of the present embodiment, the requirement of high resolution of the display panel 000 can be met, even if the number of the data lines S included in the display area AA is greater, the first connection line 50 is routed from the display area AA, the space, occupied by the fan-out routing 40 connected with the first connection line 50, of the non-display area NA in the second direction X can be reduced, so that the width, in the second direction X, of the non-display area NA can be further compressed, the requirement of high resolution can be met, the display function can be ensured, and a narrower frame can be realized.

Alternatively, as shown in fig. 4, the first signal line 20 and the first connecting line 50 are arranged in the same layer in this embodiment, that is, the first signal line 20 connected to the shift register unit 101 of the non-display area NA is fabricated by using the film layer where the first connecting line 50 is located, so that the film layer of the first connecting line 50 can be multiplexed to run away the first signal line 20, no additional film layer is required, which is beneficial to reducing the number of film layers in the panel and to implementing the thin design of the display panel 000.

Alternatively, as shown in fig. 1 and fig. 5, fig. 5 is a schematic view of a partial cross-sectional structure of a region where a part of the shift register unit is located and a part of the display area in fig. 1, and this embodiment is exemplified by a display panel 000 which is an organic light emitting diode display panel, the film structure of the display panel 000 may include a substrate 01, a transistor array layer 02 located on one side of the substrate 01, the transistor array layer 02 may sequentially include a semiconductor layer 021, a gate metal layer M1, a capacitor metal layer Mc, a source drain metal layer M2, a first metal layer M3 where a first signal line 10 located on one side of the transistor array layer 02 is located away from the substrate 01, and an anode layer 03 located on one side of the transistor array layer 02 away from the substrate 01. Further alternatively, the data line S may be located in the source-drain metal layer M2 or the data line S may also be located in the first metal layer M3. The active portion of the thin film transistor T included in the shift register unit 101 may be located in the semiconductor layer 021, the gate electrode of the thin film transistor T and the scan line G included in the shift register unit 101 may be located in the gate metal layer M1, the source drain electrode of the thin film transistor T may be located in the source drain metal layer M2, the two electrodes of the capacitor included in the shift register unit 101 may be located in the gate metal layer M1 and the capacitor metal layer Mc, respectively, and the anode metal layer RE is used for manufacturing the anode of each display sub-pixel. It can be understood that the film structure and the light emitting principle of the display sub-pixel in the display panel 000 are not described in detail, and the film structure of the organic light emitting diode display panel in the related art can be specifically referred to for understanding.

In this embodiment, the first metal layer M3 where the first signal line 10 is located is disposed on a side of the transistor array layer 02 away from the substrate 01, and the specific first metal layer M3 where the first signal line 10 is located on a side of the source drain metal layer M2 where the source drain of the thin film transistor T is located away from the substrate 01, so that the film layer where the first signal line 20 is located avoids the transistor array layer 02 where the thin film transistor T is located, thereby saving the space of the transistor array layer 02, being beneficial to ensuring the size of the thin film transistor T of the transistor array layer 02 through enough space, ensuring the driving performance, and simultaneously enabling the space between the plurality of thin film transistors T included in the shift register unit 101 in the direction parallel to the plane of the substrate 01 to be reduced as much as possible, compressing the width of the non-display area NA in the direction parallel to the plane of the substrate 01 to the maximum extent, so that the space of the transistor array layer 02 in the direction parallel to the plane of the substrate 01 is not occupied by the first signal line 20 is avoided, and the narrower effect of the frame display panel 000 is realized.

Optionally, as shown in fig. 3 and fig. 6, fig. 6 is a schematic view of another partial cross-sectional structure of a region where a part of the shift register unit is located and a part of the display region in fig. 3, and a second metal layer M4 may be added to the display panel 000, where the second metal layer M4 is located on a side of the first metal layer M3 away from the substrate 01; the first connecting wire 50 connected with the first data line S1 is manufactured by adopting the second metal layer M4, so that short circuit with other signal wires of the display area AA is easily caused when the first connecting wire 50 is arranged by adopting the existing film layer of the display panel 000, and further, the wiring difficulty can be reduced, and the number of wire changing through holes in the display panel 000 can be reduced due to the fact that the whole first connecting wire 50 is manufactured by adopting the second metal layer M4, and the display quality is improved. Further alternatively, the first data line S1 may be located in the first metal layer M3, and the space between the first data line S1 and the transistor array layer 02 may be increased to reduce coupling.

Because the first signal line 20 and the first connection line 50 are arranged on the same layer, that is, the first signal line 20 is located on the second metal layer M4, at least the first metal layer M3 is further spaced between the first signal line 20 and the transistor array layer 02 in the non-display area NA, so that the width of the non-display area NA can be ensured to be compressed, the narrow frame is realized, and meanwhile, the first signal line 20 is further away from the transistor array layer 02 in which the thin film transistor T is located as far as possible in the direction Z perpendicular to the plane in which the substrate 01 is located, thereby being beneficial to reducing the possibility of signal coupling between the first signal line 20 and the thin film transistor T, avoiding the risk of bad driving caused by overlapped coupling, and being beneficial to further improving the display effect.

In some alternative embodiments, please refer to fig. 7 and fig. 8 in combination, fig. 7 is a schematic plan view of another plane structure of the display panel provided in the embodiment of the present invention, and fig. 8 is a schematic partial cross-sectional view of a portion of the display area and a portion of the area where the shift register unit is located in fig. 7, in which the first metal layer M3 includes a shielding portion 60, and the shielding portion 60 is located in a non-display area NA; the orthographic projection of the shielding portion 60 on the substrate 01 overlaps with the orthographic projection of the thin film transistor T included in the shift register unit 101 on the substrate 01.

In the present embodiment, the first metal layer M3 includes the shielding portion 60 in the area of the non-display area NA where the register unit 101 is located, and in the direction Z perpendicular to the plane where the substrate 01 is located, the shielding portion 60 overlaps with the thin film transistor T included in the shift register unit 101, and optionally, the orthographic projection of the shielding portion 60 on the substrate 01 covers the orthographic projection of the thin film transistor T included in the shift register unit 101 on the substrate 01, so that the shielding portion 60 of the first metal layer M3 may be disposed between the thin film transistor T included in the shift register unit 101 of the transistor array layer 02 and the first signal line 20 of the second metal layer M4, and the shielding portion 60 is used to separate the two, so as to reduce the overlapping coupling, avoid the mutual interference of signals between the two signals from affecting the respective driving performance, and further facilitate better improvement of the display quality.

Optionally, the shielding part 60 is connected with a fixed potential signal, so that the problem that the shielding part 60 is not connected with any electric signal, namely, floating signal interference occurs when floating can be avoided, and the influence of the floating of the shielding part 60 on the signal transmission of the first signal line 20 above and the thin film transistor T below can be avoided, thereby being beneficial to ensuring the display effect.

Alternatively, in the non-display area NA, the shielding part 60 is insulated from the thin film transistor T included in the shift register unit 101, and the shielding part 60 is insulated from the first signal line 20, so that mutual interference between the three can be avoided, and shielding performance of the shielding part 60 is affected.

In some alternative embodiments, please refer to fig. 7, 9 and 10 in combination, fig. 9 is a schematic diagram of an electrical connection structure of a pixel circuit and a light emitting element included in the display area in fig. 7, and fig. 10 is a schematic diagram of another partial cross-sectional structure of a region where a part of the shift register unit is located and a part of the display area in fig. 7, in which the display area AA includes a plurality of pixel circuits 70, and the pixel circuits 70 are connected to the low power supply signal Vpvee through the shielding portion 60 of the non-display area NA.

The present embodiment illustrates that the display area AA of the display panel 000 may include a plurality of display sub-pixels including the pixel circuit 70 and the light emitting element 80 electrically connected, alternatively, the pixel circuit 70 may be an electrical connection structure including 7 transistors and 1 capacitor as shown in fig. 9, and the 7 transistors and 1 capacitor may be fabricated using the transistor array layer 02, that is, the pixel circuit 70 includes transistors and the shift register unit 101 of the non-display area NA includes the thin film transistor T may be fabricated using the same film layer and the same process. It should be understood that fig. 9 of the present embodiment is merely an example of one electrical connection structure of the pixel circuit 70 and the light emitting element 80, and the pixel circuit of the display area AA includes, but is not limited to, this but may be other electrical connection structures, which are not limited to this embodiment. The pixel circuit 70 is connected to a scanning line, a data line, or the like, respectively, to realize a display light emitting effect of the light emitting element 80 in the display panel 000. It will be appreciated that the structure and the working principle of the pixel circuit in the display sub-pixel are not limited, and the sub-pixel structure of the display panel in the related art may be specifically referred to for understanding.

Taking the electrical connection structure of the pixel circuit 70 and the light emitting element 80 illustrated in fig. 9 as an example, the pixel circuit 70 needs to be connected to the low power signal Vpvee, and the cathode of the optional light emitting element 80 needs to be connected to the low power signal Vpvee. In this embodiment, the pixel circuit 70 is configured to access the low power supply signal Vpvee through the shielding portion 60 of the non-display area NA, that is, the cathode of the light emitting element 80 is electrically connected with the shielding portion 60 of the non-display area NA, the cathode layer 04 of the display area AA is located at one side of the anode metal layer 03 away from the substrate 01, the cathode layer 04 of the display area AA is accessed to the low power supply signal Vpvee through a negative power supply signal line (not illustrated in the drawing) disposed in the display area AA, and the negative power supply signal line may adopt the first metal layer M3 and/or the second metal layer M4, and then is electrically connected with the shielding portion 60 after being connected to the non-display area NA; alternatively, the cathode layer 04 of the display area AA may be directly connected to the non-display area NA and then electrically connected to the shielding portion 60, which is not limited in this embodiment. The present embodiment uses the shielding part 60 disposed in the non-display area NA as the negative power bus of the non-display area NA by multiplexing, so as to electrically connect the shielding part 60 multiplexed as the negative power bus with the driving chip or the flexible circuit board that is subsequently bound to the display panel 000, and the negative power signal port of the driving chip or the flexible circuit board provides the negative power signal for the negative power signal line of the display area AA through the shielding part 60 of the non-display area NA, and also ensures that the shielding part 60 accesses the negative power signal of the fixed potential, thereby ensuring the shielding effect between the thin film transistor T and the first signal line 20 included in the shift register unit 101.

In some alternative embodiments, please continue to refer to fig. 7 and 8, in this embodiment, the shielding portion 60 includes a plurality of hollowed holes 60K, and the thin film transistor T included in the shift register unit 101 of the non-display area NA is connected to the first signal line 20 through the hollowed holes 60K.

The present embodiment explains that the shift register unit 101 of the non-display area NA includes the thin film transistor T that needs to be connected to the first signal line 20 to supply the driving signal to the shift register unit 101 through the first signal line 20. The source or drain of at least one thin film transistor T as included in the shift register unit 101 is electrically connected to the first signal line 20. In this embodiment, the shielding portion 60 includes a plurality of hollowed holes 60K, and the source or drain electrode of at least one thin film transistor T included in the shift register unit 101 is connected to the first signal line 20 through the hollowed holes 60K, that is, the hollowed holes 60K are formed by punching holes in the through holes where the source or drain electrode of the thin film transistor T is connected to the first signal line 20, and the hollowed holes 60K penetrate through the thickness of the shielding portion 60, so that when the first metal layer M3 where the shielding portion 60 is located between the transistor array layer 02 and the second metal layer M4 where the first signal line 20 is located, the source or drain electrode of the thin film transistor T is electrically connected to the first signal line 20 to cause a short circuit with the shielding portion 60, thereby affecting the shielding performance of the shielding portion 60 itself, thereby being beneficial to further ensuring the display quality.

Optionally, as shown in fig. 7 and 8, in this embodiment, the shielding portion 60 outside the hollowed-out hole 60K has a whole surface structure, so that the manufacturing difficulty of the shielding portion 60 outside the hollowed-out hole 60K can be simplified, the overall manufacturing efficiency of the panel can be improved, and the shielding effect of the shielding portion 60 outside the hollowed-out hole 60K between the transistor array layer 02 where the thin film transistor T is located and the second metal layer M4 where the first signal line 20 is located can be enhanced, so that the driving performance of the panel can be better ensured.

In some alternative embodiments, please refer to fig. 11, fig. 11 is a schematic plan view of a display device according to an embodiment of the present invention, and the display device 111 according to the embodiment of the present invention includes the display panel 000 according to the above embodiment of the present invention. The embodiment of fig. 11 is only an example of a mobile phone, and the display device 111 is described, and it is to be understood that the display device 111 provided in the embodiment of the present invention may be other display devices 111 having a display function, such as a computer, a television, and a vehicle-mounted display device, which is not particularly limited in the present invention. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention, and the specific description of the display panel 000 in the above embodiments may be referred to specifically, and this embodiment is not repeated here.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising: a display region and a non-display region disposed at least partially around the display region;

the non-display area comprises a scanning driving circuit and a plurality of first signal lines connected with the scanning driving circuit; the scanning driving circuit comprises a plurality of cascaded shift register units, wherein each shift register unit comprises a plurality of signal input ends, and the signal input ends are connected with the first signal lines;

the shift register unit includes a plurality of thin film transistors;

the display panel comprises a substrate and a transistor array layer positioned on one side of the substrate, and the thin film transistor is positioned on the transistor array layer;

the film layer where the first signal line is located at one side, far away from the substrate, of the transistor array layer.

2. The display panel of claim 1, wherein the display area includes a plurality of data lines extending in a first direction;

the non-display area comprises a binding area, and the binding area is positioned on one side of the display area in the first direction;

the binding area comprises a plurality of conductive pads, the conductive pads are electrically connected with fan-out wires, and the fan-out wires are positioned in the non-display area;

the data lines comprise first data lines, the first data lines are electrically connected with the fan-out wiring through at least one first connecting line, and the first connecting lines are located in the display area.

3. The display panel according to claim 2, wherein the first signal line is provided in the same layer as the first connection line.

4. The display panel of claim 1, comprising a first metal layer and a second metal layer, the first metal layer being on a side of the transistor array layer remote from the substrate, the second metal layer being on a side of the first metal layer remote from the substrate;

the first signal line is positioned on the second metal layer.

5. The display panel of claim 4, wherein the first metal layer comprises a shielding portion, the shielding portion being located in the non-display region;

an orthographic projection of the shielding part on the substrate overlaps with an orthographic projection of the thin film transistor on the substrate.

6. The display panel according to claim 5, wherein the shielding portion is connected to a fixed potential signal.

7. The display panel of claim 5, wherein the display area includes a plurality of pixel circuits that are connected to a low power signal through the shield.

8. The display panel according to claim 5, wherein the shielding portion is insulated from the thin film transistor, and wherein the shielding portion is insulated from the first signal line.

9. The display panel according to claim 5, wherein the shielding portion includes a plurality of hollowed holes, and the thin film transistor is connected to the first signal line through the hollowed holes.

10. The display panel according to claim 9, wherein the shielding portion other than the hollowed-out hole has a whole surface structure in the non-display region.

11. The display panel according to claim 1, wherein the plurality of first signal lines includes at least a clock control signal line, a start shift signal line, and a reset signal line.

12. A display device comprising the display panel of any one of claims 1-11.