Disclosure of Invention
The invention solves the technical problems that: the defects of the prior art are overcome, the imaging resolution is provided with the configurable multi-band TDI-CMOS image sensor, the requirements of a system on resolution and signal to noise ratio are met, and the resource occupation of off-chip data storage and data processing is reduced.
The invention aims at realizing the following technical scheme: an imaging resolution configurable multi-band TDI-CMOS image sensor, comprising: the device comprises a multispectral pixel array, a time sequence driving circuit, a digital binding readout circuit and a configuration circuit; the multi-spectrum pixel array converts the optical signals into image electric signals and transmits the image electric signals to the digital binding readout circuit; the digital binding readout circuit receives the image electric signal, carries out digital quantization and horizontal digital binding operation on the image electric signal, and outputs a processed digital image; the time sequence driving circuit provides a normal working time sequence for the multispectral pixel array; the configuration circuit sets the working modes of the time sequence driving circuit and the digital binding readout circuit, and detects the working state of the circuit.
In the above imaging resolution configurable multi-band TDI-CMOS image sensor, the multi-band pixel array includes a plurality of band partitions; wherein each pixel in each spectral bin is identical in structure, each pixel in each spectral bin is equal in size, and the pixel spacing in each spectral bin is equal.
In the above-mentioned imaging resolution configurable multi-band TDI-CMOS image sensor, each band partition is a rectangular area, wherein the number of pixels in the horizontal direction of the rectangular area determines the maximum resolution n of the image sensor in the non-binning mode, and the number of pixels in the vertical direction of the rectangular area determines the maximum TDI progression m of the image sensor in the non-binning mode.
In the above imaging resolution configurable multi-band TDI-CMOS image sensor, the timing driving circuit includes a plurality of sub-timing driving circuits, where the number of sub-timing driving circuits is equal to the number of band partitions; each sub-timing driving circuit provides a timing of normal operation to a spectrum segment partition corresponding to each sub-timing driving circuit.
In the above imaging resolution configurable multi-band TDI-CMOS image sensor, the digital binding readout circuit includes a programmable gain amplifier, an analog-to-digital converter, a horizontal digital domain binding unit, a data processing circuit, and an image interface circuit; the programmable gain amplifier amplifies the image electric signal to obtain an amplified image electric signal, and the amplified image electric signal is transmitted to the analog-digital converter; the analog-digital converter receives the amplified image electric signal, converts the amplified image electric signal into an image digital signal, and transmits the image digital signal to the horizontal digital domain binding unit; the horizontal digital domain binding unit receives the image digital signal, carries out horizontal digital binding operation on the image digital signal according to the working mode of the data processing circuit, obtains a processed digital image, and transmits the processed digital image to the image interface circuit.
In the above-mentioned imaging resolution configurable multi-band TDI-CMOS image sensor, the mode selection bit 1 and the mode selection bit 0 of the operation mode of the data processing circuit are assigned with "X0" to represent a non-binning output mode, wherein X represents an arbitrary value of 0 or 1, assigned with "01" to represent a horizontal X2 binning output mode, and assigned with "11" to represent a horizontal X4 binning output mode.
In the imaging resolution configurable multi-spectral TDI-CMOS image sensor, the horizontal digital domain binding unit comprises a first-stage double-circuit data selection circuit, a second-stage double-circuit data selection circuit, a 1-stage adder, a 2-stage adder and a saturation judgment circuit; wherein the analog-digital converter is four paths; the image digital signals of the four-way analog-digital converter pass through a first-stage two-way data selection circuit, when a mode selection bit 0 is set to be 0, the four-way image digital signals are directly output, and when the mode selection bit 0 is set to be 1, the first two-way four-way image digital signals and the second two-way four-way image digital signals in the four-way image digital signals are respectively input into a 1-stage adder for addition, and the addition result is input into a second-stage two-way data selection circuit; when the mode selection bit 1 is set to 0, two addition results pass through a saturation judging circuit, and if the result is saturated, a saturation flag bit is set; when the mode selection bit 1 is set to be 1, two summation results are input into a 2-stage adder for summation, and the summation passes through a saturation judging circuit, and if the result is saturated, a saturation flag bit is set.
In the imaging resolution configurable multi-band TDI-CMOS image sensor, pixels in the band partition adopt a CCD working principle, and each pixel is internally provided with a plurality of transfer electrodes, and the pixels are divided into a two-phase CCD, a three-phase CCD and a four-phase CCD.
In the imaging resolution configurable multi-band TDI-CMOS image sensor, the pixels are two-phase CCD, the TDI level is 32 levels, wherein the pixel 1 level pixels of 2 levels to 32 levels output signals to the pixel output circuit through controlling the TX gate signals of the transmission tube TG, and the charge signals are converted into analog voltage signals through the pixel circuit to be output.
In the above imaging resolution configurable multi-band TDI-CMOS image sensor, the digital binning readout circuitry includes a top digital binning readout circuit and a bottom digital binning readout circuit; wherein the top digital binding readout circuit is located at the top of the multi-band pixel array and the bottom digital binding readout circuit is located at the bottom of the multi-band pixel array.
Compared with the prior art, the invention has the following beneficial effects:
(1) The method can be applied to the field of aerospace to-ground multispectral remote sensing imaging, different scenes are imaged by adopting different resolutions, the signal to noise ratio of a system is improved, and meanwhile, the off-chip mass data processing pressure is reduced;
(2) According to the invention, pixel bridging is realized in the image sensor chip, so that the processing pressure of the data outside the chip of the mass image sensor is reduced, the data do not need to be subjected to off-chip bridging operation in a peripheral FPGA, the output data quantity is reduced, and the occupation of off-chip storage and processing resources is reduced.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
With the continuous progress of semiconductor process technology, CMOS image sensors have fully replaced CCDs in the civilian field, and TDI-CMOS image sensors have also begun to gradually replace TDI-CCDs in the high-end field.
The technical route for realizing TDI comprises charge domain accumulation, analog domain accumulation and digital domain accumulation, and the charge domain accumulation process does not introduce extra noise, so that the accumulation speed is high, and the method is the most mainstream technology; the area of the noise circuit layout introduced by the analog accumulation operational amplifier is large, and the analog accumulation operational amplifier only appears in academic research; the digital domain accumulation has a larger requirement on data storage and processing resources, and mainly an area array CMOS realizes digital TDI by using the digital domain accumulation.
The most typical application of the TDI technology is the aerospace remote sensing field, the special spectrum and resolution are selected according to the characteristics of the scenery, the reflectivities of different sceneries are different, the application scenes are different, the special requirements on the number of imaged spectral bands, the imaging spatial resolution and the signal to noise ratio are met, no TDI-CMOS image sensor with multi-spectral band and imaging resolution capable of being configured according to the application exists at present, if a scene with high signal to noise ratio requirement exists, the digital binding operation is needed to be carried out outside the chip, and the occupation of storage and processing resources of an off-chip processor is large.
Fig. 1 is a block diagram of an imaging resolution configurable multi-band TDI-CMOS image sensor provided by an embodiment of the present invention. As shown in fig. 1, the imaging resolution configurable multi-band TDI-CMOS image sensor includes a multi-band pixel array, a timing drive circuit, a digital binning readout circuit, and a configuration circuit; wherein,,
the multispectral pixel array converts the optical signals into image electric signals and transmits the image electric signals to the digital binding readout circuit; the digital binding readout circuit receives the image electric signal, carries out digital quantization and horizontal digital binding operation on the image electric signal, and outputs a processed digital image; the time sequence driving circuit provides normal working time sequence for the multispectral pixel array; the configuration circuit sets the working modes of the time sequence driving circuit and the digital binding readout circuit, and detects the working state of the circuit.
The multi-spectrum pixel array comprises a plurality of spectrum subareas, the number of the spectrum subareas can be designed according to application requirements and manufacturing cost, and the pixel structure, the pixel size and the pixel spacing of each spectrum subarea are equal. The function of which is to convert an optical signal into an electrical signal.
The pixels in the spectrum partition adopt CCD working principle, and charge transfer and charge accumulation in the vertical direction are carried out on the charge signals after photoelectric conversion under the action of electrode time sequence.
The time sequence driving circuit comprises a plurality of sub time sequence driving circuits, each sub time sequence driving circuit is identical, and the number of the sub circuits is consistent with the number of spectrum segment partitions in the multi-spectrum segment pixel array. The time sequence driving circuit is used for providing time sequence for normal operation of the multi-spectrum pixel array. Each sub-timing driving circuit provides a timing of normal operation to a spectrum segment partition corresponding to each sub-timing driving circuit.
As shown in fig. 4, the digital binding readout circuit includes a programmable gain amplifier, an analog-to-digital converter, a horizontal digital domain binding unit, a data processing circuit, and an image interface circuit; wherein,,
the programmable gain amplifier amplifies the image electric signal to obtain an amplified image electric signal, and the amplified image electric signal is transmitted to the analog-digital converter; the analog-digital converter receives the amplified image electric signal, converts the amplified image electric signal into an image digital signal, and transmits the image digital signal to the horizontal digital domain binding unit; the horizontal digital domain binding unit receives the image digital signal, carries out horizontal digital binding operation on the image digital signal according to the working mode of the data processing circuit, obtains a processed digital image, and transmits the processed digital image to the image interface circuit.
The configuration circuit comprises a register and a bus configuration circuit, and is used for setting the working modes of the timing driving circuit and the reading circuit and detecting the working state of the circuit.
The configuration circuit is connected with the time sequence driving circuit and the digital binding readout circuit, and can respectively configure the working modes of each sub-time sequence circuit in the time sequence circuit and all the working modes of the digital binding readout circuit.
The time sequence driving circuit is positioned at the left side of the pixel, and the output driving signal is connected with the corresponding multi-spectrum pixel array spectrum section partition to provide vertical transfer and readout time sequence signals for the pixel.
The digital canning readout circuit is positioned at the top and the bottom of the multispectral pixel array, is connected with each spectral region partition, and analog image signals output by the pixels are input to the PGA circuit in the digital canning readout circuit.
The imaging resolution configurable function is realized by an on-chip mixed domain binning technology, the mixed domain binning technology is realized by a vertical charge domain binning technology and a horizontal digital domain binning technology, and the binning modes of 1×1, 1×2, 2×2, 2×3, 4×4 and the like can be realized.
The charge domain binding technology in the vertical direction is switched by configuring the working mode of the time sequence driving circuit.
The horizontal digital domain binning technique is implemented by configuring the operation modes of the horizontal digital domain binning unit and the data processing circuit in the readout circuit.
Each spectrum segment of the multi-spectrum segment pixel array is a rectangular area, as shown in fig. 2, wherein the number of pixels in the horizontal direction determines the maximum resolution n of the image sensor in the non-binding mode, the vertical direction is the TDI direction in which the TDI image sensor works, and the number of pixels in the vertical direction determines the maximum TDI number m of the image sensor in the non-binding mode.
Fig. 3 is a single-column pixel array, wherein the pixel structure is a two-phase CCD, the TDI series is m-stage, the 1-stage pixel outputs a signal to the pixel output circuit through the transmission tube TG, and the charge signal is converted into an analog voltage signal output through the pixel circuit.
The digital binding readout circuit receives pixel output analog image data, the signals sequentially pass through the PGA, the ADC, the horizontal digital domain binding unit, the data processing circuit and the image interface circuit and are converted into digital image data, and the digital binding readout circuit can realize horizontal digital domain binding operation on the data.
The horizontal digital domain canning unit can process 4 paths of ADC output data, the configuration circuit selects a working mode through mode selection bit assignment, the horizontal digital domain canning unit can output non-canning data, horizontal x2 canning data and horizontal x 4b canning data, and the unit can judge whether the data after canning is saturated or not and output a saturation zone bit.
As shown in fig. 6, 1×1 indicates that no binning operation is performed, 1×2 indicates that two pixels in two vertical columns and two horizontal rows are subjected to a binning operation, 2×2 indicates that four pixels in two vertical columns and two horizontal rows are subjected to a binning operation, 2×3 indicates that 6 pixels in two vertical columns and three horizontal rows are subjected to a binning operation, and 4×4 indicates that 16 pixels in four vertical columns and four horizontal rows are subjected to a binning operation.
Fig. 7 illustrates a vertical x2 binding implementation in a cross-sectional view of a pixel structure, where driving signals are applied to two-phase CCD pixel electrodes PH1 and PH2, driving charge signals are transferred between pixels, and finally two pixel charge signals enter into an FD capacitor through a TX gate signal of a control transmission tube TG, are converted into analog voltage signals through a pixel output circuit, and after the signals are read out, the FD capacitor signals are emptied through a RST signal, and wait for the next package charge to enter.
Specifically, the imaging resolution of the multi-spectral TDI-CMOS image sensor with configurable imaging resolution is determined by considering the factors such as application requirement, manufacturing cost, working frequency, etc., and the implementation is illustrated by taking four-spectral-band, pixel size of 9 μm, maximum resolution of 3072 and maximum TDI series of 32 stages as examples.
The imaging resolution configurable multi-band TDI-CMOS image sensor is characterized by comprising a multi-band pixel array, a time sequence driving circuit, a digital binding readout circuit and a configuration circuit.
The multi-spectrum pixel array comprises four spectrum partitions, which are respectively defined as P, B, B2, B3 and B4, wherein each spectrum partition pixel structure, pixel size 9 mu m and pixel spacing 9 mu m, each spectrum region direction definition is shown in fig. 2, the number of pixels in the horizontal direction determines the maximum resolution 3072 of the image sensor in a non-binding mode, the vertical direction is the TDI direction of the TDI image sensor, the number of pixels in the vertical direction determines the maximum TDI stage 32 of the image sensor in the non-binding mode, the maximum resolution value generally requires a multiple of 4, and the stage value generally requires a multiple of 8. The multi-band pixel array functions to convert an optical signal into an electrical signal.
The pixels in the spectrum partition adopt the working principle of CCD, each pixel is internally provided with a plurality of transfer electrodes, and the transfer electrodes are generally divided into two-phase CCD, three-phase CCD and four-phase CCD, the two-phase CCD is taken as an example for illustration in the embodiment, and each pixel is provided with two electrodes PH1 and PH2 as shown in figure 3. And carrying out charge transfer and charge accumulation in the vertical direction on the charge signal after photoelectric conversion under the action of the CCD electrode time sequence.
As shown in FIG. 3, the single-column pixel array in the spectrum partition has a pixel structure of a two-phase CCD, the TDI stage is 32 stages, wherein the pixel 1 stage pixels of 2 stages to 32 stages output signals to a pixel output circuit through a TX gate signal of a control transmission tube TG, and charge signals are converted into analog voltage signals through the pixel circuit to be output.
The time sequence driving circuit comprises a plurality of sub time sequence driving circuits, each sub time sequence driving circuit is identical, and the number of the sub circuits is consistent with the number of spectrum segment partitions in the multi-spectrum segment pixel array. The time sequence driving circuit is used for providing time sequence for normal operation of the multi-spectrum pixel array.
The digital binding readout circuit includes a Programmable Gain Amplifier (PGA), an analog-to-digital converter (ADC), a horizontal digital domain binding unit, a data processing circuit, and an image interface circuit, as shown in fig. 4. The digital canning readout circuit is used for carrying out digital quantization and horizontal digital canning operation on the image signal and outputting the processed digital image.
The configuration circuit comprises a register and a bus configuration circuit, and is used for setting the working modes of the timing driving circuit and the digital binding readout circuit and detecting the working state of the circuit.
The configuration circuit is connected with the time sequence driving circuit and the digital binding readout circuit, and can respectively configure the working modes of each sub-time sequence circuit in the time sequence circuit and all the working modes of the digital binding readout circuit.
The sub-timing circuit is positioned at the left side of the pixel, and the output driving signal is connected with the corresponding multi-spectrum pixel array spectrum partition to provide vertical transfer and readout timing signals for the pixel.
The digital binding readout circuit is positioned at the top and the bottom of the multispectral pixel array, the top digital binding readout circuit processes the P-band and B1-band image data, the bottom digital binding readout circuit processes the B2-band and B3-band image data, and the analog image signals output by the pixels are input to the PGA circuit in the digital binding readout circuit.
The imaging resolution may be configured by an on-chip hybrid domain binning technique, the hybrid domain binning technique is implemented by a vertical charge domain binning technique and a horizontal digital domain binning technique, and a binning mode of 1×1, 1×2, 2×2, 2×3, 4×4, etc. may be implemented, as shown in fig. 6, 1×1 indicates that no binning operation is performed, 1×2 indicates that two pixels in a vertical column and two horizontal rows are subjected to a binning operation, 2×2 indicates that four pixels in a vertical column and two horizontal rows are subjected to a binning operation, 2×3 indicates that 6 pixels in a vertical column and three horizontal rows are subjected to a binning operation, and 4×4 indicates that 16 pixels in a vertical column and four horizontal rows are subjected to a binning operation.
The charge domain alignment technology in the vertical direction is switched by configuring the working mode of a time sequence driving circuit, taking vertical x2 alignment as an example, as shown in fig. 7, by applying driving signals to two-phase CCD pixel electrodes PH1 and PH2, charge signals are transferred between pixels, finally charges of two pixels enter into an FD capacitor through a transmission tube TG, the charges are converted into analog voltage signals through a pixel output circuit, and after the signals are read out, the FD capacitor signals are emptied through RST.
The horizontal digital domain binning technique is implemented by configuring the operation modes of the horizontal digital domain binning unit and the data processing circuit in the digital binning readout circuit, as shown in fig. 5, the mode select bit 1 and the mode select bit 0 assign "X0" to represent a non-binning output mode, where X represents an arbitrary value of 0 or 1, assign "01" to represent a horizontal X2 binning output mode, and assign "11" to represent a horizontal X4 binning output mode.
The horizontal digital domain binding unit, as shown in fig. 5, includes a two-way data selection circuit (MUX 2), a 1-stage adder, a 2-stage adder, and a saturation determination circuit. The quantized signals of the four paths of ADC are firstly subjected to MUX2, when the mode selection bit 0 is set to 0, the four paths of data are directly output to the unit circuit, when the mode selection bit 0 is set to 1, the first two paths and the second two paths of data are respectively input to the 1-level adder for addition, and the addition result is input to the second-level MUX2; when the mode selection bit 1 is set to 0, two addition results pass through the saturation judgment output unit, and if the result is saturated, a saturation flag bit is set; when the mode selection bit 1 is set to be 1, two summation results are input into a 2-stage adder for summation, and the summation passes through a saturation judgment output unit, and if the result is saturated, a saturation flag bit is set. The saturation flag bit is fed back to the PGA, and the optional device automatically adjusts the PGA gain, or by an external controller program of the image sensor.
A workflow of imaging resolution configuration is illustrated. Of the four spectral bands, P spectral band resolution 3072, B1 spectral band resolution 1536, B2 and B3 spectral band resolution 768 are required. According to the resolution requirement, the P spectrum band does not carry out the canning operation, the B1 spectrum band carries out the 2×2 canning operation, and the B2 and B3 spectrum bands carry out the 4×4 canning operation. The sub-timing circuit 1 is configured not to perform vertical charge domain binning, the sub-timing circuit 2 performs x2 vertical charge domain binning, and the sub-timing circuits 3 and 4 perform x 4 vertical charge domain binning. The top digital binding readout circuit is configured, the P spectrum segment corresponds to the digital binding readout circuit configuration mode selection bit amplitude value of "00", the B1 spectrum segment corresponds to the digital binding readout circuit configuration mode selection bit amplitude value of "01", the B2 and B3 spectrum segments correspond to the digital binding readout circuit configuration mode selection bit amplitude value of "11", and TDI imaging can be performed after configuration is completed.
This embodiment brings new modes for imaging system design and load application. For the same imaging system, the embodiment can configure different spectral regions of the device to be in different imaging resolutions according to different imaging scene characteristics and spectral reflection characteristics so as to meet the requirements of system resolution and signal-to-noise ratio.
In the embodiment, as the imaging resolution can be flexibly configured, the same imaging electronics system can be used as a mature product to be applied to different imaging systems, so that the need of developing one set of imaging electronics system independently for one imaging system is avoided, and the development cost is saved. According to the embodiment, pixel bridging is realized in the image sensor chip, so that the processing pressure of the data outside the chip of the mass image sensor is reduced, the data do not need to be subjected to off-chip bridging operation in the peripheral FPGA, the output data quantity is reduced, and the occupation of off-chip storage and processing resources is reduced. The working mode of the device can be configured according to the pixel size requirement of the non-square pixel, repeated design is not needed, and development cost and development period are saved.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.