CN115523945B

CN115523945B - Sensor circuit and electric equipment with same

Info

Publication number: CN115523945B
Application number: CN202211497327.5A
Authority: CN
Inventors: 秦文辉; 袁辅德
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2022-11-28
Filing date: 2022-11-28
Publication date: 2023-05-05
Anticipated expiration: 2042-11-28
Also published as: CN115523945A

Abstract

The invention discloses a sensor circuit and electric equipment with the same, wherein the sensor circuit comprises: the circuit comprises a first sensing unit, a second sensing unit and a suppression circuit, wherein the suppression circuit comprises a first regulating circuit and a second regulating circuit which are respectively connected to the output end of the circuit; the first sensing unit is connected to the first regulating circuit to form a first sensing branch, and the second sensing unit is connected to the second regulating circuit to form a second sensing branch; the first sensing branch is configured to have a low bandwidth and a high gain, and the second sensing branch is configured to have a high bandwidth and a low gain; the first sensing branch is configured to output a high gain signal that attenuates at least low bandwidth drift formed by the second sensing branch on the circuit output. The sensor circuit provided by the invention can be used for combining the advantages of adaptability to high-bandwidth working requirements and low-voltage drift.

Description

Sensor circuit and electric equipment with same

Technical Field

The invention relates to the technical field of data measurement, in particular to a sensor circuit and electric equipment with the same.

Background

Data measurement, particularly measurement of electrical parameters, is always a focus of attention in the field, accurate measurement results, simple measurement means and high-integration sensor circuit configuration, and is helpful to realize more complex and efficient operation and feedback regulation processes. Wherein the measurement of the current is one of these data measurements. Current measurement has applications in a variety of scenarios such as motor servo control, circuit protection, power control, and temperature regulation. Compared with the traditional contact type measurement scheme, the magnetic field is used for realizing the non-contact type current measurement, and the non-contact type measurement scheme is typically built by adopting a Hall device.

However, the sensitivity of hall devices is generally large relative to the sense signal, resulting in poor measurement accuracy of the built sensor circuit. In the prior art, a static method is adopted to improve the precision of a sensor circuit, and a plurality of Hall devices are connected in parallel to enable offset voltages of the Hall devices to be offset, but the offset voltages close to the amplitude of an induction signal are remained more, and the overall precision of the sensor circuit still cannot be improved. In the other prior art, a dynamic method is adopted to improve the precision of the sensor circuit, but because the offset voltage is modulated to high frequency, the offset voltage becomes high-frequency ripple superimposed on the signal, and instead, certain operation is needed to eliminate the ripple, so that the precision improvement effect is still unsatisfactory.

The technical scheme can not only effectively solve the precision problem of the sensor circuit, but also can not adapt to the requirement of high bandwidth due to the limitations of signal sampling and signal processing architecture.

Disclosure of Invention

One of the objectives of the present invention is to provide a sensor circuit, which solves the problem that the sensor circuit in the prior art cannot achieve both high measurement accuracy and high bandwidth adaptability.

One of the purposes of the invention is to provide electric equipment.

To achieve one of the above objects, an embodiment of the present invention provides a sensor circuit, including: the circuit comprises a first sensing unit, a second sensing unit and a suppression circuit, wherein the suppression circuit comprises a first regulating circuit and a second regulating circuit which are respectively connected to the output end of the circuit; the first sensing unit is connected to the first regulating circuit to form a first sensing branch, and the second sensing unit is connected to the second regulating circuit to form a second sensing branch; the first sensing branch is configured to have a low bandwidth and a high gain, and the second sensing branch is configured to have a high bandwidth and a low gain; the first sensing branch is configured to output a high gain signal that attenuates at least low bandwidth drift formed by the second sensing branch on the circuit output.

As a further improvement of an embodiment of the present invention, the first adjusting circuit includes a first chopper, a first transconductance amplifier, a second chopper, and a drift filter circuit connected in sequence, and an output end of the drift filter circuit is connected to an output end of the circuit; the second adjusting circuit comprises a second transconductance amplifier, and the output end of the second transconductance amplifier is connected to the output end of the drift filter circuit.

As a further improvement of an embodiment of the present invention, the drift filter circuit includes a third transconductance amplifier, a first filter capacitor, and a second filter capacitor; one end of the first filter capacitor is connected with the non-inverting input end of the third transconductance amplifier, and the other end of the first filter capacitor is connected between the non-inverting output end of the third transconductance amplifier and the circuit output end; one end of the second filter capacitor is connected with the inverting input end of the third transconductance amplifier, and the other end of the second filter capacitor is connected between the inverting output end of the third transconductance amplifier and the circuit output end.

As a further improvement of an embodiment of the present invention, a first trap is provided between the first transconductance amplifier and the third transconductance amplifier.

As a further improvement of an embodiment of the present invention, the first adjusting circuit further includes a noise filter circuit, and the noise filter circuit is disposed between the drift filter circuit and the circuit output terminal; the noise filter circuit comprises a first integrating capacitor and a second integrating capacitor, and the sum of the capacitance values of the first filtering capacitor and the second filtering capacitor is larger than the sum of the capacitance values of the first integrating capacitor and the second integrating capacitor.

As a further improvement of an embodiment of the present invention, the noise filter circuit includes a fourth transconductance amplifier; one end of the first integrating capacitor is connected with the non-inverting input end of the fourth transconductance amplifier, and the other end of the first integrating capacitor is connected with the inverting output end of the fourth transconductance amplifier; one end of the second integrating capacitor is connected with the inverting input end of the fourth transconductance amplifier, and the other end of the second integrating capacitor is connected with the non-inverting output end of the fourth transconductance amplifier; the other end of the first filter capacitor, which is not connected with the non-inverting input end of the third transconductance amplifier, is connected to the non-inverting output end of the fourth transconductance amplifier; the other end of the second filter capacitor, which is not connected with the inverting input end of the third transconductance amplifier, is connected to the inverting output end of the fourth transconductance amplifier.

As a further improvement of an embodiment of the present invention, the inverting output terminal of the first transconductance amplifier is connected to the non-inverting input terminal of the third transconductance amplifier through the second chopper, and the inverting output terminal of the third transconductance amplifier is connected to the non-inverting input terminal of the fourth transconductance amplifier, so as to form a first inverting branch of the first adjusting circuit; the positive phase output end of the first transconductance amplifier is connected to the negative phase input end of the third transconductance amplifier through the second chopper, and the positive phase output end of the third transconductance amplifier is connected to the negative phase input end of the fourth transconductance amplifier to form a first positive phase branch of the first regulating circuit; the output end of the first normal phase branch forms a circuit normal phase output end of the circuit output end, and the output end of the first reverse phase branch forms a circuit reverse phase output end of the circuit output end; the input end of the first normal phase branch forms a first normal phase input end of the circuit input end of the suppression circuit, and the input end of the first reverse phase branch forms a first reverse phase input end of the circuit input end.

As a further improvement of an embodiment of the present invention, the suppression circuit further includes a third adjusting circuit, the third adjusting circuit includes a third chopper, a fifth transconductance amplifier, and a fourth chopper that are sequentially connected, and a positive phase output terminal of the fifth transconductance amplifier is connected to a positive phase input terminal of the third transconductance amplifier through the fourth chopper, so as to form a third positive phase branch of the third adjusting circuit; the inverting output end of the fifth transconductance amplifier is connected to the inverting input end of the third transconductance amplifier through the fourth chopper to form a third inverting branch of the third regulating circuit; the input end of the third normal phase branch forms a third normal phase input end of the circuit input end of the suppression circuit, and the input end of the third reverse phase branch forms a third reverse phase input end of the circuit input end.

As a further improvement of an embodiment of the present invention, a positive phase output end of the second transconductance amplifier is connected to a positive phase input end of the fourth transconductance amplifier, so as to form a second positive phase branch of the second adjusting circuit; the input end of the second normal phase branch forms a second normal phase input end of the circuit input end of the suppression circuit; the inverting output end of the second transconductance amplifier is connected with the inverting input end of the fourth transconductance amplifier to form a second inverting branch of the second regulating circuit; the input of the second inverting branch forms a second inverting input of the circuit input.

As a further improvement of an embodiment of the present invention, the suppression circuit further includes a fourth adjusting circuit, the fourth adjusting circuit including a sixth transconductance amplifier; the positive phase output end of the sixth transconductance amplifier is connected with the negative phase input end of the fourth transconductance amplifier to form a fourth positive phase branch of the fourth regulating circuit; the input end of the fourth normal phase branch forms a fourth normal phase input end of the circuit input end of the suppression circuit; the inverting output end of the sixth transconductance amplifier is connected with the non-inverting input end of the fourth transconductance amplifier to form a fourth inverting branch of the fourth regulating circuit; the input of the fourth inverting branch forms a fourth inverting input of the circuit input.

As a further improvement of an embodiment of the present invention, the suppression circuit further includes a first feedback circuit corresponding to the first adjusting circuit, the first feedback circuit being disposed between the circuit output terminal and the output terminal of the second chopper, the first feedback circuit including a fifth chopper, a seventh transconductance amplifier, and a sixth chopper connected in sequence.

As a further improvement of an embodiment of the present invention, the suppression circuit further includes a gain adjustment circuit disposed between the first feedback circuit and the circuit output, the gain adjustment circuit being configured to adjust a gain of the suppression circuit.

As a further improvement of an embodiment of the present invention, the gain adjusting circuit includes a first configuration resistor connected in series to a first inverting branch in the first adjusting circuit, a second configuration resistor connected in series to a first non-inverting branch in the first adjusting circuit, and a third configuration resistor connected in parallel between the first inverting branch and the first non-inverting branch.

As a further improvement of an embodiment of the present invention, the suppression circuit further includes a second feedback circuit corresponding to the second adjusting circuit, the second feedback circuit being disposed between the circuit output terminal and the output terminal of the second transconductance amplifier, the second feedback circuit including an eighth transconductance amplifier.

As a further improvement of an embodiment of the present invention, the suppression circuit further includes a gain adjustment circuit disposed between the second feedback circuit and the circuit output terminal, the gain adjustment circuit being configured to adjust a gain of the suppression circuit.

As a further improvement of an embodiment of the present invention, the suppression circuit further includes a ripple cancellation circuit; the inverting voltage input end of the ripple cancellation circuit is connected with the non-inverting current output end and is connected to the inverting output end of the first transconductance amplifier; the ripple cancellation circuit has a non-inverting voltage input connected to the inverting current output and to the non-inverting output of the first transconductance amplifier.

As a further improvement of an embodiment of the present invention, the ripple cancellation circuit includes an integrating chopper circuit.

As a further improvement of an embodiment of the present invention, the integrating chopper circuit includes a seventh chopper, a ninth transconductance amplifier, a tenth transconductance amplifier, an eighth chopper, a third integrating capacitor, and a fourth integrating capacitor; the third integrating capacitor is arranged between the inverting input end and the non-inverting output end of the ninth transconductance amplifier, and the fourth integrating capacitor is arranged between the non-inverting input end and the inverting output end of the ninth transconductance amplifier.

As a further improvement of an embodiment of the present invention, the integrating chopper circuit further includes at least one of a configuration resistor and an eleventh transconductance amplifier; the configuration resistor comprises a fourth configuration resistor and a fifth configuration resistor, the fourth configuration resistor is connected with the inverting input end of the ninth transconductance amplifier, and the fifth configuration resistor is connected with the non-inverting input end of the ninth transconductance amplifier; the non-inverting output end of the eleventh transconductance amplifier is connected with the inverting input end of the ninth transconductance amplifier, and the inverting output end of the eleventh transconductance amplifier is connected with the non-inverting input end of the ninth transconductance amplifier.

As a further improvement of an embodiment of the present invention, the ripple cancellation circuit includes at least one of a pre-high-pass filter circuit, a pre-amplification circuit, and a second trap; the front high-pass filter circuit comprises a third filter capacitor, a fourth filter capacitor, a first filter resistor and a second filter resistor; the pre-amplifier circuit includes a twelfth transconductance amplifier.

As a further improvement of an embodiment of the present invention, the sensor circuit further includes a first switching circuit disposed between the first sensing unit and the suppressing circuit, the first switching circuit including a driving switch group and a signal switch group; the driving switch group is at least used for driving the first sensing unit, and the signal switch group is at least used for outputting signal voltage generated after the first sensing unit is driven to the suppression circuit.

As a further improvement of an embodiment of the present invention, the first sensing unit includes a first output node, a second output node, a third output node, and a fourth output node; the driving switch group comprises a first driving branch, a second driving branch, a third driving branch and a fourth driving branch which are mutually connected in parallel, wherein the first driving branch is connected with a first driving switch in series, the second driving branch is connected with a second driving switch in series, the third driving branch is connected with a third driving switch in series, and the fourth driving branch is connected with a fourth driving switch in series; the signal switch group comprises a first signal branch, a second signal branch, a third signal branch and a fourth signal branch which are mutually connected in parallel, wherein the first signal branch is connected with a fourth signal switch in series, the second signal branch is connected with the first signal switch in series, the third signal branch is connected with the second signal switch in series, and the fourth signal branch is connected with the third signal switch in series; the first output node is connected to the first driving branch and the first signal branch, the second output node is connected to the second driving branch and the second signal branch, the third output node is connected to the third driving branch and the third signal branch, and the fourth output node is connected to the fourth driving branch and the fourth signal branch; the action time sequences of the first driving switch and the first signal switch are basically the same, the action time sequences of the second driving switch and the second signal switch are basically the same, the action time sequences of the third driving switch and the third signal switch are basically the same, and the action time sequences of the fourth driving switch and the fourth signal switch are basically the same.

As a further improvement of an embodiment of the present invention, the first driving branch is further connected in series with a seventh driving switch, and the seventh driving switch and the third driving switch act synchronously; the first signal branch is also connected in series with a sixth signal switch, and the sixth signal switch and the second signal switch synchronously act; the first output node is connected between the first driving switch and the seventh driving switch and between the fourth signal switch and the sixth signal switch; the second driving branch is also connected in series with an eighth driving switch, and the eighth driving switch and the fourth driving switch synchronously act; the second signal branch is also connected in series with a seventh signal switch, and the seventh signal switch and the third signal switch synchronously act; the second output node is connected between the second driving switch and the eighth driving switch and between the first signal switch and the seventh signal switch; the third driving branch is also connected in series with a fifth driving switch, and the fifth driving switch and the first driving switch synchronously act; the third signal branch is also connected in series with an eighth signal switch, and the eighth signal switch and the fourth signal switch synchronously act; the third output node is connected between the third driving switch and the fifth driving switch and between the second signal switch and the eighth signal switch; the fourth driving branch is also connected in series with a sixth driving switch, and the sixth driving switch and the second driving switch synchronously act; the fourth signal branch is also connected in series with a fifth signal switch, and the fifth signal switch and the first signal switch synchronously act; the fourth output node is connected between the fourth driving switch and the sixth driving switch and between the third signal switch and the fifth signal switch; the first driving switch, the second driving switch, the third driving switch and the fourth driving switch are connected with one of an excitation voltage source or a grounding terminal, and the seventh driving switch, the eighth driving switch, the fifth driving switch and the sixth driving switch are connected with the other of the excitation voltage source or the grounding terminal; the fourth signal switch, the first signal switch, the second signal switch and the third signal switch are connected with one of a first signal output end or a first reference output end of the first switching circuit, and the sixth signal switch, the seventh signal switch, the eighth signal switch and the fifth signal switch are connected with the other one of the first signal output end or the first reference output end.

As a further improvement of an embodiment of the present invention, the sensor circuit is configured to alternately trigger the first drive switch and the second drive switch, and to delay triggering the first signal switch by a first delay time after triggering the first drive switch, and to delay triggering the second signal switch by a second delay time after triggering the second drive switch.

As a further improvement of an embodiment of the present invention, the sensor circuit is configured to trigger a first driving switch, a second driving switch, a third driving switch, and a fourth driving switch in sequence in each driving period, and delay a first delay time after triggering the first driving switch to trigger the first signal switch, delay a second delay time after triggering the second driving switch to trigger the second signal switch, delay a third delay time after triggering the third driving switch to trigger the third signal switch, and delay a fourth delay time after triggering the fourth driving switch to trigger the fourth signal switch.

As a further improvement of an embodiment of the present invention, the sensor circuit is configured to trigger the chopper in the suppression circuit for a first holding time in a first state and to trigger the chopper for a second holding time in a second state; wherein a trigger rising edge of the chopper is at least aligned with a trigger rising edge of the first signal switch, and a first holding time is greater than or equal to a trigger duration of the first signal switch; a trigger falling edge of the chopper aligned with a trigger rising edge of the second signal switch in the first state and aligned with a trigger rising edge of the third signal switch in the second state; the first retention time is one-half of the second retention time.

As a further development of an embodiment of the invention, the first switching circuit further comprises an output capacitor connected in parallel with the first signal branch.

As a further improvement of an embodiment of the present invention, the sensor circuit further includes a clock circuit, which is connected to the first switching circuit and the suppressing circuit, respectively, and is configured to control at least an operation timing of the signal switch in the first switching circuit and an operation timing of the chopper in the suppressing circuit.

As a further improvement of an embodiment of the present invention, the sensor circuit further includes a third sensing unit and a fourth sensing unit, and the suppressing circuit further includes a third adjusting circuit and a fourth adjusting circuit connected to the output terminals of the circuit, respectively; the third sensing unit is connected to the third adjusting circuit, and the fourth sensing unit is connected to the fourth adjusting circuit.

As a further improvement of an embodiment of the present invention, the sensor circuit further includes a second switching circuit disposed between the third sensing unit and the suppressing circuit.

As a further improvement of an embodiment of the present invention, the first sensing unit and the second sensing unit include hall elements.

As a further improvement of an embodiment of the present invention, the first sensing unit includes a first hall element and a second hall element; the first Hall node of the first Hall element is connected with the sixth Hall node of the second Hall element to form a first output node; the second Hall node of the first Hall element is connected with the seventh Hall node of the second Hall element to form a second output node; the third Hall node of the first Hall element is connected with the eighth Hall node of the second Hall element to form a third output node; the fourth Hall node of the first Hall element is connected with the fifth Hall node of the second Hall element to form a fourth output node; the first sensing unit is connected to the suppression circuit through the first, second, third and/or fourth output nodes.

As a further improvement of an embodiment of the present invention, the first sensing unit includes a first hall element, a second hall element, a third hall element, and a fourth hall element; the first Hall node of the first Hall element, the eighth Hall node of the second Hall element, the eleventh Hall node of the third Hall element and the fourteenth Hall node of the fourth Hall element are connected to form a first output node; the second Hall node of the first Hall element, the fifth Hall node of the second Hall element, the twelfth Hall node of the third Hall element and the fifteenth Hall node of the fourth Hall element are connected to form a second output node; the third Hall node of the first Hall element, the sixth Hall node of the second Hall element, the ninth Hall node of the third Hall element and the sixteenth Hall node of the fourth Hall element are connected to form a third output node; the fourth Hall node of the first Hall element, the seventh Hall node of the second Hall element, the tenth Hall node of the third Hall element and the thirteenth Hall node of the fourth Hall element are connected to form a fourth output node; the first sensing unit is connected to the suppression circuit through the first, second, third and/or fourth output nodes.

As a further improvement of an embodiment of the present invention, the first sensing unit includes a first hall element and a second hall element; the first Hall node of the first Hall element is connected with the fifth Hall node of the second Hall element to form a first output node; the second Hall node of the first Hall element is connected with the eighth Hall node of the second Hall element to form a second output node; the third Hall node of the first Hall element is connected with the seventh Hall node of the second Hall element to form a third output node; the fourth Hall node of the first Hall element is connected with the sixth Hall node of the second Hall element to form a fourth output node; the first sensing unit is connected to the suppression circuit through the first, second, third and/or fourth output nodes.

In order to achieve one of the above objects, an embodiment of the present invention provides an electrical apparatus, which includes the sensor circuit according to any one of the above technical solutions.

Compared with the prior art, the sensor circuit provided by the invention has the advantages that one of the two sensing branches is constructed into the low bandwidth and the high gain by constructing the two sensing branches which are mutually compared, and the other one of the two sensing branches is constructed into the high bandwidth and the low gain, so that the characteristics of high gain and small drift of the former branch in the low bandwidth working range are utilized, the output of the latter branch in the low bandwidth range is equivalently replaced, the integral output of the sensor circuit has the characteristic of small drift even in the high working bandwidth range, and the high precision of measurement and the stronger adaptability of the high bandwidth working scene are both considered.

Drawings

Fig. 1 is a schematic diagram of a sensor circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a first sensing unit in a first embodiment of a sensor circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram illustrating an operation of the first sensing unit in the first embodiment of the sensor circuit according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a first sensing unit in a second embodiment of a sensor circuit according to an embodiment of the invention.

Fig. 5 is a schematic diagram illustrating the operation of the first sensing unit in the second embodiment of the sensor circuit according to an embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a first sensing unit in a third embodiment of a sensor circuit according to an embodiment of the invention.

Fig. 7 is a schematic diagram of a first switching circuit of the sensor circuit according to an embodiment of the present invention.

FIG. 8 is a timing diagram illustrating operation of the first switching circuit and the clock circuit in the first mode of operation of the sensor circuit according to an embodiment of the present invention.

FIG. 9 is a timing diagram illustrating operation of the first switching circuit and the clock circuit in the second mode of operation of the sensor circuit according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of a first example of a suppression circuit in a sensor circuit according to an embodiment of the present invention.

Fig. 11 is a schematic diagram of a configuration of a suppression circuit in a second example of a sensor circuit according to an embodiment of the present invention.

Fig. 12 is a schematic diagram showing a configuration of a suppression circuit in a third example of a sensor circuit according to an embodiment of the present invention.

Fig. 13 is a schematic diagram of a ripple cancellation circuit of a suppression circuit in a third example of a sensor circuit in an embodiment of the present invention.

Fig. 14 is a schematic diagram of a sensor circuit according to another embodiment of the present invention.

Fig. 15 is a schematic diagram of a suppression circuit of a sensor circuit according to another embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.

It should be noted that the term "comprises," "comprising," or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," "eighth," "ninth," "tenth," "eleventh," "twelfth," "thirteenth," "fourteenth," "fifteenth," "sixteenth," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

It should be noted that, in fig. 2 to 6, the first direction W1, the second direction W2, and the third direction W3 are shown to have a correspondence relationship with each other, and those skilled in the art can determine the arrangement orientation of the structures such as the current sensor provided by the present invention, and the relative positional relationship between the internal structures thereof, based on such correspondence relationship. In the present invention, the first direction W1, the second direction W2, and the third direction W3 may refer to directions shown in the drawings or the opposite directions, unless otherwise specified. Preferably, the first direction W1, the second direction W2 and the third direction W3 are perpendicular to each other.

An embodiment of the invention provides an electrical device comprising a sensor circuit. The powered device may be any device or system that controls or outputs data based on the data signals output by the sensor circuit. Specifically, the electric equipment may be a bulk device such as industrial equipment, medical equipment, an automobile or a power supply, or may be a small device such as an integrated circuit chip, a Light-Emitting Diode (LED) driving device, a motor driving device or a communication device. Preferably, the sensor circuit may be used to detect current.

An embodiment of the present invention provides a sensor circuit 100 as shown in fig. 1, which can be applied to any of the above-mentioned electric devices, and can also be applied to any other device that needs to perform data detection. Notably, the constituent modules in the sensor circuit 100 may be configured in the electrical device independently of each other, and communication and linkage between each other may be completed through wiring; the various parts of the sensor circuit 100 may also be integrally formed on a structure such as a circuit board, so as to be integrally disposed in the powered device, so as to ensure structural stability of the constituent parts.

In an embodiment, as shown in fig. 1 in combination with fig. 10 to 12 and fig. 14 and 15, the sensor circuit 100 (or in fig. 14, the sensor circuit 100') includes a first sensing unit 20, a second sensing unit 30, and a suppression circuit 40. Wherein the first sensing unit 20 and the second sensing unit 30 are used for detecting data signals, on the one hand, preferably for detecting current signals on an external conductor; on the other hand, the second sensing unit 30 may be configured to have the same sensitivity level as the first sensing unit 20.

The suppression circuit 40 is configured to receive the output signals of the first sensing unit 20 and the second sensing unit 30, and output a data detection signal supporting full bandwidth and having high accuracy after modulation. The data detection signal is preferably configured as a voltage signal carrying current information of the outer conductor.

The suppression circuit 40 includes a first regulation circuit 41 and a second regulation circuit 42 respectively connected to circuit outputs. The first sensing unit 20 is connected to the first adjusting circuit 41 to form a first sensing branch, and the second sensing unit 30 is connected to the second adjusting circuit 42 to form a second sensing branch; the first sensing branch is configured for low bandwidth high gain and the second sensing branch is configured for high bandwidth low gain.

In the present invention, the expressions "connected", "connected to" and the like may be interpreted as a direct connection including but not limited to connection by Wire Bonding (Bonding Wire), an indirect connection including but not limited to indirect connection by a component such as a resistor, a capacitor or the like, or an indirect connection by a circuit component such as the first switching circuit 50.

Wherein embodiments implementing the "low bandwidth high gain" and the "high bandwidth low gain" may be of the variety described below. As will be appreciated by those skilled in the art, bandwidth characteristics and gain characteristics are generally mutually exclusive: configuring the first conditioning circuit 41 or the first sensing branch to be high gain results in its lower bandwidth, lower voltage drift in the low bandwidth range, and higher voltage drift in the high bandwidth range; configuring the second conditioning circuit 42 or the second sensing branch to be low gain results in a higher bandwidth, higher voltage drift in the low bandwidth range, and lower voltage drift in the high bandwidth range.

Further, the first sensing leg may be configured to output a high gain signal that attenuates low bandwidth drift that the second sensing leg forms on the circuit output 401. In this way, the first sensing branch or the first regulating circuit 41 has the advantage of having a high gain and a lower drift in the low bandwidth range based on the voltage drift on the second sensing branch or the second regulating circuit 42 being distributed in the low bandwidth range, and thus the low bandwidth drift of the second sensing branch or the second regulating circuit 42 at the circuit output 401 can be attenuated.

The suppression of low bandwidth drift is more pronounced when the first sensing unit 20 and the second sensing unit 30 are operating at high bandwidth, but of course still exists when both sensing units are operating at low bandwidth.

In other words, since the gain of the first sensing branch is large, the output of the suppression circuit 40 is mainly derived from the output of the first sensing branch in the low bandwidth of the first sensing branch, at which time voltage drift mainly distributed in the low bandwidth range is naturally shielded. Correspondingly, when the bandwidth of the signal applied to the two sensing units is higher than the low bandwidth range of the first sensing branch, the output of the suppressing circuit 40 mainly comes from the output of the second sensing branch, and the offset voltage in the output of the second sensing branch is equivalently replaced by the output of the first sensing branch because the frequency of the offset voltage falls within the bandwidth of the first sensing branch and the gain on the second sensing branch is smaller than the gain on the first sensing branch.

In this way, the sensor circuit provided by the invention takes the output of the first sensing branch circuit with high gain and low drift as main output in a low bandwidth range, takes the output of the second sensing branch circuit with low gain as main output in a high bandwidth range, and utilizes the output of the first sensing branch circuit in the low bandwidth range to at least weaken the voltage drift in the bandwidth range of the first sensing branch circuit in the output of the second sensing branch circuit, even utilizes the output of the first sensing branch circuit in the low bandwidth range to directly replace the voltage drift in the output of the second sensing branch circuit in the above range, thereby realizing the effect of improving the signal precision on the basis of adapting to high bandwidth.

In an embodiment of the present invention, the first sensing unit 20 and the second sensing unit 30 may be composed of or at least include hall elements. Further, each sensing unit may include one or more hall elements therein, and perform unidirectional superposition output, multidirectional superposition output, or multidirectional differential output. In this way, the error can be reduced on the output side of the sensing unit based on the sensitivity in the multiple directions. Various examples based on this embodiment will be explained below, although the present invention is described below with the first sensing unit 20 as an object, it will be understood that the following structural configuration is equally possible for the second sensing unit 30 or even more other sensing units (such as the third sensing unit 83 and the fourth sensing unit 84 in fig. 14).

As shown in fig. 2 and 3, in combination with fig. 1, 7 and 14, in the first example based on the above-described embodiment, the first sensing unit 20 includes the first hall element 21 and the second hall element 22.

The first hall node h1 of the first hall element 21 is connected to the sixth hall node h6 of the second hall element 22 to form a first output node P1. The second hall node h2 of the first hall element 21 is connected to the seventh hall node h7 of the second hall element 22 to form a second output node P2. The third hall node h3 of the first hall element 21 is connected to the eighth hall node h8 of the second hall element 22 to form a third output node P3. The fourth hall node h4 of the first hall element 21 is connected to the fifth hall node h5 of the second hall element 22 to form a fourth output node P4.

Further, the first sensing unit 20 is connected to the suppression circuit 40 through the first output node P1, the second output node P2, the third output node P3, or the fourth output node P4, or is connected to the suppression circuit 40 through the first output node P1 and the third output node P3, or is connected to the suppression circuit 40 through the second output node P2 and the fourth output node P4, or is connected to the suppression circuit 40 through the four output nodes. In this manner, a multidirectional sensitivity superposition output is optionally constructed.

Preferably, two of the four output nodes may be connected to the power supply level and the ground level, respectively, and the other two are connected to the suppression circuit 40 as outputs. It will be appreciated that the connection selection of the output nodes described above may be achieved by a mechanical switch, a switching tube or a contact construction switchable path.

Taking the example of switching the first output node P1 to the power supply level, switching the third output node P3 to the ground level, and switching the second output node P2 and the fourth output node P4 to the suppression circuit 40. The first hall element 21 generates a first hall current i11 in a direction intermediate to the second direction W2 and the opposite direction of the first direction W1; the second hall element 22 generates the second hall current i12 in a direction intermediate between the second direction W2 and the first direction W1. If a magnetic field generated after the external conductor is energized is applied to the first sensing unit 20 in the opposite direction of the third direction W3, charges are accumulated at the fourth and fifth hall nodes h4 and h5, and the second and seventh hall nodes h2 and h7 are repelled. The potential differences on the first hall element 21 and the second hall element 22 are respectively superimposed on the fourth output node P4 and the second output node P2, forming a multidirectional superimposed voltage signal.

As shown in fig. 4 and 5, in combination with fig. 1, 7 and 14, in the second example based on the above-described embodiment, the first sensing unit 20' includes the first hall element 21, the second hall element 22, the third hall element 23 and the fourth hall element 24.

The first hall node h1 of the first hall element 21, the eighth hall node h8 of the second hall element 22, the eleventh hall node h11 of the third hall element 23, and the fourteenth hall node h14 of the fourth hall element 24 are connected to form a first output node P1.

The second hall node h2 of the first hall element 21, the fifth hall node h5 of the second hall element 22, the twelfth hall node h12 of the third hall element 23, and the fifteenth hall node h15 of the fourth hall element 24 are connected to form a second output node P2.

The third hall node h3 of the first hall element 21, the sixth hall node h6 of the second hall element 22, the ninth hall node h9 of the third hall element 23, and the sixteenth hall node h16 of the fourth hall element 24 are connected to form a third output node P3.

The fourth hall node h4 of the first hall element 21, the seventh hall node h7 of the second hall element 22, the tenth hall node h10 of the third hall element 23, and the thirteenth hall node h13 of the fourth hall element 24 are connected to form a fourth output node P4.

Further, the first sensing unit 20' is connected to the inhibit circuit 40 through the first output node P1, the second output node P2, the third output node P3 or the fourth output node P4, or is connected to the inhibit circuit 40 through the first output node P1 and the third output node P3, or is connected to the inhibit circuit 40 through the second output node P2 and the fourth output node P4, or is connected to the inhibit circuit 40 through the four output nodes. In this manner, a multidirectional sensitivity superposition output is optionally constructed.

Taking the example of switching the first output node P1 to the power supply level, switching the third output node P3 to the ground level, and switching the second output node P2 and the fourth output node P4 to the suppression circuit 40. The first hall element 21 generates a first hall current i11 in a direction intermediate to the second direction W2 and the opposite direction of the first direction W1; the second hall element 22 generates a second hall current i12 in a direction intermediate between the opposite direction of the second direction W2 and the opposite direction of the first direction W1; the third hall element 23 generates a third hall current i13 in a direction opposite to the second direction W2 and in a direction intermediate to the first direction W1; the fourth hall element 24 generates a fourth hall current i14 in a direction intermediate between the second direction W2 and the first direction W1.

If a magnetic field generated after the external conductor is energized is applied to the first sensing unit 20' in the opposite direction of the third direction W3, charges are accumulated at the fourth, seventh, tenth and thirteenth hall nodes h4, h7, h10 and h13, and the second, fifth, twelfth and fifteenth hall nodes h2, h5, h12 and h15 are repelled. The potential differences of the four hall elements are respectively overlapped on the fourth output node P4 and the second output node P2 to form a voltage signal after multidirectional overlapping.

As shown in fig. 6, in conjunction with fig. 1, 7 and 14, in the third example based on the above-described embodiment, the first sensing unit 20″ includes the first hall element 21 and the second hall element 22.

The first hall node h1 of the first hall element 21 is connected to the fifth hall node h5 of the second hall element 22 to form a first output node P1. The second hall node h2 of the first hall element 21 is connected to the eighth hall node h8 of the second hall element 22 to form a second output node P2. The third hall node h3 of the first hall element 21 is connected to the seventh hall node h7 of the second hall element 22 to form a third output node P3. The fourth hall node h4 of the first hall element 21 is connected to the sixth hall node h6 of the second hall element 22 to form a fourth output node P4.

Further, the first sensing unit 20″ is connected to the inhibit circuit 40 through the first output node P1, the second output node P2, the third output node P3, or the fourth output node P4, or is connected to the inhibit circuit 40 through the first output node P1 and the third output node P3, or is connected to the inhibit circuit 40 through the second output node P2 and the fourth output node P4, or is connected to the inhibit circuit 40 through the four output nodes. As such, a multi-directional sensitivity differential output is optionally constructed.

Taking the example of switching the first output node P1 to the power supply level, switching the third output node P3 to the ground level, and switching the second output node P2 and the fourth output node P4 to the suppression circuit 40. The first hall element 21 generates a first hall current i11 in a direction intermediate to the second direction W2 and the opposite direction of the first direction W1; the second hall current i12 is generated in the second hall element 22 in a direction intermediate between the opposite direction of the second direction W2 and the opposite direction of the first direction W1. If a magnetic field generated after the external conductor is energized is applied to the first sensing unit 20″ in the opposite direction of the third direction W3, charges are accumulated at the fourth and eighth hall nodes h4 and h8, and the second and sixth hall nodes h2 and h6 are repelled. The potential differences on the first hall element 21 and the second hall element 22 cancel each other out on the fourth output node P4 and the second output node P2, respectively, forming a multi-directional differential voltage signal.

As further shown in fig. 1 and 14, the sensor circuit 100 (or in fig. 14, the sensor circuit 100') further includes a first switching circuit 50 disposed between the first sensing unit 20 and the suppressing circuit 40, where the first switching circuit 50 is configured to switch the current flowing in the first sensing unit 20, and correspondingly adjust the connection relationship between the suppressing circuit 40 and the node on the first sensing unit 20 for outputting the signal.

For example, at one time, the first output node P1 is controlled to be connected to the power supply level, the third output node P3 is controlled to be connected to the ground level, and the second output node P2 and the fourth output node P4 are controlled to be connected to the suppression circuit 40; at another time, the second output node P2 is controlled to be connected to the power supply level, the fourth output node P4 is controlled to be connected to the ground level, and the first output node P1 and the third output node P3 are controlled to be connected to the suppression circuit 40.

In addition, the present invention does not exclude the provision of a switching circuit between the second sensing unit and the suppression circuit 40, nor the configuration of the switching circuit to have the same or opposite operation timing as the first switching circuit 50.

In one embodiment, the above-mentioned relation adjustment is reflected on the structural level, and may be that the first output node P1, the second output node P2, the third output node P3, and the fourth output node P4 are respectively connected to the first switching circuit 50, and the first switching circuit 50 outputs the node for outputting the data signal to the suppression circuit 40 through the first signal output terminal Vopd1 of the first switching circuit 50 and the first reference output terminal Vond1 of the first switching circuit 50. The reference signs Vopd1 and Vond1 corresponding to the "first signal output terminal" and the "first reference output terminal" may also be interpreted as that the two output terminals realize transmission in the form of a voltage signal.

Preferably, as shown in fig. 7, in combination with fig. 1 and 14. The first switching circuit 50 may include a driving switch group 51 and a signal switch group 52. It will be appreciated that a switching circuit (such as the second switching circuit 82 in fig. 14) provided later may be configured in the same or similar structure as the first switching circuit 50.

Wherein the driving switch group 51 is at least used for driving the first sensing unit 20. May be interpreted as being used to drive other sensing units than the first sensing unit 20, and may be interpreted as being used to perform other functions than driving the first sensing unit 20.

The signal switch group 52 is at least used for outputting the signal voltage generated after the first sensing unit 20 is driven to the suppression circuit 40. It can be explained that the voltage signal generated by the first sensing unit 20 after driving corresponding to the external conductor and carrying the current signal is transmitted to the suppression circuit 40.

Preferably, the first switching circuit 50 may be constructed as a switching array from mechanical switches, contacts or transistors as switching devices. A preferred embodiment is provided below based on the first sensing unit 20 comprising a first output node P1, a second output node P2, a third output node P3 and a fourth output node P4.

The driving switch group 51 includes a first driving leg, a second driving leg, a third driving leg, and a fourth driving leg connected in parallel with each other. Preferably, four driving branches may be connected in parallel between the excitation voltage source EXC and the ground GND, thereby providing a power supply level and a ground level to the first sensing unit 20.

The first driving branch is connected with a first driving switch D1 in series, the second driving branch is connected with a second driving switch D2 in series, the third driving branch is connected with a third driving switch D3 in series, and the fourth driving branch is connected with a fourth driving switch D4 in series.

The signal switch group comprises a first signal branch, a second signal branch, a third signal branch and a fourth signal branch which are mutually connected in parallel. Preferably, four signal branches may be connected in parallel between the first signal output terminal Vopd1 and the first reference output terminal Vond1, and the signal voltage from the first sensing unit 20 is adjusted and output to the back-end device.

The first signal branch is connected with a fourth signal switch S4 in series, the second signal branch is connected with a first signal switch S1 in series, the third signal branch is connected with a second signal switch S2 in series, and the fourth signal branch is connected with a third signal switch S3 in series.

Further, a first output node P1 is connected to the first driving branch and the first signal branch, a second output node P2 is connected to the second driving branch and the second signal branch, a third output node P3 is connected to the third driving branch and the third signal branch, and a fourth output node P4 is connected to the fourth driving branch and the fourth signal branch.

Preferably, the operation timings of the first driving switch D1 and the first signal switch S1 are substantially the same, the operation timings of the second driving switch D2 and the second signal switch S2 are substantially the same, the operation timings of the third driving switch D3 and the third signal switch S3 are substantially the same, and the operation timings of the fourth driving switch D4 and the fourth signal switch S4 are substantially the same.

When the first driving switch D1 is closed and the first signal switch S1 is closed, the first output node P1 is connected to the excitation voltage source EXC, and the second output node P2 is connected to the first signal output terminal Vopd1, so that one phase in the hall current-direction multiphase regulation is formed. Similarly, the second driving switch D2 is closed and the second signal switch S2 is closed to form a phase, the third driving switch D3 is closed and the third signal switch D3 is closed to form a phase, the fourth driving switch D4 is closed and the fourth signal switch D4 is closed to form a phase, and four-phase adjustment can be realized by applying the circuit provided by the invention.

Correspondingly, in one embodiment, the first driving branch is further connected in series with a seventh driving switch D7. The seventh driving switch D7 and the third driving switch D3 operate synchronously. The first signal branch is also connected in series with a sixth signal switch S6. The sixth signal switch S6 and the second signal switch S2 operate synchronously. Based on this, the first output node P1 is connected between the first driving switch D1 and the seventh driving switch D7, and the first output node P1 is connected between the fourth signal switch S4 and the sixth signal switch S6.

In one embodiment, the second drive branch is further connected in series with an eighth drive switch D8. The eighth driving switch D8 and the fourth driving switch D4 operate synchronously. The second signal branch is also connected in series with a seventh signal switch S7. The seventh signal switch S7 and the third signal switch S3 operate synchronously. Based on this, the second output node P2 is connected between the second driving switch D2 and the eighth driving switch D8, and the second output node P2 is connected between the first signal switch S1 and the seventh signal switch S7.

In one embodiment, the third driving branch is further connected in series with a fifth driving switch D5. The fifth driving switch D5 and the first driving switch D1 operate synchronously. The third signal branch is also connected in series with an eighth signal switch S8. The eighth signal switch S8 and the fourth signal switch S4 operate synchronously. Based on this, the third output node P3 is connected between the third driving switch D3 and the fifth driving switch D5, and the third output node P3 is connected between the second signal switch S2 and the eighth signal switch S8.

In one embodiment, the fourth drive branch is further connected in series with a sixth drive switch D6. The sixth driving switch D6 and the second driving switch D2 operate synchronously. The fourth signal branch is also connected in series with a fifth signal switch S5. The fifth signal switch S5 operates in synchronization with the first signal switch S1. Based on this, the fourth output node P4 is connected between the fourth driving switch D4 and the sixth driving switch D6, and the fourth output node P4 is connected between the third signal switch S3 and the fifth signal switch S5.

Further, the first driving switch D1, the second driving switch D2, the third driving switch D3 and the fourth driving switch D4 are connected to one of the excitation voltage source EXC or the ground GND. In one embodiment, the excitation voltage source EXC may be connected. The seventh driving switch D7, the eighth driving switch D8, the fifth driving switch D5, and the sixth driving switch D6 are connected to the other one of the excitation voltage source EXC or the ground GND. In one embodiment, it may be connected to ground GND.

Correspondingly, the fourth signal switch S4, the first signal switch S1, the second signal switch S2 and the third signal switch S3 are connected to one of the first signal output terminal Vopd1 and the first reference output terminal Vond1. In one embodiment, the first signal output terminal Vopd1 is connected. The sixth signal switch S6, the seventh signal switch S7, the eighth signal switch S8, and the fifth signal switch S5 are connected to the other one of the first signal output terminal Vopd1 and the first reference output terminal Vond1. In one embodiment, the first reference output terminal Vond1 may be connected.

For example, when the first driving switch D1 and the first signal switch S1 are closed, the fifth driving switch D5 and the fifth signal switch S5 are correspondingly closed, the first output node P1 is connected to the excitation voltage source EXC, the third output node P3 is connected to the ground GND, the second output node P2 is connected to the first signal output terminal Vopd1, and the fourth output node P4 is connected to the first reference output terminal Vond1. Thus, one phase of the hall current direction multiphase regulation is constituted. The other phase formed by the second driving switch D2 and the second signal switch S2, or other three phases, can be realized with reference to the description of the operation principle above.

Preferably, the first switching circuit 50 may further include an output capacitor Cs connected in parallel with the first signal branch, the second signal branch, the third signal branch, or the fourth signal branch.

In one embodiment, the first switching circuit 50 may implement a two-phase adjustment, i.e., a first operation mode, based on the action timing shown in fig. 8. As shown in connection with fig. 1 and 7, or fig. 14 and 7, the sensor circuit 100 or the sensor circuit 100' may be configured to alternately trigger the first driving switch D1 and the second driving switch D2. In one aspect, the first driving switch D1 may be controlled to be triggered at a high level (logic 1) and the second driving switch D2 may be controlled to be turned off at a low level (logic 0) during a first period; the second time period after the first time period controls the first driving switch D1 to be turned off at a low level, and controls the second driving switch D2 to be triggered at a high level. On the other hand, during the two-phase adjustment, the third driving switch D3, the third signal switch S3, the fourth driving switch D4, and the fourth signal switch S4 may be always in a low-level off (logic 0) state.

Further, the sensor circuit 100 or the sensor circuit 100' may be further configured to trigger the first signal switch S1 by a first delay time D1 after the triggering of the first driving switch D1 and trigger the second signal switch S2 by a second delay time D2 after the triggering of the second driving switch D2. In this way, it is possible to avoid an error in which "dead time" generated by the fact that the drive switch has just been closed and the output of the sensing unit has not been established is reflected to the subsequent stage of the circuit.

Preferably, the rising edge of the first signal switch S1 and other signal switches is delayed compared to the rising edge of the first driving switch D1 and other driving switches, and the falling edge of the first driving switch D1 and other driving switches may be delayed compared to the falling edge of the first signal switch S1 and other signal switches, so that the on time of the signal switches is shorter than that of the driving switches.

Preferably, the first delay time d1 is equal to the second delay time d2.

In another embodiment, the first switching circuit 50 may implement four-phase adjustment, i.e., the second operation mode, based on the operation timing shown in fig. 9. As shown in connection with fig. 1 and 7, or fig. 14 and 7, the sensor circuit 100 or the sensor circuit 100' may be configured to sequentially trigger the first driving switch D1, the second driving switch D2, the third driving switch D3, and the fourth driving switch D4 at each driving period. On the other hand, the high level triggering (logic 1) of the first driving switch D1 and the low level switching off (logic 0) of the other driving switches such as the second driving switch D2, the third driving switch D3 and the fourth driving switch D4 can be controlled in a first time period; the second time period after the first time period controls the second driving switch D2 to trigger at a high level, controls the first driving switch D1 and other switches to turn off at a low level, and so on.

Further, the sensor circuit 100 may be further configured to delay triggering of the first signal switch S1 by a first delay time D1 after triggering of the first drive switch D1, delay triggering of the second signal switch S2 by a second delay time D2 after triggering of the second drive switch D2, delay triggering of the third signal switch S3 by a third delay time D3 after triggering of the third drive switch D3, and delay triggering of the fourth signal switch S4 by a fourth delay time D4 after triggering of the fourth drive switch D4.

Preferably, the first delay time d1, the second delay time d2, the third delay time d3, and the fourth delay time d4 are equal.

Either the two-phase adjustment shown in fig. 8 or the four-phase adjustment shown in fig. 9 can be considered to be performed under the control of the first clock signal C1 and the first inverted clock signal C1N. In the two-phase adjustment, the rising edge of the first clock signal C1 may be aligned with the rising edge of the first signal switch S1, and the rising edge of the first inverted clock signal C1N may be aligned with the rising edge of the second signal switch S2. In the four-phase adjustment, the first clock signal C1 is aligned with the rising edge of the first signal switch S1 or the third signal switch S3, and the first inverted clock signal C1N is aligned with the rising edge of the second signal switch S2 or the fourth signal switch S4.

As shown in fig. 8 and 9, in conjunction with fig. 1, 7 and 14, the suppression circuit 40 may further include a chopper, and the first clock signal C1 and the first inverted clock signal C1N may be further used to at least control the action of the chopper, so as to implement corresponding processing when a signal is output to the suppression circuit 40.

In addition, the sensor circuit 100 or the sensor circuit 100' may further include a second clock signal C2 and a second inverted clock signal C2N, which are applied in a four-phase adjustment scenario to eliminate errors between the first phase and the second phase and between the third phase and the fourth phase. Wherein the first phase points to the first driving switch D1, and the first signal switch S1 is conducted; the second phase points to the second driving switch D2 and the second signal switch S2 to be conducted; the third phase points to the third driving switch D3 and the third signal switch S3 is conducted; the fourth phase is directed to the fourth driving switch D4, and the fourth signal switch S4 is turned on.

Specifically, the sensor circuit 100 (or the sensor circuit 100' in fig. 14) is configured to trigger the chopper in the suppression circuit 40 for a first holding time Δt1 in a first state, and to trigger the chopper for a second holding time Δt2 in a second state.

Wherein the trigger rising edge of the chopper is at least aligned with the trigger rising edge of the first signal switch S1, and the first holding time Δt1 is greater than or equal to the trigger duration of the first signal switch S1. In this way, it can be ensured that the chopper is able to receive the signal from the front end completely.

Wherein the trigger falling edge of the chopper is aligned with the trigger rising edge of the second signal switch S2 in the first state and with the trigger rising edge of the third signal switch S3 in the second state. Thus, the operating frequency of the chopper can be made to correspond to the single-phase trigger time period or the two-phase trigger time period.

Wherein the first holding time Δt1 is one half of the second holding time Δt2. In this way, the error between the front two phases and the rear two phases can be eliminated based on the manner in which the equivalent two-phase adjustment is made in the four-phase adjustment.

It will be appreciated that although the configuration of the sensor circuit 100 is described above as being based on the second clock signal C2, a person skilled in the art will be able to derive the purpose of the second inverted clock signal C2N and a description based thereon. In addition, since the four driving switches are sequentially triggered and the four signal switches are sequentially triggered during four-phase adjustment, the trigger rising edge of the chopper in the first state can be aligned with the trigger rising edge of the third signal switch, and the trigger falling edge of the chopper in the first state can be aligned with the trigger falling edge of the fourth signal switch.

Preferably, continuing with fig. 1 and 14, sensor circuit 100 (or sensor circuit 100' in fig. 14) also includes clock circuit 60. The clock circuit 60 is connected to the first switching circuit 50 and the suppressing circuit 40, respectively, and is used for controlling at least the operation timing of the signal switch in the first switching circuit 50 and the operation timing of the chopper in the suppressing circuit 40. Based on this, the sensor circuit 100 can realize the above control by the clock circuit 60. Of course, the invention does not exclude other ways such as controlling the action time sequence of the components in the circuit by an upper computer.

In summary, table 1 below shows the flow direction of the excitation current (or driving current) on the sensing unit, the direction of the output voltage, and the positive and negative of the voltage signal Vh (specifically, hall voltage signal) carrying the current information generated by the sensing unit and the positive and negative of the offset voltage Vos based on two schemes of four-phase adjustment and two-phase adjustment.

TABLE 1

Based on this, the first switching circuit 50 may be used to modulate the offset voltage Vos to a high frequency.

As shown in fig. 10, 11, 12 and 15, the present invention provides various arrangements with respect to the suppression circuit 40, particularly the first and

second regulating circuits

41 and 42 therein, as shown in connection with fig. 1 and 14.

Preferably, the first adjusting circuit 41 comprises a first chopper ch1, a first transconductance amplifier Gm1, a second chopper ch2 and a drift filter circuit 45 connected in sequence, the output 450 of the drift filter circuit being connected to the circuit output 401.

The first chopper ch1 is configured to demodulate the first offset voltage Vos1 modulated to a high frequency from the input signal from the first sensing unit 20 (in particular, from the signal output from the first switching circuit 50) back to a dc state, and to modulate the first voltage signal Vh1 of the dc from the first sensing unit 20 to a high frequency. The second chopper ch2 is configured to modulate the first offset voltage Vos1 to a high frequency again, and simultaneously demodulate and output the voltage signal Vh back to a dc state. The drift filter circuit 45 is configured to amplify and voltage drift filter the signal from the second chopper ch2 (i.e., perform filtering on at least the offset voltage Vos such as the first offset voltage Vos 1).

In this way, the first adjusting circuit can superimpose the input of the high-frequency first offset voltage Vos1 Fang Bowen wave on the basis of the first voltage signal Vh1, modulate the offset voltage of the first transconductance amplifier Gm1 into a high frequency through chopping and amplifying, superimpose the high-frequency first offset voltage Vos1 input by the first sensing unit 20, and output the high-frequency first offset voltage Vos1 to the drift filter circuit 45. The offset voltage after superposition is converted into triangular wave by the drift filter circuit 45 from square wave ripple, so that ripple suppression is realized.

Preferably, the second adjusting circuit 42 comprises a second transconductance amplifier Gm2, the output of the second transconductance amplifier Gm2 being connected to the output 450 of the drift filter circuit. In this way, in the embodiment in which the first switching circuit 50 is disposed between the first adjusting circuit 41 and the first sensing unit 20 and the switching circuit is not disposed between the second adjusting circuit 42 and the second sensing unit 30, the second adjusting circuit 42 receives the second voltage signal Vh2 and the second offset voltage Vos2 from the second sensing unit 30, which are both in the direct current state.

When the signal bandwidth falls within the low bandwidth range of the first adjusting circuit 41, the output of the circuit output 401 mainly comes from the output of the first adjusting circuit 41 based on the high gain state formed by the first adjusting circuit 41 under the action of the drift filter circuit 45. When the signal bandwidth exceeds the low bandwidth range of the first adjusting circuit 41, the output of the circuit output terminal 401 mainly comes from the output of the second adjusting circuit 42, and because the second offset voltage Vos2 on the second adjusting circuit 42 is in a dc state, the frequency will necessarily fall within the low bandwidth range of the first adjusting circuit 41, and therefore the second offset voltage Vos2 will be replaced by the signal on the first adjusting circuit 41. The first regulator circuit 41 is provided with a drift filter circuit, and the voltage drift of the first offset voltage Vos1 is suppressed, which is equivalent to suppressing low-frequency noise at the time of high-bandwidth output. Thus, the advantages of high bandwidth and low offset voltage are achieved.

Preferably, the drift filter circuit 45 includes a third transconductance amplifier Gm3, a first filter capacitor Cf1, and a second filter capacitor Cf2.

One end of the first filter capacitor Cf1 is connected to the non-inverting input end of the third transconductance amplifier Gm3, and the other end of the first filter capacitor Cf1 is connected between the non-inverting output end of the third transconductance amplifier Gm3 and the circuit output end 401.

One end of the second filter capacitor Cf2 is connected to the inverting input end of the third transconductance amplifier Gm3, and the other end of the second filter capacitor Cf2 is connected between the inverting output end of the third transconductance amplifier Gm3 and the circuit output end 401.

Preferably, the first adjusting circuit 41 further comprises a noise filtering circuit 46 for filtering out thermal noise. The noise filter circuit 46 is disposed between the drift filter circuit 45 and the circuit output terminal 401, so that the signal subjected to the overvoltage drift filtering is subjected to thermal noise filtering, and the accuracy of the output signal is further improved.

The noise filter circuit 46 includes a first integration capacitor Ci1 and a second integration capacitor Ci2 for constructing an integration circuit to realize a thermal noise filtering effect. Further, the sum of the capacitance values of the first filter capacitor Cf1 and the second filter capacitor Cf2 is larger than the sum of the capacitance values of the first integration capacitor Ci1 and the second integration capacitor Ci 2. In this way, the gain of the second adjusting circuit 42 is lower than the gain of the first adjusting circuit 41, and the output of the second adjusting circuit 42 is filtered by the noise filter circuit 46, and then the signal output at the circuit output terminal 401 is formed.

In one embodiment, noise filtering circuit 46 includes a fourth transconductance amplifier Gm4. One end of the first integrating capacitor Ci1 is connected with the non-inverting input end of the fourth transconductance amplifier Gm4, and the other end of the first integrating capacitor Ci1 is connected with the inverting output end of the fourth transconductance amplifier Gm4. One end of the second integrating capacitor Ci2 is connected with the inverting input end of the fourth transconductance amplifier Gm4, and the other end of the second integrating capacitor Ci2 is connected with the non-inverting output end of the fourth transconductance amplifier Gm4. Thus, an integrating circuit centering on the transconductance amplifier is constructed.

Based on this, the other end of the first filter capacitor Cf1, which is not connected to the non-inverting input terminal of the third transconductance amplifier Gm3, may be connected to the non-inverting output terminal of the fourth transconductance amplifier Gm4. The other end of the second filter capacitor Cf2, which is not connected to the inverting input terminal of the third transconductance amplifier Gm3, may be connected to the inverting output terminal of the fourth transconductance amplifier Gm4.

The first regulating circuit 41 as a whole may be regarded as a main circuit provided in the suppressing circuit 40, which may specifically comprise a first inverting branch 411 and a first non-inverting branch 412 to form an output in differential form.

In a preferred embodiment, the inverting output of the first transconductance amplifier Gm1 is connected to the non-inverting input of the third transconductance amplifier Gm3 by a second chopper ch 2. The inverting output terminal of the third transconductance amplifier Gm3 is connected to the non-inverting input terminal of the fourth transconductance amplifier Gm4. Thus, the first inverting branch 411 of the first adjusting circuit 41 is formed.

On the other hand, the non-inverting output terminal of the first transconductance amplifier Gm1 is connected to the inverting input terminal of the third transconductance amplifier Gm3 through the second chopper ch 2. The non-inverting output terminal of the third transconductance amplifier Gm3 is connected to the inverting input terminal of the fourth transconductance amplifier Gm 4. Thus, the first normal phase leg 412 of the first regulating circuit 41 is formed.

Based on the internal structure of the first adjusting circuit 41 described above, the suppressing circuit 40 may specifically have a configuration such that the first adjusting circuit 41 establishes a connection relationship with other portions in the sensor circuit. The output of the first normal phase leg 412 forms the normal phase output Vop of the circuit output 401; the output of the first inverting branch 411 forms the circuit inverting output Von of the circuit output 401. The input of the first non-inverting branch 412 forms a first non-inverting input Vips1 of the circuit input 402 of the suppression circuit 40 for establishing a connection with the first sensing unit 20, in particular with the first sensing unit 20 via the first signal output Vopd 1. The input of the first inverting branch 411 forms a first inverting input Vins1 of the circuit input 402 for establishing a connection with the first sensing unit 20, in particular with the first sensing unit 20 via the first reference output Vond 1.

Preferably, the suppression circuit 40 further comprises a first feedback circuit 47 corresponding to the first regulation circuit 41 for producing an output opposite to the output of the first regulation circuit 41 for achieving closed loop regulation.

The first feedback circuit 47 is disposed between the circuit output terminal 401 and the output terminal of the second chopper ch2, and the first feedback circuit 47 includes a fifth chopper ch5, a seventh transconductance amplifier Gm7, and a sixth chopper ch6, which are sequentially connected.

Preferably, the seventh transconductance amplifier Gm7 is connected to the first inverting branch 411 by its non-inverting input and inverting output, and the seventh transconductance amplifier Gm7 is connected to the first non-inverting branch 412 by its inverting input and non-inverting output. That is, the first feedback circuit 47 forms an output opposite to the first transconductance amplifier Gm1 for regulation by receiving the first forward and reverse feed voltage Vfp on the first non-inverting branch 412 at its inverting input and the first reverse feedback voltage Vfn on the first inverting branch 411 at its non-inverting input.

In one embodiment, the suppression circuit 40 may further include a gain adjustment circuit 48 disposed between the first feedback circuit 47 and the circuit output 401. Wherein the gain adjustment circuit 48 is used to adjust the gain of the suppression circuit 40.

The gain adjustment circuit 48 may preferably be implemented using a simple resistor divider, or may have other special configurations such as a variable resistor. In one embodiment, the gain adjusting circuit 48 includes a first configuration resistor R1 connected in series with the first inverting branch 411 in the first adjusting circuit 41, a second configuration resistor R2 connected in series with the first non-inverting branch 412 in the first adjusting circuit 41, and a third configuration resistor R3 connected in parallel between the first inverting branch 411 and the first non-inverting branch 412.

Similarly, the suppression circuit 40 may also include a second feedback circuit 49 corresponding to the second regulation circuit 42, and may also be used to output an electrical signal opposite the output of the second regulation circuit 42 to effect closed loop regulation.

The second feedback circuit 49 is disposed between the circuit output terminal 401 and the output terminal of the second transconductance amplifier Gm2, and the second feedback circuit 49 includes an eighth transconductance amplifier Gm8.

Preferably, the inverting output of the second transconductance amplifier Gm2 is connected to the first non-inverting branch 412 to form the second inverting branch 421 of the second regulating circuit 42; the non-inverting output of the second transconductance amplifier Gm2 is connected to the first inverting branch 411 to form a second non-inverting branch 422 of the second regulating circuit 42.

Based on this, the inverting output of the eighth transconductance amplifier Gm8 may be connected to the second inverting branch 421, and the non-inverting output of the eighth transconductance amplifier Gm8 may be connected to the second non-inverting branch 422. The eighth transconductance amplifier Gm8 may obtain the first inverted feedback voltage Vfn by connecting its non-inverting input terminal to the first inverting branch 411, and obtain the first positive and negative feedback voltage Vfp by connecting its inverting input terminal to the first non-inverting branch 412. In this way, an opposite output is formed with respect to the second regulating circuit 42 to effect regulation.

The above structure can also be expressed as having the inverting output of the second transconductance amplifier Gm2 and/or the inverting output of the eighth transconductance amplifier Gm8 connected to the first non-inverting branch 412, in particular to the non-inverting output of the third transconductance amplifier Gm 3; the non-inverting output of the second transconductance amplifier Gm2 and/or the non-inverting output of the eighth transconductance amplifier Gm8 is connected to the first inverting branch 411, in particular to the inverting output of the third transconductance amplifier Gm 3.

In one embodiment, the suppression circuit 40 may also include a gain adjustment circuit 48 disposed between the second feedback circuit 49 and the circuit output 401. Wherein the gain adjustment circuit 48 is used to adjust the gain of the suppression circuit 40. Preferably, the first feedback circuit 47 and the second feedback circuit 49 may share a gain adjustment circuit 48.

In particular, in the second embodiment provided in fig. 11, a first trap N1 is provided between the first transconductance amplifier Gm1 and the third transconductance amplifier Gm 3. In other words, a first trap N1 is provided between the first transconductance amplifier Gm1 or the second chopper ch2 and the drift filter circuit 45. In this way, by sampling and averaging the first trap N1 based on different timings, the ripple of the offset voltage in the signal from the first transconductance amplifier Gm1 in the first adjusting circuit 41 and the signal from the seventh transconductance amplifier Gm7 in the first feedback circuit 47 can be further eliminated.

In particular, in the third embodiment provided in fig. 12 and 13, the suppression circuit 40 further includes a ripple cancellation circuit 70. Wherein the ripple cancellation circuit 70 is configured to further perform ripple suppression on the offset voltage. Preferably, the offset voltage in the first adjusting circuit 41 can be compensated and offset by separating the offset voltage from the voltage signal carrying the current information and generating negative feedback for the offset voltage.

Preferably, the inverting voltage input Vinr and the non-inverting current output Iopr of the ripple cancellation circuit 70 are connected and connected to the inverting output of the first transconductance amplifier Gm 1. The non-inverting voltage input Vipr and the inverting current output Ionr of the ripple cancellation circuit 70 are connected and connected to the non-inverting output of the first transconductance amplifier Gm 1.

In one embodiment, the ripple cancellation circuit 70 may include an integral chopper circuit 71 therein. The integrating chopper 71 is configured to demodulate the output of the first transconductance amplifier Gm1, in particular, the first offset voltage Vos1 output by the first transconductance amplifier Gm1 through the second chopper ch2 from the ripple form back to the dc state, and modulate the first voltage signal Vh1 output by the integrating chopper into the high frequency state, and is configured to amplify the first offset voltage Vos1 of the dc, attenuate or even eliminate the first voltage signal Vh1 of the high frequency, and is configured to modulate the first offset voltage Vos1 of the dc into the high frequency signal, and suppress the first offset voltage Vos1 of the high frequency on the first adjusting circuit 41 through the negative feedback effect.

In one embodiment, the integrating chopper circuit 71 may include a seventh chopper ch7, a ninth transconductance amplifier Gm9, a tenth transconductance amplifier Gm10, an eighth chopper ch8, a third integrating capacitor Ci3, and a fourth integrating capacitor Ci4. The third integrating capacitor Ci3 is disposed between the inverting input terminal and the non-inverting output terminal of the ninth transconductance amplifier Gm9, and the fourth integrating capacitor Ci4 is disposed between the non-inverting input terminal and the inverting output terminal of the ninth transconductance amplifier Gm 9. In this way, the mutual conversion between the direct current state and the high-frequency signal is realized through the two choppers, and the filtering of the high-frequency first voltage signal Vh1 and the inversion compensation of the first offset voltage Vos1 are completed through the ninth transconductance amplifier Gm9, the two integrating capacitors and the tenth transconductance amplifier Gm 10.

Preferably, the integrating chopper circuit 71 may include a number of specific embodiments. For example, the integrating chopper circuit 71 may include at least one of a configuration resistor and an eleventh transconductance amplifier Gm 11.

In an embodiment including configuration resistors, the integrating chopper circuit 71 may be provided with configuration resistors including a fourth configuration resistor R4 and a fifth configuration resistor R5. The fourth configuration resistor R4 is connected to the inverting input terminal of the ninth transconductance amplifier Gm9, and the fifth configuration resistor R5 is connected to the non-inverting input terminal of the ninth transconductance amplifier Gm 9.

In the embodiment comprising the eleventh transconductance amplifier Gm11, the non-inverting output of the eleventh transconductance amplifier Gm11 is connected to the inverting input of the ninth transconductance amplifier Gm9, and the inverting output of the eleventh transconductance amplifier Gm11 is connected to the non-inverting input of the ninth transconductance amplifier Gm 9.

Specifically, it may be configured to:

(1) In the first integrating chopper circuit 71', an eleventh transconductance amplifier Gm11 is provided between the seventh chopper ch7 and the ninth transconductance amplifier Gm9, and the eleventh transconductance amplifier Gm11 is directly connected to the ninth transconductance amplifier Gm 9.

(2) In the second integrating chopper circuit 71″, the seventh chopper ch7 is provided between the eleventh transconductance amplifier Gm11 and the ninth transconductance amplifier Gm9, and the eleventh transconductance amplifier Gm11 and the ninth transconductance amplifier Gm9 are indirectly connected.

In other embodiments, the ripple cancellation circuit 70 may further include at least one of a pre-high pass filter circuit 72, a pre-amplifier circuit 73, and a second trap N2.

Preferably, the front-end high-pass filter circuit 72 includes a third filter capacitor Cf3, a fourth filter capacitor Cf4, a first filter resistor Rf1, and a second filter resistor Rf2. One end of the first filter resistor Rf1 is grounded, and the other end of the first filter resistor Rf1 is connected with the third filter capacitor Cf3; one end of the second filter resistor Rf2 is grounded, and the other end is connected with the fourth filter capacitor Cf4.

Preferably, the pre-amplifier circuit 73 comprises a twelfth transconductance amplifier Gm12, the non-inverting output of the twelfth transconductance amplifier Gm12 being connected to the inverting input of the ninth transconductance amplifier Gm9, in particular to the inverting input of the ninth transconductance amplifier Gm9 through a seventh chopper ch 7; the inverting output terminal of the twelfth transconductance amplifier Gm12 is connected to the non-inverting input terminal of the ninth transconductance amplifier Gm9, and in particular, is connected to the non-inverting input terminal of the ninth transconductance amplifier Gm9 through the seventh chopper ch 7.

In another embodiment as shown in fig. 14 and 15, the sensor circuit 100' further includes a third sensing unit 83 and a fourth sensing unit 84. Preferably, the suppression circuit 40 further comprises a third regulation circuit 43 and a fourth regulation circuit 44, respectively, connected to the circuit output 401. Wherein the third sensing unit 83 is connected to the third adjusting circuit 43 and the fourth sensing unit 84 is connected to the fourth adjusting circuit 44. Thus, two sets of drift noise suppression systems with at least internal mutual restriction are constructed, and noise and drift are kept to be minimized on the premise of adapting to various bandwidth scenes.

Preferably, the sensor circuit 100' further comprises a second switching circuit 82 arranged between the third sensing unit 83 and the suppression circuit 40. The structural configuration and functional role of the second switching circuit 82 can be referred to as the description of the first switching circuit 50 in the present invention, and will not be repeated here.

Specifically, the third sensing unit 83 forms a fifth output node P5, a sixth output node P6, a seventh output node P7, and an eighth output node P8, and is connected to the second switching circuit 82 through the above-described four output nodes, and the second switching circuit 82 is connected to the third non-inverting input terminal Vips3 and the third inverting input terminal Vins3 of the suppression circuit 40 through the second signal output terminal Vopd2 of the second switching circuit 82 and the second reference output terminal Vond2 of the second switching circuit 82, respectively. The fourth sensing unit 84 is connected to the fourth non-inverting input Viph4 and the fourth inverting input Vinh4 of the inhibit circuit 40.

Preferably, the third adjusting circuit 43 in the suppressing circuit 40 includes a third chopper ch3, a fifth transconductance amplifier Gm5, and a fourth chopper ch4 connected in this order. The three functions may be sequentially referred to in the present invention, and descriptions of the first chopper ch1, the first transconductance amplifier Gm1, and the second chopper ch2 are not repeated herein.

Further, the non-inverting output terminal of the fifth transconductance amplifier Gm5 is connected to the non-inverting input terminal of the third transconductance amplifier Gm3 through the fourth chopper ch4, to form a third non-inverting branch 432 of the third adjusting circuit 43. The inverting output terminal of the fifth transconductance amplifier Gm5 is connected to the inverting input terminal of the third transconductance amplifier Gm3 through the fourth chopper ch4, forming the third inverting branch 431 of the third regulating circuit 43.

Based on this, in a preferred embodiment, the input of the third normal phase leg 432 forms the third normal phase input Vips3 of the circuit input 402 of the suppression circuit 40, and the input of the third reverse phase leg 431 forms the third reverse phase input Vins3 of the circuit input 402. In this way, the third normal phase leg 432 and the third reverse phase leg 431 can receive the differential signal from the third sensing unit 83, especially from the second switching circuit 82, so as to adjust the output of the first transconductance amplifier Gm1, so that the offset voltage component in the output signal is further weakened, and the voltage signal carrying the current signal is further enhanced.

Similarly to the previous description, in the embodiments shown in fig. 10, 11, 12 and 15, the non-inverting output of the second transconductance amplifier Gm2 is connected to the non-inverting input of the fourth transconductance amplifier Gm4, forming the second non-inverting branch 422 of the second regulating circuit 42. The input of the second non-inverting branch 422 forms the second non-inverting input Viph2 of the circuit input 402 of the suppression circuit 40.

The inverting output terminal of the second transconductance amplifier Gm2 is connected to the inverting input terminal of the fourth transconductance amplifier Gm4, forming a second inverting branch 421 of the second adjusting circuit 42. The input of the second inverting branch 421 forms the second inverting input Vinh2 of the circuit input 402. In this way, the output of the third transconductance amplifier Gm3 can be adjusted, and the adaptability in the high bandwidth range and the attenuation of the voltage offset in the low bandwidth range can be realized.

Correspondingly, the fourth adjusting circuit 44 in the suppressing circuit 40 includes a sixth transconductance amplifier Gm6. The functional role of the sixth transconductance amplifier Gm6 is referred to the description of the second transconductance amplifier Gm2 in the present invention, and will not be repeated here.

Further, the non-inverting output terminal of the sixth transconductance amplifier Gm6 is connected to the inverting input terminal of the fourth transconductance amplifier Gm4, to form a fourth non-inverting branch 442 of the fourth adjusting circuit 44. The input of the fourth non-inverting branch 442 forms the fourth non-inverting input Viph4 of the circuit input 402 of the suppression circuit 40.

In addition, the inverting output terminal of the sixth transconductance amplifier Gm6 is connected to the non-inverting input terminal of the fourth transconductance amplifier Gm4, to form a fourth inverting branch 441 of the fourth adjusting circuit 44. The input of the fourth inverting branch 441 forms the fourth inverting input Vinh4 of the circuit input 402.

Based on this, the fourth normal phase branch 442 and the fourth reverse phase branch 441 can receive the differential signal from the fourth sensing unit 84, so as to adjust the output of the second transconductance amplifier Gm2, so that the offset voltage component in the output signal is suppressed in advance, and the voltage signal carrying the current signal is superimposed.

It should be understood that the "signal input", "reference input" and "signal output" of the upper Wen Suoshe "reference output" are named only according to the level of the signal applied thereto, and are not substantially different from each other except for the connection relationship in practical application. In particular, in the case of high level triggering, the levels applied at the "signal input" and the "signal output" are high levels, and thus may be named as "normal phase input" and "normal phase output", and the levels applied at the "reference input" and the "reference output" are low levels, and thus may be named as "reverse phase input" and "reverse phase output".

In summary, by constructing two sensing branches which are mutually matched, one of the two sensing branches is constructed as low bandwidth and high gain, and the other is constructed as high bandwidth and low gain, so that the characteristics of high gain and small drift of the former branch in a low bandwidth working range are utilized, the output of the latter branch in the low bandwidth range is equivalently replaced, the defect of large drift of the latter branch in the low bandwidth range is counteracted, the integral output of the sensor circuit has the characteristic of small drift even in the high bandwidth working range, and the high precision of measurement and the strong adaptability of a high bandwidth working scene are both considered.

It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.

The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.

Claims

1. A sensor circuit, comprising: the circuit comprises a first sensing unit, a second sensing unit and a suppression circuit, wherein the suppression circuit comprises a first regulating circuit and a second regulating circuit which are respectively connected to the output end of the circuit; the first sensing unit is connected to the first regulating circuit to form a first sensing branch, and the second sensing unit is connected to the second regulating circuit to form a second sensing branch; the first sensing branch is configured to have a low bandwidth and a high gain, and the second sensing branch is configured to have a high bandwidth and a low gain;

The first sensing branch is configured to output a high gain signal that at least attenuates low bandwidth drift formed by the second sensing branch on the circuit output;

the sensor circuit further comprises a first switching circuit arranged between the first sensing unit and the suppression circuit, wherein the first switching circuit is used for switching the flow direction of current on the first sensing unit and correspondingly adjusting the connection relation between the suppression circuit and a node for outputting signals on the first sensing unit.

2. The sensor circuit of claim 1, wherein the first conditioning circuit comprises a first chopper, a first transconductance amplifier, a second chopper, and a drift filter circuit connected in sequence, an output of the drift filter circuit connected to the circuit output; the second adjusting circuit comprises a second transconductance amplifier, and the output end of the second transconductance amplifier is connected to the output end of the drift filter circuit.

3. The sensor circuit of claim 2, wherein the drift filter circuit comprises a third transconductance amplifier, a first filter capacitor, and a second filter capacitor; one end of the first filter capacitor is connected with the non-inverting input end of the third transconductance amplifier, and the other end of the first filter capacitor is connected between the non-inverting output end of the third transconductance amplifier and the circuit output end; one end of the second filter capacitor is connected with the inverting input end of the third transconductance amplifier, and the other end of the second filter capacitor is connected between the inverting output end of the third transconductance amplifier and the circuit output end.

4. A sensor circuit according to claim 3, wherein a first trap is provided between the first transconductance amplifier and the third transconductance amplifier.

5. A sensor circuit according to claim 3, wherein the first conditioning circuit further comprises a noise filter circuit, the noise filter circuit being disposed between the drift filter circuit and the circuit output; the noise filter circuit comprises a first integrating capacitor and a second integrating capacitor, and the sum of the capacitance values of the first filtering capacitor and the second filtering capacitor is larger than the sum of the capacitance values of the first integrating capacitor and the second integrating capacitor.

6. The sensor circuit of claim 5, wherein the noise filtering circuit comprises a fourth transconductance amplifier; one end of the first integrating capacitor is connected with the non-inverting input end of the fourth transconductance amplifier, and the other end of the first integrating capacitor is connected with the inverting output end of the fourth transconductance amplifier; one end of the second integrating capacitor is connected with the inverting input end of the fourth transconductance amplifier, and the other end of the second integrating capacitor is connected with the non-inverting output end of the fourth transconductance amplifier;

The other end of the first filter capacitor, which is not connected with the non-inverting input end of the third transconductance amplifier, is connected to the non-inverting output end of the fourth transconductance amplifier; the other end of the second filter capacitor, which is not connected with the inverting input end of the third transconductance amplifier, is connected to the inverting output end of the fourth transconductance amplifier.

7. The sensor circuit of claim 6, wherein an inverting output of the first transconductance amplifier is connected to a non-inverting input of the third transconductance amplifier through the second chopper, and an inverting output of the third transconductance amplifier is connected to a non-inverting input of the fourth transconductance amplifier to form a first inverting branch of the first regulating circuit;

the positive phase output end of the first transconductance amplifier is connected to the negative phase input end of the third transconductance amplifier through the second chopper, and the positive phase output end of the third transconductance amplifier is connected to the negative phase input end of the fourth transconductance amplifier to form a first positive phase branch of the first regulating circuit;

the output end of the first normal phase branch forms a circuit normal phase output end of the circuit output end, and the output end of the first reverse phase branch forms a circuit reverse phase output end of the circuit output end; the input end of the first normal phase branch forms a first normal phase input end of the circuit input end of the suppression circuit, and the input end of the first reverse phase branch forms a first reverse phase input end of the circuit input end.

8. The sensor circuit of claim 7, wherein the suppression circuit further comprises a third regulation circuit comprising a third chopper, a fifth transconductance amplifier, and a fourth chopper connected in sequence, a positive phase output of the fifth transconductance amplifier being connected to a positive phase input of the third transconductance amplifier through the fourth chopper, forming a third positive phase leg of the third regulation circuit;

the inverting output end of the fifth transconductance amplifier is connected to the inverting input end of the third transconductance amplifier through the fourth chopper to form a third inverting branch of the third regulating circuit;

the input end of the third normal phase branch forms a third normal phase input end of the circuit input end of the suppression circuit, and the input end of the third reverse phase branch forms a third reverse phase input end of the circuit input end.

9. The sensor circuit of claim 6, wherein a non-inverting output of the second transconductance amplifier is connected to a non-inverting input of the fourth transconductance amplifier to form a second non-inverting branch of the second regulating circuit; the input end of the second normal phase branch forms a second normal phase input end of the circuit input end of the suppression circuit;

The inverting output end of the second transconductance amplifier is connected with the inverting input end of the fourth transconductance amplifier to form a second inverting branch of the second regulating circuit; the input of the second inverting branch forms a second inverting input of the circuit input.

10. The sensor circuit of claim 9, wherein the suppression circuit further comprises a fourth conditioning circuit comprising a sixth transconductance amplifier; the positive phase output end of the sixth transconductance amplifier is connected with the negative phase input end of the fourth transconductance amplifier to form a fourth positive phase branch of the fourth regulating circuit; the input end of the fourth normal phase branch forms a fourth normal phase input end of the circuit input end of the suppression circuit;

the inverting output end of the sixth transconductance amplifier is connected with the non-inverting input end of the fourth transconductance amplifier to form a fourth inverting branch of the fourth regulating circuit; the input of the fourth inverting branch forms a fourth inverting input of the circuit input.

11. The sensor circuit of claim 2, wherein the suppression circuit further comprises a first feedback circuit corresponding to the first regulation circuit, the first feedback circuit disposed between the circuit output and the output of the second chopper, the first feedback circuit comprising a fifth chopper, a seventh transconductance amplifier, and a sixth chopper connected in sequence.

12. The sensor circuit of claim 11, wherein the suppression circuit further comprises a gain adjustment circuit disposed between the first feedback circuit and the circuit output, the gain adjustment circuit for adjusting a gain of the suppression circuit.

13. The sensor circuit of claim 12, wherein the gain adjustment circuit comprises a first configuration resistor connected in series with a first inverting branch in the first adjustment circuit, a second configuration resistor connected in series with a first non-inverting branch in the first adjustment circuit, and a third configuration resistor connected in parallel between the first inverting branch and the first non-inverting branch.

14. The sensor circuit of claim 2, wherein the suppression circuit further comprises a second feedback circuit corresponding to the second regulation circuit, the second feedback circuit disposed between the circuit output and the output of the second transconductance amplifier, the second feedback circuit comprising an eighth transconductance amplifier.

15. The sensor circuit of claim 14, wherein the suppression circuit further comprises a gain adjustment circuit disposed between the second feedback circuit and the circuit output, the gain adjustment circuit for adjusting a gain of the suppression circuit.

16. The sensor circuit of claim 2, wherein the suppression circuit further comprises a ripple cancellation circuit; the inverting voltage input end of the ripple cancellation circuit is connected with the non-inverting current output end and is connected to the inverting output end of the first transconductance amplifier; the ripple cancellation circuit has a non-inverting voltage input connected to the inverting current output and to the non-inverting output of the first transconductance amplifier.

17. The sensor circuit of claim 16, wherein the ripple cancellation circuit comprises an integral chopper circuit.

18. The sensor circuit of claim 17, wherein the integrating chopper circuit comprises a seventh chopper, a ninth transconductance amplifier, a tenth transconductance amplifier, an eighth chopper, a third integrating capacitor, and a fourth integrating capacitor; the third integrating capacitor is arranged between the inverting input end and the non-inverting output end of the ninth transconductance amplifier, and the fourth integrating capacitor is arranged between the non-inverting input end and the inverting output end of the ninth transconductance amplifier.

19. The sensor circuit of claim 18, wherein the integrating chopper circuit further comprises at least one of a configuration resistor and an eleventh transconductance amplifier;

The configuration resistor comprises a fourth configuration resistor and a fifth configuration resistor, the fourth configuration resistor is connected with the inverting input end of the ninth transconductance amplifier, and the fifth configuration resistor is connected with the non-inverting input end of the ninth transconductance amplifier;

the non-inverting output end of the eleventh transconductance amplifier is connected with the inverting input end of the ninth transconductance amplifier, and the inverting output end of the eleventh transconductance amplifier is connected with the non-inverting input end of the ninth transconductance amplifier.

20. The sensor circuit of claim 17, wherein the ripple cancellation circuit comprises at least one of a pre-high pass filter circuit, a pre-amplification circuit, and a second trap;

the front high-pass filter circuit comprises a third filter capacitor, a fourth filter capacitor, a first filter resistor and a second filter resistor;

the pre-amplifier circuit includes a twelfth transconductance amplifier.

21. The sensor circuit of claim 1, further comprising a first switching circuit disposed between the first sensing unit and the suppression circuit, the first switching circuit comprising a set of drive switches and a set of signal switches;

The driving switch group is at least used for driving the first sensing unit, and the signal switch group is at least used for outputting signal voltage generated after the first sensing unit is driven to the suppression circuit.

22. The sensor circuit of claim 21, wherein the first sensing unit comprises a first output node, a second output node, a third output node, and a fourth output node;

the driving switch group comprises a first driving branch, a second driving branch, a third driving branch and a fourth driving branch which are mutually connected in parallel, wherein the first driving branch is connected with a first driving switch in series, the second driving branch is connected with a second driving switch in series, the third driving branch is connected with a third driving switch in series, and the fourth driving branch is connected with a fourth driving switch in series;

the signal switch group comprises a first signal branch, a second signal branch, a third signal branch and a fourth signal branch which are mutually connected in parallel, wherein the first signal branch is connected with a fourth signal switch in series, the second signal branch is connected with the first signal switch in series, the third signal branch is connected with the second signal switch in series, and the fourth signal branch is connected with the third signal switch in series;

The first output node is connected to the first driving branch and the first signal branch, the second output node is connected to the second driving branch and the second signal branch, the third output node is connected to the third driving branch and the third signal branch, and the fourth output node is connected to the fourth driving branch and the fourth signal branch;

the action time sequences of the first driving switch and the first signal switch are basically the same, the action time sequences of the second driving switch and the second signal switch are basically the same, the action time sequences of the third driving switch and the third signal switch are basically the same, and the action time sequences of the fourth driving switch and the fourth signal switch are basically the same.

23. The sensor circuit of claim 22, wherein the first drive leg is further coupled in series with a seventh drive switch that operates in synchronization with the third drive switch; the first signal branch is also connected in series with a sixth signal switch, and the sixth signal switch and the second signal switch synchronously act; the first output node is connected between the first driving switch and the seventh driving switch and between the fourth signal switch and the sixth signal switch;

The second driving branch is also connected in series with an eighth driving switch, and the eighth driving switch and the fourth driving switch synchronously act; the second signal branch is also connected in series with a seventh signal switch, and the seventh signal switch and the third signal switch synchronously act; the second output node is connected between the second driving switch and the eighth driving switch and between the first signal switch and the seventh signal switch;

the third driving branch is also connected in series with a fifth driving switch, and the fifth driving switch and the first driving switch synchronously act; the third signal branch is also connected in series with an eighth signal switch, and the eighth signal switch and the fourth signal switch synchronously act; the third output node is connected between the third driving switch and the fifth driving switch and between the second signal switch and the eighth signal switch;

the fourth driving branch is also connected in series with a sixth driving switch, and the sixth driving switch and the second driving switch synchronously act; the fourth signal branch is also connected in series with a fifth signal switch, and the fifth signal switch and the first signal switch synchronously act; the fourth output node is connected between the fourth driving switch and the sixth driving switch and between the third signal switch and the fifth signal switch;

The first driving switch, the second driving switch, the third driving switch and the fourth driving switch are connected with one of an excitation voltage source or a grounding terminal, and the seventh driving switch, the eighth driving switch, the fifth driving switch and the sixth driving switch are connected with the other of the excitation voltage source or the grounding terminal;

the fourth signal switch, the first signal switch, the second signal switch and the third signal switch are connected with one of a first signal output end or a first reference output end of the first switching circuit, and the sixth signal switch, the seventh signal switch, the eighth signal switch and the fifth signal switch are connected with the other one of the first signal output end or the first reference output end.

24. The sensor circuit of claim 22, wherein the sensor circuit is configured to alternately trigger the first drive switch and the second drive switch, and to delay triggering the first signal switch a first delay time after triggering the first drive switch, and to delay triggering the second signal switch a second delay time after triggering the second drive switch.

25. The sensor circuit of claim 22, wherein the sensor circuit is configured to trigger a first drive switch, a second drive switch, a third drive switch, and a fourth drive switch sequentially each drive cycle, and delay a first delay time to trigger the first signal switch after the first drive switch triggers, delay a second delay time to trigger the second signal switch after the second drive switch triggers, delay a third delay time to trigger the third signal switch after the third drive switch triggers, and delay a fourth delay time to trigger the fourth signal switch after the fourth drive switch triggers.

26. The sensor circuit of claim 25, wherein the sensor circuit is configured to trigger a chopper in the suppression circuit for a first hold time in a first state and to trigger the chopper for a second hold time in a second state;

wherein a trigger rising edge of the chopper is at least aligned with a trigger rising edge of the first signal switch, and a first holding time is greater than or equal to a trigger duration of the first signal switch;

A trigger falling edge of the chopper aligned with a trigger rising edge of the second signal switch in the first state and aligned with a trigger rising edge of the third signal switch in the second state;

the first retention time is one-half of the second retention time.

27. The sensor circuit of claim 22, wherein the first switching circuit further comprises an output capacitance in parallel with the first signal branch.

28. The sensor circuit of claim 21, further comprising a clock circuit connected to the first switching circuit and the suppression circuit, respectively, for controlling at least an operation timing of a signal switch in the first switching circuit and an operation timing of a chopper in the suppression circuit.

29. The sensor circuit of claim 1, further comprising a third sensing unit and a fourth sensing unit, the suppression circuit further comprising a third regulation circuit and a fourth regulation circuit connected to the circuit outputs, respectively; the third sensing unit is connected to the third adjusting circuit, and the fourth sensing unit is connected to the fourth adjusting circuit.

30. The sensor circuit of claim 29, further comprising a second switching circuit disposed between the third sensing unit and the suppression circuit.

31. The sensor circuit of claim 1, wherein the first sensing unit and the second sensing unit comprise hall elements.

32. The sensor circuit of claim 31, wherein the first sensing unit comprises a first hall element and a second hall element; the first Hall node of the first Hall element is connected with the sixth Hall node of the second Hall element to form a first output node; the second Hall node of the first Hall element is connected with the seventh Hall node of the second Hall element to form a second output node; the third Hall node of the first Hall element is connected with the eighth Hall node of the second Hall element to form a third output node; the fourth Hall node of the first Hall element is connected with the fifth Hall node of the second Hall element to form a fourth output node;

the first sensing unit is connected to the suppression circuit through the first, second, third and/or fourth output nodes.

33. The sensor circuit of claim 31, wherein the first sensing unit comprises a first hall element, a second hall element, a third hall element, and a fourth hall element;

the first Hall node of the first Hall element, the eighth Hall node of the second Hall element, the eleventh Hall node of the third Hall element and the fourteenth Hall node of the fourth Hall element are connected to form a first output node;

the second Hall node of the first Hall element, the fifth Hall node of the second Hall element, the twelfth Hall node of the third Hall element and the fifteenth Hall node of the fourth Hall element are connected to form a second output node;

the third Hall node of the first Hall element, the sixth Hall node of the second Hall element, the ninth Hall node of the third Hall element and the sixteenth Hall node of the fourth Hall element are connected to form a third output node;

the fourth Hall node of the first Hall element, the seventh Hall node of the second Hall element, the tenth Hall node of the third Hall element and the thirteenth Hall node of the fourth Hall element are connected to form a fourth output node;

34. The sensor circuit of claim 31, wherein the first sensing unit comprises a first hall element and a second hall element; the first Hall node of the first Hall element is connected with the fifth Hall node of the second Hall element to form a first output node; the second Hall node of the first Hall element is connected with the eighth Hall node of the second Hall element to form a second output node; the third Hall node of the first Hall element is connected with the seventh Hall node of the second Hall element to form a third output node; the fourth Hall node of the first Hall element is connected with the sixth Hall node of the second Hall element to form a fourth output node;

35. A powered device comprising the sensor circuit of any of claims 1-34.