CN115290957A

CN115290957A - Hall sensing circuit

Info

Publication number: CN115290957A
Application number: CN202210932525.3A
Authority: CN
Inventors: 秦文辉; 盛云
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2022-11-04
Also published as: CN115598395A; CN115598395B; CN112526191B; CN112526191A

Abstract

The invention belongs to the field of measurement and discloses a Hall sensing circuit which comprises a Hall sensor, a rotary switch circuit connected with the Hall sensor and a text wave elimination chopper amplifier connected with the rotary switch circuit; the chopping amplifier for eliminating the text wave comprises a first amplifier, a second amplifier and a first negative feedback circuit, wherein the first amplifier and the second amplifier are connected in series; the first negative feedback circuit comprises a diploe eliminating circuit and a transconductance amplifier connected with the diploe eliminating circuit, and the output end of the transconductance amplifier is connected with the input end of the second amplifier; the diploe elimination loop comprises a chopper and an integrator, wherein the input end of the chopper is coupled with the output end of the second amplifier, the output end of the chopper is coupled with the input end of the integrator, and the output end of the integrator is coupled with the transconductance amplifier. The technical scheme realizes high bandwidth, high response speed, high measurement precision, low noise and low offset voltage.

Description

Hall sensing circuit

The application is a divisional application of an invention patent application with the application date of 2020, 11 and 20, and the application number of 202011314470.7, and the name of the invention is 'a Hall sensing circuit'.

Technical Field

The invention belongs to the field of measurement, and particularly relates to an improvement of a Hall sensing circuit.

Background

Current monitoring is widely used in high power circuit systems, such as motor or load control, inverter circuits, power factor correction and power monitoring systems, etc. In these systems, a current of several amperes to hundreds of even thousands or tens of thousands of amperes needs to be monitored, and the conventional current monitoring method for monitoring the voltage on the resistor through the series resistor causes great energy loss.

High current systems are typically monitored using hall sensors. According to the magnetic effect of the current, the conducting wire with the current forms a magnetic field proportional to the current around, the size of the magnetic field can be detected through the Hall effect, and then the size of the current in the conducting wire can be monitored. Hall sensors are an important component in magnetic sensors among others. The Hall sensor has the characteristics of high linearity and good consistency compared with other magnetic sensors, but the Hall sensor has general sensitivity and large offset voltage relative to an induction signal, and the measurement precision of the Hall sensor is seriously limited.

Methods for reducing the influence of the offset voltage of the hall sensor on the measurement are mainly classified into two types, static methods and dynamic methods. In the static method, a plurality of Hall sensors are connected in parallel to enable offset voltages of the Hall sensors to offset each other, but the method still has the effect of remaining the offset voltage close to the amplitude of an induction signal. The dynamic method can modulate the offset voltage of the hall sensor to high frequency, and then the offset voltage becomes a high-frequency Ripple superimposed on the signal, and some methods are still needed to eliminate the Ripple (Ripple).

The dynamic method is divided into two types according to different processing methods of the text wave signals. The common methods mainly have two schemes, the first adopts a low-pass filter for filtering, and the second adopts a wave trap based on sampling for removing.

Referring to fig. 1 and 2, using the low pass filter LPF scheme, the dynamic method employs the rotary switch circuit 104 to excite two of the four ports of the hall sensor 102 by the clock CLK/CLKN or periodic rotation and correspondingly performs voltage detection on the other two ports. The launch port is driven by the CLK clock signal and the output port is driven using the CLK clock inverted signal CLKN.

The output waveform Vo1 includes two portions. The first part is a signal voltage Vh induced by the Hall sensor, the other part is a high-frequency signal converted from an offset voltage Vos after Hall modulation, the high-frequency signal is represented as a square wave at a rotation frequency, and the effective signal frequency of the Hall sensor is unchanged Vh. Vo1 is amplified by a Low Offset amplifier 106 (Low Offset Amp) of the subsequent stage to output Vo2, and Vo2 is filtered by a Low Pass Filter (LPF) of the subsequent stage to output (via VOP/VON port). A Low Pass Filter (LPF) 108 filters out the modulated offset voltage and retains the signal Vo3.

In order to suppress the ripple caused by Vos completely, the bandwidth of the LPF needs to be much smaller than the rotation frequency, which limits the signal bandwidth and makes the response speed of the signal path slow and the response time long. To better suppress the ripple, a second or higher order low pass filter is required, which further deteriorates the response speed.

Referring to fig. 3, a scheme of using a Notch Filter (NF) 110 using a low pass Filter is used. Unlike low pass filters, traps are used to filter out ripple instead of low pass filters, and traps filter out ripple much more efficiently than low pass filters.

The effect of the trap filter 110 is related to the trap frequency point, and when the trap frequency is identical to the SPIN Freq, the ripple can be effectively filtered, and if the two frequencies have a difference, the filtering effect can be greatly reduced. Therefore, the trap is generally implemented by using a switched capacitor sampling method, and the sampling frequency is synchronized with the SPIN Freq, so that the trap frequency and the SPIN Freq can be completely the same. However, the switched capacitor sampling causes noise aliasing, deteriorates in-band noise, and limits the response time, the output is changed when the sampling clock is turned over, the response time is limited by the sampling frequency, and the response speed is slow.

Disclosure of Invention

In order to solve the above-mentioned technical problems, an object of the present invention is to provide a hall sensor circuit that removes ripples, and has no limitation on response speed, no aliasing noise, low offset voltage, low noise, and high response speed.

The invention relates to a Hall sensing circuit, comprising: the device comprises a Hall sensor, a rotary switch circuit connected with the Hall sensor and a text wave elimination chopper amplifier connected with the rotary switch circuit;

the text wave elimination chopper amplifier comprises a first amplifier, a second amplifier and a first negative feedback circuit, wherein the first amplifier and the second amplifier are connected in series; the first negative feedback circuit comprises a diploe eliminating circuit and a transconductance amplifier connected with the diploe eliminating circuit, and the output end of the transconductance amplifier is connected with the input end of the second amplifier;

the diploe elimination loop comprises a chopper and an integrator, wherein the input end of the chopper is coupled with the output end of the second amplifier, the output end of the chopper is coupled with the input end of the integrator, and the output end of the integrator is coupled with the transconductance amplifier.

As a further improvement of an embodiment of the present invention, the first amplifier is a chopper amplifier including a first transconductance amplifier and a first chopper connected to an input terminal of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier, and the input end of the second transconductance amplifier is connected with a second chopper; the input end of the first chopper is used as the input end of the chopping amplifier for eliminating the text wave, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the output end of the first negative feedback circuit is connected with the output end of the first transconductance amplifier and used for eliminating the output end diplonic signal of the first transconductance amplifier.

As a further improvement of the embodiment of the present invention, the text wave canceling chopper amplifier further includes a second negative feedback circuit, an input end of the second negative feedback circuit is connected to an output end of the second transconductance amplifier, and an output end of the second negative feedback circuit is connected to an input end of the second transconductance amplifier, and is configured to cancel a text wave signal at the input end of the second transconductance amplifier; the second negative feedback circuit is similar to the first negative feedback circuit in structure, also comprises an acoustic wave elimination circuit and a transconductance amplifier connected with the acoustic wave elimination circuit, and is connected with the input end of the second transconductance amplifier through a third chopper.

As a further improvement of an embodiment of the present invention, the hall sensing circuit further includes a synchronous clock signal generator, the synchronous clock signal generator generates a first clock and a second clock, and a clock period of the second clock is twice a clock period of the first clock; the first clock and the inverted signal of the first clock drive the first chopper and the second chopper; the second clock and the second clock inverted signal drive the third chopper.

As a further improvement of an embodiment of the present invention, said dipleg elimination loop includes a preamplifier having an output connected to an input of said chopper.

As a further improvement of one embodiment of the present invention, said text wave elimination loop comprises a high pass filter connected to an input of said preamplifier.

As a further improvement of an embodiment of the present invention, the diploe elimination loop includes a chopper, a transconductance amplifier and a transconductance integrator, an output end of the chopper is connected to an input end of the transconductance amplifier, and an output end of the transconductance amplifier is connected to an input end of the transconductance integrator.

As a further improvement of one embodiment of the present invention, the diploe elimination loop includes a chopper, a transconductance amplifier and a transconductance integrator, an input end of the chopper is connected to an output end of the transconductance amplifier, and an output end of the chopper is connected to an input end of the transconductance integrator.

As a further improvement of the embodiment of the present invention, the rotary switch circuit includes an excitation switch group and an output switch group, the control timing of the excitation switch group and the control timing of the output switch group have a time delay, a falling edge of the output switch group is advanced with respect to a corresponding excitation switch group, and a rising edge is delayed with respect to the corresponding excitation switch group.

A hall sensing circuit, comprising: the device comprises a Hall sensor, a rotary switch circuit connected with the Hall sensor and a text wave elimination chopper amplifier connected with the rotary switch circuit; the chopping amplifier for eliminating the diploma comprises a differential amplifier and a first diploma eliminating circuit, wherein the differential amplifier consists of a first operational amplifier and a second operational amplifier; the output ends of the first operational amplifier and the second operational amplifier are connected with three resistors in series; the input end of the first operational amplifier is connected with the second resistor, and the input end of the second operational amplifier is connected with the third resistor; the first operational amplifier and the second operational amplifier both comprise a first feedback port, the first feedback port is connected with the output end of the first diploe elimination loop, and the input end of the first diploe elimination loop is connected with the output ends of the first operational amplifier and the second operational amplifier;

each operational amplifier comprises a first amplifier, a second amplifier and a first negative feedback transconductance amplifier; the first amplifier is a chopper amplifier and comprises a first transconductance amplifier and a first chopper connected with the input end of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier and a second chopper connected with the input end of the second transconductance amplifier; the input end of the first chopper is used as the input end of each operational amplifier, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the input end of the first negative feedback transconductance amplifier is connected with the first feedback port of each operational amplifier, and the output end of the first negative feedback transconductance amplifier is connected with the output end of the first transconductance amplifier;

the first dipleg elimination loop comprises a chopper and an integrator, wherein the input end of the chopper is coupled with the output end of the second amplifier, the output end of the chopper is coupled with the input end of the integrator, and the output end of the integrator is coupled with the first negative feedback transconductance amplifier.

As a further improvement of one embodiment of the present invention, each of the first operational amplifier and the second operational amplifier comprises a second feedback port and a second wavelet elimination loop, the second feedback port is connected to an output end of the second wavelet elimination loop, and an input end of the second wavelet elimination loop is connected to output ends of the first operational amplifier and the second operational amplifier;

each operational amplifier comprises a second negative feedback transconductance amplifier of which the input end is connected with a second feedback port, and the second negative feedback transconductance amplifier is connected with the input end of the second transconductance amplifier through a third chopper; the second dipleg cancellation loop is similar in structure to the first dipleg cancellation loop and also comprises a chopper and an integrator, wherein an input end of the chopper is coupled with an output end of the second amplifier, an output end of the chopper is coupled with an input end of the integrator, and an output end of the integrator is coupled with the second negative feedback transconductance amplifier.

As a further improvement of an embodiment of the present invention, said first and/or second acoustic cancellation circuits are/is the acoustic cancellation circuit described above.

Compared with the prior art, the invention has the advantages that the text wave eliminating chopping amplifying circuit adopts the text wave eliminating loop formed by the chopper and the integrator as the feedback loop, thereby realizing the elimination of ripple signals without limiting the response speed and aliasing noises, and realizing the Hall sensor circuit with low offset voltage, low noise and high response speed.

Drawings

FIG. 1 is a block diagram of a prior art Hall sensor rotary excitation scheme incorporating a low pass filter and low pass amplifier;

FIG. 2 is a timing diagram of signals for a prior art Hall sensor rotary excitation in combination with a low pass filter and a low pass amplifier;

FIG. 3 is a block diagram of a prior art Hall sensor rotational excitation in combination with a low pass filter and trap scheme;

FIG. 4 is a frame diagram of a Hall sensor rotary excitation scheme of the present application;

FIG. 5 is a schematic diagram of the circuit structure of the rotary switch of the present application;

FIG. 6 is a timing diagram of the two-phase excitation clock signal and switch control of the present application;

FIG. 7 is a timing diagram of the four phase activation clock signals and switch control of the present application;

FIG. 8 is a schematic diagram of a first embodiment of a chopper amplifier for diploma cancellation;

FIG. 9 is a schematic diagram of six embodiments of a cancellation loop;

FIG. 10 is a schematic diagram of the chopper structure;

FIG. 11 is a schematic diagram of a second embodiment of a chopper amplifier for diploma cancellation;

fig. 12 is a schematic diagram of an operational amplifier implementation in a text wave canceling chopper amplifier.

Detailed Description

The following detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings to assist those skilled in the art in understanding the present invention. In this application, "bank" is used to represent a plurality of electronic devices of the same type, for example, a sampling capacitor bank represents a plurality of sampling capacitors, and a switch bank represents a plurality of switches having the same function or switches driven by the same clock. In this application, "input" means a positive input port and a negative input port, and "output" means a positive output port and a negative output port.

Referring to fig. 4, a Hall sensing circuit framework architecture diagram is shown, which includes a Hall sensor (Hall) 402 and associated circuitry coupled to the Hall sensor 402, as well as circuitry for processing the Hall sensor 402 signal. A hall sensing circuit, a text wave cancellation chopper amplifier 406, and in the figure a single hall sensor 402 are included, and to further reduce the offset signal, one skilled in the art may optionally connect multiple hall sensors 402 in parallel.

The hall sensing circuit includes a combination of a hall sensor 402, a rotary switch circuit 404, and an westerncancellation chopper amplifier 406. The hall sensor 402 includes four ports, two for inputting excitation signals and two for outputting sensing signals. Four ports of the hall sensor 402 are connected to first, second, third, and fourth ports (a, b, c, d) of the rotary switch circuit 404, respectively. The rotary switch circuit 404 periodically energizes two ports in the hall sensor 402 while receiving output signals of the other two ports; the rotary switch circuit 404 outputs signals output by the other two ports to the diploe elimination chopper amplifier 406; the text wave cancellation chopper amplifier 406 and the rotary switch circuit 404 use the synchronous clock signal generator 408 as a clock signal source.

At least one chopper circuit in the text wave elimination chopper amplifier 406 can eliminate text wave signals, and the text wave elimination chopper amplifier 406 and the rotary switch circuit 404 have good synchronous response speed by using synchronous clock signals as driving signal source signals.

Referring to fig. 5, a schematic diagram of an embodiment of the rotary switch circuit 404 is shown, wherein the switches with the same reference number are the switch sets with the same operation timing, i.e. simultaneously turned on or simultaneously turned off. The operation timing of the reference numbers with S suffix is the same as that without S suffix, for example, the operation timing of P1/P1S, P2/P2S is the same.

The rotary switch circuit 404 is composed of an excitation switch group 502 that controls an excitation signal and a sensing signal output switch group 504. The hall sensor 402 comprises a first port a, a second port b, a third port c and a fourth port d; the excitation switch group 502 includes: a first switch group P1 for forming an excitation signal loop at the first port a and the third port c, and a second switch group P2 for forming an excitation loop at the second port b and the fourth port d; a third switch group P3 for forming an excitation signal loop at the third port c and the first port a and a fourth switch group P4 for forming an excitation signal loop at the fourth port d and the second port b; the output switch set 504 includes: a first output switch group P1S for forming an output loop at the second port b and the fourth port d, and a second output switch group P2S for forming an output loop at the third port c and the first port a; a third output switch group P3S for forming an output loop at the fourth port d and the second port, and a fourth switch group P4S for forming an output loop at the first port a and the third port c. And the first to fourth switch groups respectively comprise a switch connected with the excitation signal port and a switch to the ground. The specific connection modes of the excitation switch group 502 and the output switch group 504 and the switches are as follows: (for simplicity, only switch numbers are identified) the first port a is connected to P1, P3, P4S, P S, the second port b is connected to P2, P4, P1S, P S, the third port c is connected to P3, P1, P2S, P S, and the fourth port d is connected to P4, P2, P3S, P S.

The output switch group 504 of the rotary switch circuit 404 is connected to an output capacitor Cs, a first pole of the output capacitor Cs is a positive output terminal VOP of the rotary switch circuit 404, and a second pole of the output capacitor Cs is a negative output terminal VON of the rotary switch. The output capacitor Cs is used for sampling the output voltage generated by the hall sensor 402, and the output voltage Vo1 is the sum of the voltage Vh and the voltage Vos of the effective signal Vh of the hall sensor 402.

The rotary switch circuit 404 performs four-phase or two-phase excitation on the hall sensor 402 and receives signals through two other ports except for an excitation port under the action of the excitation switch group 502 and the output switch group 504 under the switch control timing. The following table is prepared according to the mapping relation of the phase, the excitation port and the direction, the sampling port and the direction, the signal direction and the offset voltage direction:

in the table, "+, -" indicates the direction of the hall voltage Vh and the offset voltage Vos, and "→" indicates the direction of the voltage of the excitation port or the output port.

Fig. 5 and 6 are clock signals generated by the synchronous clock signal generator 408, and control timings of the above-described switching components. The synchronous clock signal generator 408 generates a first clock C1 and a second clock C2, wherein the clock C1 period of the second clock is twice the clock C2 period of the first clock. The activation process of the rotary switch circuit 404 is further described below with reference to a clock and control timing.

Fig. 6 shows the control timing of the two-phase rotary switch, and the synchronous clock signal generator 408 generates the clock signal C1 and the clock signal inversion driving signal C1N. In the first clock period t1, the switches P1 and P1S are closed, the excitation port sum direction is a → c, the first port a and the third port c form an excitation loop, the output port sum direction is b → d, and the Hall voltage Vh sum offset voltage Vos is output in the positive direction. And in the second clock period t2, the switches P1 and P1S are opened while the switches P2 and P2S are closed, the excitation port and the direction are b → d, namely the second port b and the fourth port d form an excitation loop, the output port and the direction are c → a, the Hall voltage Vh is output in a positive direction, and the offset voltage Vos is output in a negative direction.

Therefore, the offset voltage Vos changes along with the direction of the clock signal C1, the signal of the offset voltage Vos is modulated into a high-frequency signal with the same frequency as the clock signal, and the high-frequency signal is superimposed on the hall voltage Vh signal in a mode of a text wave signal to form the output signal Vo1 of the rotary switch circuit, and the high-frequency signal is convenient for subsequent processing in a mode of filtering and the like.

In fig. 6, the switches P3, P4, P3S and P4S are always kept in an open state, i.e., the excitation signals of the two phases c → a, d → b and the corresponding output signals are shielded by means of the control timing. In fig. 7, the four-phase rotary switch circuit 404 further includes the two-phase excitation signal and the corresponding output signal.

Four different timings are included in the four-phase rotary switch circuit 404. The timing of the activation of the switch bank 502 and the output switch bank 504 at the first clock cycle t1 and the second clock cycle t2 is different from the timing of the operation of the two-phase rotary switch shown in fig. 3. In a third clock cycle t3, the P3, P3S are closed, with the excitation port and direction c → a output port and direction d → b; the P4, P4S closure actuates the port and direction d → b and the output port and direction a → c at four clock cycles t 4. It can be seen that the sign of the offset signal Vos output at the 4-phase rotary switch circuit 404 changes with the direction of the clock signal and is superimposed on the hall voltage Vh signal in the form of a wen wave signal to form the four-phase rotary switch circuit output signal Vo1.

It should be noted that the two-phase rotary switch circuit or the four-phase rotary switch circuit has a certain time delay (as labeled d1 to d4 in fig. 6 and 7) to the control timing of the excitation and output switch groups. The falling edges of the output switch sets P1S-P4S lead the corresponding excitations P1-P4 a little and the rising edges lag the corresponding excitations P1-P4 a little. Because the falling/rising edges of P1-P4 mean that the switch is in the switching process, and the output of the HALL is not established at this time, P1S-P4S has a dead time at the position corresponding to the edge of P1-P4, and the error caused by amplifying the output which is not established by the HALL by the later stage sampling is avoided. Meanwhile, the clock of the later-stage ripple cancellation chopper amplifier needs to be aligned with the falling edges of P1S-P4S, so that the modulated Vh can be well suppressed by the ripple cancellation loop of the later-stage amplifier.

Referring to fig. 4 and 8, positive and negative input ports (VIP, VIN) of the text wave cancellation chopper amplifier 406 are connected to positive and negative output ports (VOP, VON) of the rotary switch circuit 404, respectively. Text wave canceling chopper amplifier 406 includes a variety of implementations, and this application illustrates two exemplary implementations.

Fig. 8 shows a first implementation of text wave canceling chopper amplifier 406. It comprises a first amplifier 802, a second amplifier 804 and a first negative feedback circuit 806 connected in series; the first amplifier 802 comprises a first transconductance amplifier GM1 and a first chopper Ch1 connected to an input end of the first transconductance amplifier GM1, an input end of the first chopper Ch1 serves as an input end of the diploe canceling chopper amplifier 406, and the chopper Ch1 is used for canceling an offset voltage of the first transconductance amplifier GM 1.

The second amplifier 804 comprises a second transconductance amplifier GM2 and a second chopper Ch2 connected with the input end of the second transconductance amplifier GM 2; the input end of the second chopper Ch2 is connected with the output end of the first transconductance amplifier GM 1; an input terminal of the first negative feedback circuit 806 is connected to an output terminal of the second transconductance amplifier GM2.

The first negative feedback circuit 806 is used to suppress the second transconductance amplifier GM2 diploe output. The amplifier comprises a text wave elimination loop RRL and a transconductance amplifier GMa connected with the text wave elimination loop RRL, and the output end of the transconductance amplifier GMa is used as a first negative feedback circuit output end 806. The input end of the transconductance amplifier GMa is connected with the output end of the ripple wave eliminating loop RRL, and the ripple wave signal in the output signal collected by the text wave eliminating loop RRL is demodulated, amplified and negatively fed back to the output port of the first transconductance amplifier GM1 to inhibit the output ripple wave.

In fig. 8, if the rotary switch circuit 404 performs four-phase sampling, the chopping text wave cancellation chopper amplifier 406 further comprises a second negative feedback circuit 808, an input end of the second negative feedback circuit 808 is connected with an output end of the second transconductance amplifier GM2, and an output end of the second negative feedback circuit 808 is connected with an input end of the second transconductance amplifier GM2. The second negative feedback circuit 808 has the same structure as the first negative feedback circuit 806, and an output end thereof is connected to an input end of a third chopper Ch3, and an output end of the third chopper Ch3 is connected to an input end of a second stage transconductance amplifier GM2.

For the four-phase rotary switch circuit, the first chopper Ch1 and the second chopper Ch2 are driven by the first clock C1 and the first clock inversion signal C1N, and the second clock signal C2 has twice the clock cycle of the first clock signal C1 and drives the third chopper. So that the dipleg cancellation path of the second negative feedback circuit 808 can effectively suppress the ripple at one-half of the rotation frequency. For a two-phase rotary switch circuit, the second negative feedback circuit 808 may be removed or electrically turned off.

Referring to fig. 9, several typical implementations of the RRL are listed, and the RRL has a common feature that the RRL mainly includes a chopper and an integrator, the chopper can demodulate the ripple in the output signal back to DC, the ripple is amplified by the integrator and fed back to the signal path, and the RRL can suppress the output ripple of the amplifier to be negligible relative to the hall signal through negative feedback.

With continued reference to fig. 9, first text wave elimination loop 902 includes chopper ch connected to the input of integrator Int, and integrator Int. The second loop 904 adds a preamplifier GM2 whose output is connected to the input of said chopper Ch, on the basis of the first loop RRL.

For the first ripple cancellation loop 902, the residual ripple of which is determined by the offset voltage of the amplifier in the integrator Int, a pre-amplifier GM2 is added before the chopper Ch, which can further reduce the ripple and suppress the ripple by the gain of the pre-amplifier GM2 at the chopping frequency.

The third dipleg elimination loop 906 adds a high pass filter HPF to the second dipleg elimination loop 904, the high pass filter HPF being connected to the preamplifier GM2 input. The high pass filter HPF is an RC structure as shown in the figure. The high pass filter HPF may allow the high frequency text wave signal to pass through and block the hall signal Vh before the preamplifier so that the RRL processes the hall signal Vh less, only the ripple. Since the hall signal Vh, which has a frequency lower than the chopping frequency, is modulated by the chopper ch to the chopping frequency and is suppressed by the low-pass characteristic of the integrator Int while passing through the integrator, the RRL does not feed back the useful hall signal Vh, but feeds back only the ripple and suppresses the ripple.

The fourth dipleg elimination loop 908 dipleg elimination loop comprises a chopper Ch, a transconductance amplifier GM1 and a transconductance integrator Int ', wherein the output end of the chopper Ch is connected with the input end of the transconductance amplifier, and the output end of the transconductance amplifier GM1 is connected with the input end of the transconductance integrator Int'.

The fifth dipleg elimination loop 910 includes a chopper Ch, a transconductance amplifier GM1, and a transconductance integrator Int ', wherein an input terminal of the chopper Ch is connected to an output terminal of the transconductance amplifier GM1, and an output terminal of the chopper Ch is connected to an input terminal of the transconductance integrator Int'. Chopper Ch of fifth dipleg cancellation loop 910 may be moved from the input across to the amplifier to the output, helping to reduce the residual ripple amplitude.

Referring to the implementation of the chopper shown in fig. 10, the chopper includes a first switch group S1 forward connected to the input and output terminals and a second switch group S2 backward connected to the output and output terminals, the first switch group drives the clock source to be C1 or C2, correspondingly, the second switch group drives the clock source to be C1N or C2N, and the switching output signal of the chopper is continuously inverted along with the clock signal.

Fig. 11 shows a second implementation of the chopper amplifier 406 for removing text waves, wherein the implementation of the chopper and the text wave removal loop RRL is the same as the implementation of the first chopper amplifier 406 for removing text waves.

The acoustic wave canceling chopper amplifier 406 includes a differential amplifier composed of a first operational amplifier OPAMP1 and a second operational amplifier OPAMP2, and an acoustic wave canceling circuit RRL. The output ends of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 are connected with three resistors (R1, R2 and R3) in series; the input end of the first operational amplifier OPAMP1 is connected with a second resistor R2, and the input end of the second operational amplifier OPAMP2 is connected with a third resistor R3; the first operational amplifier OPAMP1 or the second operational amplifier OPAMP2 comprises a first feedback port VIP1/VIN1, the positive input terminal VIP1 and the negative input terminal VIN1 of the first feedback port VIP1/VIN1 are connected with the positive output terminal VOP and the negative output terminal VON of the wenbo cancellation loop RRL, respectively, and the positive input terminal VIP and the negative input terminal VIN of the wenbo cancellation loop RRL are connected with the output terminals of the first operational amplifier OPAMP1 and the second operational amplifier OPAMP 2.

The operational amplifiers (OPAMP 1/OPAMP 1) described with reference to fig. 12 include a first amplifier 1202, a second amplifier 1204, and a first negative feedback transconductance amplifier GMa; the first amplifier 1202 comprises a first transconductance amplifier GM1 and a first chopper Ch1 connected with the input end of the first transconductance amplifier GM1, and the second amplifier 1204 comprises a second transconductance amplifier GM2 and a second chopper Ch2 connected with the input end of a second transconductance amplifier GMb; the input end of the first chopper Ch1 is used as the input end of an operational amplifier, and the input end of the second chopper Ch2 is connected with the output end of the first transconductance amplifier GM 1; the input end of the first negative feedback transconductance amplifier Gma is connected with a first feedback port VIP1/VIN2 of the operational amplifier, and the output end of the first negative feedback transconductance amplifier Gma is connected with the output end of the first transconductance amplifier GM 1.

Referring to fig. 11 and 2 if the rotary switch circuit is 4-phase energized, the operational amplifier further includes a venturi cancellation loop RRL 'output connection connected to the second feedback port VIP2/VIN2, the input of the venturi cancellation loop RRL' being connected to the outputs of the first and second operational amplifiers OPAMP1 and OPAMP 2. Correspondingly, a second negative feedback transconductance amplifier GMb connected with the second feedback port VIP2/VIN2 at the internal input end of the operational amplifier, and a second negative feedback transconductance amplifier GMb is connected with the input end of the second transconductance amplifier Gmb through a third chopper Ch 3; the first chopper Ch1 and the second chopper Ch2 are driven by a first clock C1 and a first clock inversion signal C1N; the second clock C2 and the second clock inverted signal C2N drive the third chopper Ch3. The loop of the dipleg cancellation RRL', the second transconductance amplifier Gmb and the third chopper Ch3 can be electrically shielded or deleted from the circuit if the rotary switch circuit is 2-phase excited.

In summary, the present invention cooperates with the rotating switch circuit and the switching clock and clock edge of the post-stage ripple cancellation chopper amplifier, and the ripple cancellation loop in the post-stage ripple cancellation chopper amplifier is used to cancel the offset voltage modulated by the hall element. The two-phase rotary switch circuit and the four-phase rotary switch circuit can be compatible through a reasonable switching sequence. Through 2 loops, ripples at the rotating frequency and at the half position of the rotating frequency are respectively suppressed, and ripples caused by four-phase rotation can be effectively eliminated.

According to the invention, a low-pass or high-order low-pass filter with low cut-off frequency is not added in a signal path, a switch sampling circuit is not added, the bandwidth and delay time of the signal path are not influenced, and the noise aliasing effect caused by switch sampling is avoided, so that the high bandwidth, the high response speed, the high measurement precision, the small noise and the small offset voltage are realized. The measurement precision and the delay time are short enough, when the detected system current is over-current, the system can quickly receive an over-current signal and start protective measures to protect the safety of the whole system.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present application.

Claims

1. A hall sensing circuit, comprising: the device comprises a Hall sensor, a rotary switch circuit connected with the Hall sensor and a text wave elimination chopper amplifier connected with the rotary switch circuit;

the chopping amplifier for eliminating the text wave comprises a first amplifier, a second amplifier and a first negative feedback circuit, wherein the first amplifier and the second amplifier are connected in series; the first negative feedback circuit comprises a diploe eliminating circuit and a transconductance amplifier connected with the diploe eliminating circuit, and the output end of the transconductance amplifier is connected with the input end of the second amplifier;

2. The Hall sensing circuit according to claim 1, wherein the first amplifier is a chopper amplifier comprising a first transconductance amplifier and a first chopper connected to an input of the first transconductance amplifier; the second amplifier comprises a second transconductance amplifier, and the input end of the second transconductance amplifier is connected with a second chopper; the input end of the first chopper is used as the input end of the chopping amplifier for eliminating the text wave, and the input end of the second chopper is connected with the output end of the first transconductance amplifier; the output end of the first negative feedback circuit is connected with the output end of the first transconductance amplifier and used for eliminating the output end diplonic signal of the first transconductance amplifier.

3. The hall sensing circuit of claim 2 wherein the dipleg canceling chopper amplifier further comprises a second negative feedback circuit, an input terminal of the second negative feedback circuit being connected to an output terminal of the second transconductance amplifier, an output terminal of the second negative feedback circuit being connected to an input terminal of the second transconductance amplifier for canceling the dipleg signal at the input terminal of the second transconductance amplifier; the second negative feedback circuit is similar to the first negative feedback circuit in structure, also comprises an acoustic wave elimination circuit and a transconductance amplifier connected with the acoustic wave elimination circuit, and is connected with the input end of the second transconductance amplifier through a third chopper.

4. The Hall sensing circuit according to claim 3, further comprising a synchronous clock signal generator, wherein the synchronous clock signal generator generates a first clock and a second clock, and the clock period of the second clock is twice the clock period of the first clock; the first clock and the first clock inverted signal drive the first chopper and the second chopper; the second clock and the second clock inversion signal drive the third chopper.

5. The hall sensing circuit of claim 1 wherein the loop for removing the evanescent wave comprises a preamplifier having an output connected to an input of the chopper.

6. The Hall sensing circuit of claim 5, wherein said cancellation loop comprises a high pass filter coupled to an input of said preamplifier.

7. The hall sensing circuit of claim 1 wherein the diplonic cancellation loop comprises a chopper, a transconductance amplifier and a transconductance integrator, an output terminal of the chopper is connected to an input terminal of the transconductance amplifier, and an output terminal of the transconductance amplifier is connected to an input terminal of the transconductance integrator.

8. The hall sensing circuit of claim 1 wherein the diploe cancellation loop comprises a chopper, a transconductance amplifier and a transconductance integrator, an input terminal of the chopper being connected to an output terminal of the transconductance amplifier, and an output terminal of the chopper being connected to an input terminal of the transconductance integrator.

9. The Hall sensing circuit according to claim 1, wherein the rotary switch circuit comprises an excitation switch set and an output switch set, the excitation switch set and the output switch set have time delays in control timing, the falling edge of the output switch set is advanced with respect to the corresponding excitation switch set, and the rising edge is delayed with respect to the corresponding excitation switch set.

10. A hall sensing circuit, comprising: the device comprises a Hall sensor, a rotary switch circuit connected with the Hall sensor and a text wave elimination chopper amplifier connected with the rotary switch circuit; the chopping amplifier for eliminating the diploma comprises a differential amplifier and a first diploma eliminating circuit, wherein the differential amplifier consists of a first operational amplifier and a second operational amplifier; the output ends of the first operational amplifier and the second operational amplifier are connected with three resistors in series; the input end of the first operational amplifier is connected with the second resistor, and the input end of the second operational amplifier is connected with the third resistor; the first operational amplifier and the second operational amplifier both comprise a first feedback port, the first feedback port is connected with the output end of the first diploe elimination loop, and the input end of the first diploe elimination loop is connected with the output ends of the first operational amplifier and the second operational amplifier;

11. The hall sensing circuit of claim 10 wherein the first and second operational amplifiers each comprise a second feedback port and a second dipleg cancellation loop, the second feedback port being connected to an output of the second dipleg cancellation loop, an input of the second dipleg cancellation loop being connected to outputs of the first and second operational amplifiers;

12. A hall sensing circuit according to any of claims 10 to 11 wherein the first and/or second westernremoving circuits are westernremoving circuits according to any of claims 5 to 8.