CN114860633A - Automatic calibration method and device for time delay signal, terminal equipment and storage medium - Google Patents
Automatic calibration method and device for time delay signal, terminal equipment and storage medium Download PDFInfo
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Abstract
The application is applicable to the technical field of parameter calibration, and provides an automatic calibration method, an automatic calibration device, terminal equipment and a storage medium for a time delay signal, wherein the method comprises the following steps: determining a first adjusting range of a read delay parameter and a second adjusting range of a write delay parameter, determining a delay adjusting rectangular area according to the first adjusting range and the second adjusting range, accessing a double data rate processor according to the delay adjusting rectangular area, receiving a data result returned by the double data rate processor, selecting a plurality of alternative delay parameters meeting preset conditions according to the data result, determining a target delay parameter according to the plurality of alternative delay parameters, and calibrating the double data rate processor according to the target delay parameter. According to the method and the device, the target time delay parameter is dynamically selected based on the time delay adjustment rectangular area, the automatic calibration of the read-write time delay signal is realized, the production cost is reduced, the impedance control precision and the system stability are improved, and therefore the data processing efficiency is improved.
Description
Technical Field
The present application belongs to the technical field of parameter calibration, and in particular, to an automatic calibration method and apparatus for a delay signal, a terminal device, and a readable storage medium.
Background
Typically, a Double Data Rate (DDR) processor is installed in the embedded terminal. The DDR interface belongs to a high-speed signal interface, has high requirements on the sequence and the impedance of a PCB and a transmission line.
In the batch production process of embedded products, because of cost limitation, it is difficult to satisfy the strict impedance control required by the DDR, and when the impedance control is not proper, the read-write efficiency of the high-speed DDR data is affected. In DDR timing, the most critical signals are the double speed (dule Rate) aligned input/Output (DQ) signal and the Data Strobe (DQs) signal. The phenomenon of system crash or restart caused by accidental DDR instability is caused, and the overall quality of the embedded terminal equipment is influenced.
The related timing signal calibration method usually determines a fine tuning parameter with good stability according to a large number of samples and test tests, and solidifies the fine tuning parameter into a software version, however, the method has poor flexibility, cannot meet the difference of different PCB boards, and has small impedance control precision.
Disclosure of Invention
The embodiment of the application provides an automatic calibration method and device for a time delay signal, terminal equipment and a readable storage medium, and can solve the problems that a related time sequence signal calibration method is poor in flexibility, cannot meet the difference of different PCBs, and is low in impedance control precision.
In a first aspect, an embodiment of the present application provides an automatic calibration method for a time delay signal, including:
determining a first adjusting range of the reading time delay parameter and a second adjusting range of the writing time delay parameter;
determining a time delay adjustment rectangular area according to the first adjustment range and the second adjustment range;
accessing a double data rate processor according to the time delay adjusting rectangular region, receiving a data result returned by the double data rate processor, and selecting a plurality of alternative time delay parameters meeting preset conditions according to the data result;
and determining a target time delay parameter according to the plurality of alternative time delay parameters, and calibrating the double data rate processor according to the target time delay parameter.
In one embodiment, the determining a time delay adjustment rectangular area according to the first adjustment range and the second adjustment range includes:
determining the maximum value of the read time delay parameter and the minimum value of the read time delay parameter in the first adjusting range;
determining the maximum value and the minimum value of the write delay parameter in the second adjustment range;
and constructing a time delay adjustment rectangular area according to the read time delay parameter maximum value, the read time delay parameter minimum value, the write time delay parameter maximum value and the write time delay parameter minimum value.
In one embodiment, before the accessing the double data rate processor according to the rectangular region with the adjusted time delay and receiving the data result returned by the double data rate processor, the method includes:
selecting a target region in the double data rate processor;
and writing preset data into the target area and emptying a cache.
In an embodiment, the accessing the double data rate processor according to the rectangular delay adjustment region, receiving a data result returned by the double data rate processor, and selecting a plurality of candidate delay parameters meeting a preset condition according to the data result includes:
traversing each pair of time delay parameters in the time delay adjustment rectangular area according to a preset sequence, and inputting each pair of time delay parameters into the double data rate processor; each pair of time delay parameters comprises a reading time delay parameter and a writing time delay parameter;
accessing the double data rate processor and receiving a data result returned by the double data rate processor;
selecting alternative time delay parameters according to the data result until a plurality of alternative time delay parameters meeting preset conditions are selected; the plurality of candidate latency parameters includes at least two read candidate latency parameters and at least two write candidate latency parameters.
In an embodiment, the selecting the candidate delay parameters according to the data result until a plurality of candidate delay parameters satisfying a preset condition are selected includes:
comparing the data result with the preset data;
when the data result is detected to be consistent with the preset data, determining a read time delay parameter corresponding to the data result as a read alternative time delay parameter, and determining a write time delay parameter corresponding to the data result as a write alternative time delay parameter;
and until all the time delay parameters are detected, or the difference value of the write alternative time delay parameters is less than or equal to a preset threshold value.
In one embodiment, the determining a target delay parameter according to the plurality of candidate delay parameters and calibrating the double data rate processor according to the target delay parameter includes:
detecting whether the alternative time delay parameter is illegal data or not;
when detecting that each alternative time delay parameter is not illegal data, calculating according to the write alternative time delay parameter and the read alternative time delay parameter to obtain a target time delay parameter;
and calibrating the double data rate processor according to the target time delay parameter.
In an embodiment, after detecting whether the candidate delay parameter is illegal data, the method further includes:
and when any optional time delay parameter is detected to be illegal data, generating and displaying calibration failure information.
In a second aspect, an embodiment of the present application provides an apparatus for automatically calibrating a time delay signal, including:
the data determining module is used for determining a first adjusting range of the reading delay parameter and a second adjusting range of the writing delay parameter;
the matrix determining module is used for determining a time delay adjusting rectangular area according to the first adjusting range and the second adjusting range;
the parameter selection module is used for accessing the double data rate processor according to the time delay adjustment rectangular region, receiving a data result returned by the double data rate processor, and selecting a plurality of alternative time delay parameters meeting preset conditions according to the data result;
and the parameter calibration module is used for determining a target time delay parameter according to the plurality of candidate time delay parameters and calibrating the double data rate processor according to the target time delay parameter.
In one embodiment, the delay adjustment rectangular area determining module includes:
a first parameter determining unit, configured to determine a maximum value of the read delay parameter and a minimum value of the read delay parameter in the first adjustment range;
a second parameter determining unit, configured to determine a maximum value and a minimum value of the write delay parameter in the second adjustment range;
and the matrix determining unit is used for constructing a time delay adjusting rectangular area according to the read time delay parameter maximum value, the read time delay parameter minimum value, the write time delay parameter maximum value and the write time delay parameter minimum value.
In one embodiment, the apparatus further comprises:
a region selection module for selecting a target region in the double data rate processor;
and the data writing module is used for writing preset data into the target area and emptying the cache.
In one embodiment, the parameter selecting module includes:
the traversal unit is used for traversing each pair of time delay parameters in the time delay adjustment rectangular area according to a preset sequence and inputting each pair of time delay parameters into the double data rate processor; each pair of time delay parameters comprises a reading time delay parameter and a writing time delay parameter;
the access unit is used for accessing the double data rate processor and receiving a data result returned by the double data rate processor;
the data selection unit is used for selecting alternative time delay parameters according to the data result until a plurality of alternative time delay parameters meeting preset conditions are selected; the plurality of candidate latency parameters includes at least two read candidate latency parameters and at least two write candidate latency parameters.
In one embodiment, the data selecting unit includes:
the comparison subunit is used for comparing the data result with the preset data;
a parameter determining subunit, configured to determine, when it is detected that the data result is consistent with the preset data, a read delay parameter corresponding to the data result as a read candidate delay parameter, and a write delay parameter corresponding to the data result as a write candidate delay parameter;
and the parameter detection subunit is used for detecting all the time delay parameters or the difference value of the write candidate time delay parameters is less than or equal to a preset threshold value.
In one embodiment, the parameter calibration module includes:
a parameter detection unit, configured to detect whether the alternative delay parameter is illegal data;
the calculating unit is used for calculating to obtain a target time delay parameter according to the write alternative time delay parameter and the read alternative time delay parameter when detecting that each alternative time delay parameter is not illegal data;
and the calibration unit is used for calibrating the double data rate processor according to the target time delay parameter.
In one embodiment, the parameter calibration module further includes:
and the information generating unit is used for generating and displaying calibration failure information when any one of the alternative time delay parameters is detected to be illegal data.
In a third aspect, an embodiment of the present application provides a terminal device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor, when executing the computer program, implements the method for automatically calibrating a time delay signal according to any one of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the method for automatically calibrating a time delay signal according to any one of the first aspect is implemented.
In a fifth aspect, the present application provides a computer program product, which when run on a terminal device, causes the terminal device to execute the method for automatically calibrating a time delay signal according to any one of the above first aspects.
Compared with the prior art, the embodiment of the application has the advantages that: the time delay adjusting rectangular area constructed by the read-write time delay parameters accesses the double data rate processor, the target time delay parameters are dynamically selected based on the received data results, automatic calibration of read-write time delay signals is achieved, the production cost of the PCB is reduced, meanwhile, the impedance control precision of the PCB and the system stability of the PCB are improved, and therefore the data processing efficiency of the DDR processor is improved.
It is understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, and are not described herein again.
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In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of an automatic calibration method for a delay signal according to an embodiment of the present application;
fig. 2 is a schematic flowchart of step S103 of an automatic calibration method for a delay signal according to an embodiment of the present application;
fig. 3 is a schematic flowchart of step S104 of an automatic calibration method for a delay signal according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an apparatus for automatically calibrating a delay signal according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The automatic calibration method for the time delay signal provided by the embodiment of the application can be applied to terminal devices such as a mobile phone, a tablet personal computer, a wearable device, a vehicle-mounted device, an Augmented Reality (AR)/Virtual Reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, and a Personal Digital Assistant (PDA), and the embodiment of the application does not limit the specific type of the terminal device at all.
Fig. 1 shows a schematic flow chart of an automatic calibration method for a time delay signal provided in the present application, which can be applied to the above-mentioned notebook computer by way of example and not limitation.
S101, determining a first adjusting range of the reading time delay parameter and a second adjusting range of the writing time delay parameter.
Specifically, during the read/write process of the DDR, both the read timing signal and the write timing signal are aligned at double speed (Duel Rate), so that the error accuracy required by the timing alignment of the read timing signal and the write timing signal is very high (pico-sec ps level), for example, the DDR3(1600MHz) processor requires that the timing alignment accuracy of the read timing signal and the write timing signal is 100 pico-sec (ps). The DQ/DQS timing signal has high requirements on the impedance control precision and consistency of the PCB, and the alignment precision of the DQ/DQS timing signal is within 55 ohm +/-10% in general. The common PCB has the condition that the accuracy of part of signal impedance does not meet the standard or the signal impedance of each PCB is different. In order to reduce the cost and maintain the system stability, the read-write timing signals need to be finely adjusted according to the difference of the PCB, i.e. a better read-write timing signal needs to be found. Setting a Boot (Boot/Boot) stage for automatic calibration (specifically, setting an open source code item, Universal Boot Loader, U-Boot, which follows GPL terms, for booting various embedded operating systems such as Linux).
In particular, for DDR processors, the timing of the DQ and DQs signals during read and write operations is not the same: when reading, the DQ signal center and the DQS signal center are aligned; during writing operation, the center of the DQ signal is aligned with the rising edge and the falling edge of the DQs signal, respectively, and when a difference or fluctuation occurs in the line impedance, a large influence is exerted on the timing sequence of the DQ and DQs signals, which may cause that the DQ and DQs signals cannot be aligned or exceed the range. A time delay controller is respectively designed for the time sequences of a read signal and a write signal of a DQ signal and a DQS signal in a DDR processor, the time sequences of the read signal and the write signal can be finely adjusted through the time delay controller, and the fine adjustment range is set by the time delay controller.
Specifically, two parameters of a read delay signal and a write delay signal in the DDR processor are jointly calibrated. Correspondingly, a first adjusting range of the read delay parameter (including [ the minimum value of the read delay parameter, the maximum value of the read delay parameter ]) and a second adjusting range of the write delay parameter (including [ the minimum value of the write delay parameter, the maximum value of the write delay parameter ]) are determined in advance through the delay controller.
And S102, determining a time delay adjustment rectangular area according to the first adjustment range and the second adjustment range.
Specifically, according to the first adjustment range of the read delay parameter and the second adjustment range of the write delay parameter, constructing a line of data as follows: from the minimum value of the read delay parameter to the maximum value of the read delay parameter, and the column data are: and the time delay adjustment rectangular area is from the minimum value of the write time delay parameter to the maximum value of the write time delay parameter.
S103, accessing a double data rate processor according to the time delay adjusting rectangular region, receiving a data result returned by the double data rate processor, and selecting a plurality of alternative time delay parameters meeting preset conditions according to the data result.
Specifically, each read delay parameter and each write delay parameter in the delay adjustment rectangular area are used for accessing the double data rate processor, receiving a data result returned by the double data rate processor, and detecting whether the currently input read delay parameter and write delay parameter are alternative delay parameters according to the data result until a plurality of alternative delay parameters meeting preset conditions are selected.
And S104, determining a target time delay parameter according to the plurality of candidate time delay parameters, and calibrating the double data rate processor according to the target time delay parameter.
Specifically, when it is detected that none of the plurality of candidate delay parameters is illegal data, a target delay parameter (including a target read delay parameter and a target write delay parameter) is calculated according to the plurality of candidate delay parameters, and the target delay parameter is written into the driving software, so that the double data rate processor is calibrated.
By dynamically determining the better read time delay parameter and write time delay parameter, the impedance control precision of the PCB is improved, the production cost of the PCB is reduced, and therefore the data processing precision and efficiency of the DDR processor are improved.
In one embodiment, the determining a time delay adjustment rectangular area according to the first adjustment range and the second adjustment range includes:
determining the maximum value of the read time delay parameter and the minimum value of the read time delay parameter in the first adjusting range;
determining the maximum value and the minimum value of the write delay parameter in the second adjusting range;
and constructing a time delay adjustment rectangular area according to the read time delay parameter maximum value, the read time delay parameter minimum value, the write time delay parameter maximum value and the write time delay parameter minimum value.
Specifically, a maximum value of a read delay parameter and a minimum value of the read delay parameter are determined by a first adjustment range of the read delay parameter in the delay controller, a maximum value of a write delay parameter and a minimum value of the write delay parameter are determined by the first adjustment range of the write delay parameter in the delay controller, and a row of data is constructed according to the first adjustment range and the second adjustment range, wherein the row of data comprises the maximum value of the read delay parameter from the minimum value of the read delay parameter, and the column of data comprises a delay adjustment rectangular region from the minimum value of the write delay parameter to the maximum value of the write delay parameter.
In one embodiment, before the accessing the double data rate processor according to the rectangular region with the adjusted time delay and receiving the data result returned by the double data rate processor, the method includes:
selecting a target region in the double data rate processor;
and writing preset data into the target area and emptying a cache.
Specifically, the DQ signal and DQS signal are independent of address, so a target region in the DDR processor can be pre-selected that can meet the requirement for multiple reads and writes. For example, it is preset that at least 100 read/write operations need to be satisfied, and the target area should be 100 × 4-400 bytes corresponding to a 32-bit system.
Specifically, a characteristic value is selected in advance, the value is written into each position of a target area as preset data, and cache of a Central Processing Unit (CPU) is cleared. The preset data can be specifically set according to actual requirements, and in order to ensure smooth read-write operation, binary values of 0 and 1 are set and selected, such as 0x5a5a5a5 a.
As shown in fig. 2, in an embodiment, the step S103 of accessing the double data rate processor according to the rectangular delay adjustment region, receiving a data result returned by the double data rate processor, and selecting a plurality of candidate delay parameters meeting a preset condition according to the data result includes:
s1031, traversing each pair of time delay parameters in the time delay adjustment rectangular region according to a preset sequence, and inputting each pair of time delay parameters into the double data rate processor; each pair of time delay parameters comprises a reading time delay parameter and a writing time delay parameter;
s1032, accessing the double data rate processor and receiving a data result returned by the double data rate processor;
s1033, selecting alternative time delay parameters according to the data result until a plurality of alternative time delay parameters meeting preset conditions are selected; the plurality of candidate latency parameters includes at least two read candidate latency parameters and at least two write candidate latency parameters.
Specifically, the maximum value of the read delay parameter, the minimum value of the read delay parameter, the maximum value of the write delay parameter, and the minimum value of the write delay parameter in the delay adjustment rectangular region are initialized in advance, and the values are uniformly converted into illegal data (for example, -1). And traversing each pair of delay parameters (including a read delay parameter and a write delay parameter) in the delay adjustment rectangular area through a preset sequence, writing the read delay parameter and the write delay parameter into the double-data-rate processor, accessing the double-data-rate processor, and receiving a data result returned by the double-data-rate processor. Comparing the data result with preset data, and selecting corresponding alternative time delay parameters according to the comparison result until a plurality of alternative time delay parameters meeting preset conditions are selected; the plurality of candidate latency parameters includes at least two read candidate latency parameters and at least two write candidate latency parameters.
The preset sequence can be specifically set according to actual conditions. In order to ensure the reading and writing efficiency, the preset sequence is preset from small to large. For example, the read delay parameter minimum value is selected, the read delay parameter minimum value is written into the DDR processor, the write delay parameters are traversed from small to large, each write timing signal is sequentially written into the DDR processor, and the data results returned by the DDR processor are sequentially received. When the comparison result of all the data results and the preset data is detected not to meet the screening condition, selecting a second value of the read delay parameter (namely a read delay parameter value which is greater than the minimum value of the read delay parameter and smaller than other read delay parameters), writing the second value of the read delay parameter into the DDR processor, traversing the write delay parameters from small to large, sequentially writing each write timing signal into the DDR processor, and sequentially receiving the data results returned by the DDR processor until a plurality of alternative delay parameters meeting the preset condition are selected.
The reading time delay signal and the writing time delay signal are bound to construct a corresponding two-dimensional rectangular area, a better solution is found through an algorithm for finding a central point, dynamic calibration of the reading and writing signals is achieved, and calibration precision and efficiency are improved.
In an embodiment, the selecting the alternative delay parameter according to the data result until a plurality of alternative delay parameters satisfying a preset condition are selected includes:
comparing the data result with the preset data;
when the data result is detected to be consistent with the preset data, determining a read time delay parameter corresponding to the data result as a read alternative time delay parameter, and determining a write time delay parameter corresponding to the data result as a write alternative time delay parameter;
and until all the time delay parameters are detected, or the difference value of the write alternative time delay parameters is less than or equal to a preset threshold value.
Specifically, whether a data result returned by the DDR processor is consistent with preset data or not is compared, when the data result returned by the DDR processor is detected to be consistent with the preset data written in advance, a read time delay parameter which corresponds to the current data result and is input into the DDR processor is determined to be a read alternative time delay parameter, a write time delay parameter which corresponds to the current data result and is input into the DDR processor is determined to be a write alternative time delay parameter until all time delay parameters are detected, or a difference value of the write alternative time delay parameters is detected to be smaller than or equal to a preset threshold value. Firstly, determining the maximum value of a plurality of write candidate delay parameters as a first maximum candidate delay parameter, determining the minimum value of the plurality of write candidate delay parameters as a first minimum candidate delay parameter, wherein the difference value of the write candidate delay parameters is the difference value of the first maximum candidate delay parameter and the first minimum candidate delay parameter. The preset threshold may be specifically set according to actual requirements, for example, the preset threshold is set to 2.
For example, the preset data is 0x5c5c5a5a, when the read delay parameter minimum value and the write delay parameter maximum value are input, the obtained data result is 0x5c5c5a5a, the read delay parameter minimum value is correspondingly determined as the read candidate delay parameter, and the write delay parameter maximum value is determined as the write candidate delay parameter.
As shown in fig. 3, in an embodiment, the step S104 of determining a target latency parameter according to a plurality of the candidate latency parameters and calibrating the double data rate processor according to the target latency parameter includes:
s1041, detecting whether the alternative time delay parameter is illegal data;
s1042, when detecting that each alternative time delay parameter is not illegal data, calculating according to the write alternative time delay parameter and the read alternative time delay parameter to obtain a target time delay parameter;
and S1043, calibrating the double data rate processor according to the target time delay parameter.
Specifically, when searching for a better target delay parameter (including a target read delay parameter and a target write delay parameter) in the constructed delay adjustment rectangular region, it may be determined that the better target delay parameter is a certain point (i.e., a certain pair of delay parameters) in the delay adjustment rectangular region, and the delay adjustment rectangular region is centered on the point, and data results corresponding to all points in the region constructed by the candidate delay parameters are consistent with the preset data. Therefore, the candidate delay parameter cannot be a maximum read delay parameter, a minimum read delay parameter, a maximum write delay parameter, or a minimum write delay parameter (because a point where a corresponding data result is consistent with preset data does exist in an area formed by the four values). That is, it is necessary to determine whether the alternative delay parameter is an illegal value, if it is detected that each alternative delay parameter is not illegal data, a target delay parameter is calculated according to the write alternative delay parameter and the read alternative delay parameter, and the double data rate processor is calibrated according to the target delay parameter.
The method for determining the target time delay parameter comprises the following steps: firstly, determining a first maximum alternative time delay parameter and a first minimum alternative time delay parameter in a plurality of write alternative time delay parameters; then, determining a second maximum alternative delay parameter (namely, a maximum value in the read alternative delay parameters) and a second minimum alternative delay parameter (namely, a minimum value in the read alternative delay parameters) in the read alternative delay parameters; finally, the corresponding target write delay parameters are: (first maximum candidate delay parameter + first minimum candidate delay parameter)/2; the target read delay parameters are: (second maximum candidate delay parameter + second minimum candidate delay parameter)/2.
In an embodiment, after detecting whether the candidate delay parameter is illegal data, the method further includes:
and when any optional time delay parameter is detected to be illegal data, generating and displaying calibration failure information.
Specifically, when any one of the candidate delay parameters is detected to be illegal data (such as-1), it may be determined that at least one point (or a certain pair of delay parameters) where the data result is inconsistent with the preset data exists in the region constructed by the candidate delay parameter and the other candidate delay parameters, and calibration failure information is generated and displayed.
In one embodiment, the calibration failure information may be sent to the target terminal device. The target terminal device includes, but is not limited to, a mobile terminal (such as a mobile phone, a notebook computer, etc.) of the manager.
In this embodiment, the double data rate processor is accessed through a time delay adjustment rectangular region constructed by the read-write time delay parameter, a target time delay parameter is dynamically selected based on a received data result, automatic calibration of the read-write time delay signal is realized, the production cost of the PCB is reduced, and meanwhile, the impedance control precision and the system stability of the PCB are improved, so that the data processing efficiency of the DDR processor is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Fig. 4 shows a block diagram of an automatic calibration apparatus for a time delay signal according to an embodiment of the present application, which corresponds to the automatic calibration method for a time delay signal according to the foregoing embodiment, and only shows portions related to the embodiment of the present application for convenience of description.
Referring to fig. 4, the apparatus 100 for automatically calibrating a time delay signal includes:
a data determining module 101, configured to determine a first adjustment range of the read delay parameter and a second adjustment range of the write delay parameter;
a matrix determining module 102, configured to determine a time delay adjustment rectangular area according to the first adjustment range and the second adjustment range;
a parameter selection module 103, configured to access a double data rate processor according to the time delay adjustment rectangular region, receive a data result returned by the double data rate processor, and select multiple candidate time delay parameters meeting a preset condition according to the data result;
a parameter calibration module 104, configured to determine a target delay parameter according to the multiple candidate delay parameters, and calibrate the double data rate processor according to the target delay parameter.
In one embodiment, the delay adjustment rectangular area determining module includes:
a first parameter determining unit, configured to determine a maximum value of the read delay parameter and a minimum value of the read delay parameter in the first adjustment range;
a second parameter determining unit, configured to determine a maximum value and a minimum value of the write delay parameter in the second adjustment range;
and the matrix determining unit is used for constructing a time delay adjusting rectangular area according to the read time delay parameter maximum value, the read time delay parameter minimum value, the write time delay parameter maximum value and the write time delay parameter minimum value.
In one embodiment, the apparatus further comprises:
a region selection module for selecting a target region in the double data rate processor;
and the data writing module is used for writing preset data into the target area and emptying the cache.
In one embodiment, the parameter selecting module includes:
the traversal unit is used for traversing each pair of time delay parameters in the time delay adjustment rectangular area according to a preset sequence and inputting each pair of time delay parameters into the double data rate processor; each pair of time delay parameters comprises a reading time delay parameter and a writing time delay parameter;
the access unit is used for accessing the double data rate processor and receiving a data result returned by the double data rate processor;
the data selection unit is used for selecting alternative time delay parameters according to the data result until a plurality of alternative time delay parameters meeting preset conditions are selected; the plurality of candidate latency parameters includes at least two read candidate latency parameters and at least two write candidate latency parameters.
In one embodiment, the data selecting unit includes:
the comparison subunit is used for comparing the data result with the preset data;
a parameter determining subunit, configured to determine, when it is detected that the data result is consistent with the preset data, a read delay parameter corresponding to the data result as a read candidate delay parameter, and a write delay parameter corresponding to the data result as a write candidate delay parameter;
and the parameter detection subunit is used for detecting all the time delay parameters or the difference value of the write candidate time delay parameters is less than or equal to a preset threshold value.
In one embodiment, the parameter calibration module includes:
a parameter detection unit, configured to detect whether the candidate delay parameter is illegal data;
the calculating unit is used for calculating to obtain a target time delay parameter according to the write alternative time delay parameter and the read alternative time delay parameter when detecting that each alternative time delay parameter is not illegal data;
and the calibration unit is used for calibrating the double data rate processor according to the target time delay parameter.
In one embodiment, the parameter calibration module further includes:
and the information generating unit is used for generating and displaying calibration failure information when any one of the alternative time delay parameters is detected to be illegal data.
In this embodiment, the double data rate processor is accessed through a time delay adjustment rectangular region constructed by the read-write time delay parameter, a target time delay parameter is dynamically selected based on a received data result, automatic calibration of the read-write time delay signal is realized, the production cost of the PCB is reduced, and meanwhile, the impedance control precision and the system stability of the PCB are improved, so that the data processing efficiency of the DDR processor is improved.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
Fig. 5 is a schematic structural diagram of the terminal device provided in this embodiment. As shown in fig. 5, the terminal device 5 of this embodiment includes: at least one processor 50 (only one is shown in fig. 5), a memory 51, and a computer program 52 stored in the memory 51 and executable on the at least one processor 50, wherein the processor 50 executes the computer program 52 to implement the steps in any of the above embodiments of the method for automatically calibrating a time-delayed signal.
The terminal device 5 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The terminal device may include, but is not limited to, a processor 50, a memory 51. Those skilled in the art will appreciate that fig. 5 is only an example of the terminal device 5, and does not constitute a limitation to the terminal device 5, and may include more or less components than those shown, or combine some components, or different components, such as an input-output device, a network access device, and the like.
The Processor 50 may be a Central Processing Unit (CPU), and the Processor 50 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 51 may in some embodiments be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5. In other embodiments, the memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital Card (SD), a Flash memory Card (Flash Card), and the like, which are provided on the terminal device 5. Further, the memory 51 may also include both an internal storage unit and an external storage device of the terminal device 5. The memory 51 is used for storing an operating system, an application program, a BootLoader (BootLoader), data, and other programs, such as program codes of the computer program. The memory 51 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
An embodiment of the present application further provides a terminal device, where the terminal device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, the processor implementing the steps of any of the various method embodiments described above when executing the computer program.
The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.
The embodiments of the present application provide a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the above method embodiments when executed.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/terminal apparatus, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other ways. For example, the above-described apparatus/network device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for automatically calibrating a time delay signal, comprising:
determining a first adjusting range of the reading time delay parameter and a second adjusting range of the writing time delay parameter;
determining a time delay adjustment rectangular area according to the first adjustment range and the second adjustment range;
accessing a double data rate processor according to the time delay adjusting rectangular region, receiving a data result returned by the double data rate processor, and selecting a plurality of alternative time delay parameters meeting preset conditions according to the data result;
and determining a target time delay parameter according to the plurality of alternative time delay parameters, and calibrating the double data rate processor according to the target time delay parameter.
2. The method for automatically calibrating a time delay signal according to claim 1, wherein said determining a time delay adjustment rectangular area according to the first adjustment range and the second adjustment range comprises:
determining the maximum value of the read time delay parameter and the minimum value of the read time delay parameter in the first adjusting range;
determining the maximum value and the minimum value of the write delay parameter in the second adjusting range;
and constructing a time delay adjustment rectangular area according to the read time delay parameter maximum value, the read time delay parameter minimum value, the write time delay parameter maximum value and the write time delay parameter minimum value.
3. The method for automatically calibrating a delay signal according to claim 1, wherein before accessing a double data rate processor according to the delay adjustment rectangular region and receiving a data result returned by the double data rate processor, the method comprises:
selecting a target region in the double data rate processor;
and writing preset data into the target area and emptying a cache.
4. The method of claim 1, wherein the accessing a double data rate processor according to the rectangular delay adjustment region, receiving a data result returned by the double data rate processor, and selecting a plurality of candidate delay parameters meeting a preset condition according to the data result comprises:
traversing each pair of time delay parameters in the time delay adjustment rectangular area according to a preset sequence, and inputting each pair of time delay parameters into the double data rate processor; each pair of time delay parameters comprises a reading time delay parameter and a writing time delay parameter;
accessing the double data rate processor and receiving a data result returned by the double data rate processor;
selecting alternative time delay parameters according to the data result until a plurality of alternative time delay parameters meeting preset conditions are selected; the plurality of candidate latency parameters includes at least two read candidate latency parameters and at least two write candidate latency parameters.
5. The method of claim 4, wherein the selecting the candidate delay parameters according to the data result until a plurality of candidate delay parameters satisfying a predetermined condition are selected comprises:
comparing the data result with the preset data;
when the data result is detected to be consistent with the preset data, determining a read time delay parameter corresponding to the data result as a read alternative time delay parameter, and determining a write time delay parameter corresponding to the data result as a write alternative time delay parameter;
and until all the time delay parameters are detected, or the difference value of the write alternative time delay parameters is less than or equal to a preset threshold value.
6. The method of automatically calibrating a delay signal according to claim 1, wherein said determining a target delay parameter based on a plurality of said candidate delay parameters, and calibrating said double data rate processor based on said target delay parameter comprises:
detecting whether the alternative time delay parameter is illegal data or not;
when detecting that each alternative time delay parameter is not illegal data, calculating according to the write alternative time delay parameter and the read alternative time delay parameter to obtain a target time delay parameter;
and calibrating the double data rate processor according to the target time delay parameter.
7. The method for automatically calibrating a time-delayed signal according to claim 6, wherein said detecting whether said candidate time-delayed parameter is illegal data further comprises:
and when any optional time delay parameter is detected to be illegal data, generating and displaying calibration failure information.
8. An apparatus for automatic calibration of a time delayed signal, comprising:
the data determining module is used for determining a first adjusting range of the reading delay parameter and a second adjusting range of the writing delay parameter;
the matrix determining module is used for determining a time delay adjusting rectangular area according to the first adjusting range and the second adjusting range;
the parameter selection module is used for accessing the double data rate processor according to the time delay adjustment rectangular region, receiving a data result returned by the double data rate processor, and selecting a plurality of alternative time delay parameters meeting preset conditions according to the data result;
and the parameter calibration module is used for determining a target time delay parameter according to the plurality of candidate time delay parameters and calibrating the double data rate processor according to the target time delay parameter.
9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
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