CN114550809A - Test method, device, computer equipment and storage medium for multiple memory cards - Google Patents

Abstract

The application belongs to the technical field of storage, and relates to a method and a device for testing multiple memory cards, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring a write-in command for writing data and the number of the multi-memory card into the multi-memory card, wherein the write-in command carries the data and the number; analyzing the write-in command, obtaining the data and the number, and writing the data into the multi-memory card according to the number; and reading the data from every two multi-memory cards with different numbers, putting the read data into a comparison circuit for XOR operation, and judging whether the multi-memory cards are normal or not according to the XOR operation result. By the adoption of the method, the plurality of storage cards are numbered, data are written into the plurality of storage cards simultaneously, manpower is not needed, testing of the storage cards can be automatically executed, cost is saved, testing efficiency can be improved, testing is reliable and easy to achieve, and the method can be universally applied to testing of the storage cards.

Description

Test method, device, computer equipment and storage medium for multiple memory cards

technical field

The present application relates to the field of storage technology, and in particular, to a testing method, device, computer equipment and storage medium for multiple memory cards.

Background technique

With the development of information processing technology, the demand for storage devices has increased significantly. Small storage devices, such as memory cards, are widely used due to the advantages of portability, high data storage capacity, and easy access. Due to the increasing demand for memory cards, the importance of the memory card testing process is also relatively increased before the mass production of memory cards to further ensure the performance and compatibility of memory cards. Therefore, low-cost and high-performance memory card testing has become an important issue for system manufacturers and designers.

Traditionally, when testing memory cards, testers are required to manually and step-by-step process the tests to ensure the performance of the memory cards. For example, testing is performed by the tester manually inserting or removing each memory card. In the testing process, various testing devices are required to ensure the performance and compatibility of the memory card. It can be seen that the traditional memory card testing process is not only time-consuming but also expensive. The testing principle of the memory card in the prior art is to write the same data into multiple memory cards, then read the data, and verify the consistency between the read data and the written data, so as to test the memory card. operation.

This test operation has several characteristics: First, the amount of data is relatively large. For example, when the storage device to be tested is a memory card, if the capacity of the memory card is 256GB, the test data is 256GB; if the storage device to be tested is a hard disk If the capacity of the hard disk is 2T, then the test data must be 2T; second, the data to be tested is written from the host (computer) to multiple storage devices to be tested. Write--read--data comparison; re-write--erase block--read--data comparison. Generally speaking, this kind of test process is repeated several times to test the stability of the stored data of the storage device. It can be seen that the testing process is very long and inefficient.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present application is to provide a multi-memory card testing method, device, computer equipment and storage medium, so as to solve the problems of long and low efficiency in the multi-memory card testing process in the prior art.

In order to solve the above-mentioned technical problems, the present application provides a method for testing multiple memory cards, which adopts the technical solution described below, including the following steps:

Obtain a write command for writing data and the number of the multi-memory card into the multi-memory card, and the write command includes the data and the number;

Parse the write command, obtain the data and the serial number, and write the data into the multiple memory cards according to the serial number;

Read the data from every two multi-memory cards with different numbers, store the read data in the comparison circuit for XOR operation, and judge the number of the two different numbers according to the result of the XOR operation. Is the memory card normal.

Further, before the described acquisition writes the data and the number of the multi-memory card into the write command of the multi-memory card, the write command also includes before the step of carrying the data and the number:

Sets the rules for writing commands.

Further, the step of parsing the write command, obtaining the data and the serial number, and writing the data into the multi-memory card according to the serial number specifically includes:

Parse the write command to obtain the data and the number;

Cache the obtained data in the cache area;

Write the data in the buffer area to the multi-memory card according to the stated number.

Further, the described data is read from the multiple memory cards of every two different numbers, the read data is put into the comparison circuit to carry out XOR operation, and whether the multiple storage cards are normal according to the XOR operation result is judged. The steps specifically include:

According to the number of the multiple memory cards, group them in pairs;

Read the data from every two multi-memory cards with different numbers, and put the read data into the comparison circuit for XOR operation;

If the result of the XOR operation is 0, it is judged that the two multi-memory cards with different numbers are normal; if the result of the XOR operation is 1, it is judged that one of the two multi-memory cards with different numbers is abnormal;

Identify the abnormal multi-memory card group, and then perform XOR operation on each multi-memory card in the abnormal multi-memory card group with the detected normal multi-memory card until all the abnormal multi-memory cards are detected. Normal and abnormal conditions of multiple memory cards.

Further, the rules for setting the write command include:

The first byte of the set write command represents the number of the multiple memory card.

Further, read the data from the multiple memory cards of every two different numbers, put the read data into the comparison circuit and carry out XOR operation, and judge whether the multiple memory cards are based on the XOR operation result. The normal steps are followed by:

An abnormal multiple memory card number is displayed.

In order to solve the above technical problems, the present application also provides a multi-memory card testing device, which adopts the following technical solutions, including:

an acquisition module, for acquiring a write command for writing data and the number of the multi-memory card into the multi-memory card, and the write command carries the data and the number;

a writing module for parsing the writing command, obtaining the data and the serial number, and writing the data into the multi-memory card according to the serial number;

The discriminating module is used to read the data from every two multi-memory cards with different numbers, put the read data into the comparison circuit for XOR operation, and judge whether the multi-memory card is normal according to the XOR operation result .

Further, the writing module includes:

a parsing module for parsing the write command to obtain the data and the number;

a cache module, used to cache the data in the cache area SRAM;

The output module is used for writing the data into the multiple memory cards according to the number from the buffer area SRAM.

In order to solve the above technical problems, the present application also provides a computer device, which adopts the technical solution described below, including a memory and a processor, where computer-readable instructions are stored in the memory, and the processor executes the computer-readable instructions. The steps of implementing the above-mentioned multi-memory card testing method when reading the instruction.

In order to solve the above technical problems, the present application also provides a computer-readable storage medium, which adopts the following technical solution, where computer-readable instructions are stored on the computer-readable storage medium, and the computer-readable instructions are processed The steps of implementing the above-mentioned multi-memory card testing method when the device is executed.

Compared with the prior art, the present application mainly has the following beneficial effects: by numbering the multi-memory cards, data is simultaneously written into the plurality of multi-memory cards, without relying on manpower, the test of the memory cards can be automatically performed, the cost is saved, and the Improve the test efficiency, the test is reliable and easy to implement, and can be widely used in the test of memory cards.

Description of drawings

In order to illustrate the solutions in the present application more clearly, the following will briefly introduce the accompanying drawings used in the description of the embodiments of the present application. For those of ordinary skill, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is an exemplary system architecture diagram to which the present application can be applied;

2 is a flowchart of an embodiment of the testing method for multiple memory cards of the present application;

Fig. 3 is a test schematic diagram of multiple memory cards in the prior art;

Fig. 4 is the test data transmission sequence diagram of multiple memory cards in the prior art;

Fig. 5 is the test data transmission sequence diagram of the multi-memory card of the present application;

6 is a schematic diagram of an embodiment in which data of the present application is simultaneously written to multiple memory cards;

7 is a schematic diagram of another embodiment in which data of the present application is simultaneously written to multiple memory cards;

Fig. 8 is the exclusive OR circuit diagram of eight bits of the present application;

9 is a logic circuit diagram of the present application;

10 is a schematic structural diagram of an embodiment of the multi-memory card testing device of the present application;

11 is a schematic structural diagram of a specific implementation manner of the writing module shown in FIG. 10;

FIG. 12 is a schematic structural diagram of an embodiment of a computer device of the present application.

In the figure, A-NOR gate, B-NAND gate, C-NOT gate.

Detailed ways

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of this application; the terms used herein in the specification of the application are for the purpose of describing specific embodiments only It is not intended to limit the application; the terms "comprising" and "having" and any variations thereof in the description and claims of this application and the above description of the drawings are intended to cover non-exclusive inclusion. The terms "first", "second" and the like in the description and claims of the present application or the above drawings are used to distinguish different objects, rather than to describe a specific order.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings.

As shown in FIG. 1 , the system architecture 100 may include a first terminal device 101 , a second terminal device 102 , a third terminal device 103 , a network 104 and a server 105 . The network 104 is a medium for providing a communication link between the first terminal device 101 , the second terminal device 102 , the third terminal device 103 and the server 105 . The network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, among others.

The user can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 through the network 104 to receive or send messages and the like. Various communication client applications, such as web browser applications, shopping applications, search applications, instant messaging tools, email clients, Social platform software, etc.

The first terminal device 101, the second terminal device 102, and the third terminal device 103 may be various electronic devices with a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, e-book readers, and MP3 players (Moving Picture E multi-memory card test pertsGroup AudioLayer III, Moving Picture Expert compression standard audio layer 3), MP4 (Moving PictureE multi-memory card test perts Group Audio Layer IV, Moving Picture Expert compression standard audio layer 4) player, Laptops and desktops, etc.

The server 105 may be a server that provides various services, such as a background server that provides support for the pages displayed on the first terminal device 101 , the second terminal device 102 , and the third terminal device 103 .

It should be noted that the multi-memory card testing method provided by the embodiments of the present application is generally performed by a server/terminal device, and accordingly, a multi-memory card testing apparatus is generally set in the server/terminal device.

It should be understood that the numbers of terminal devices, networks and servers in FIG. 1 are merely illustrative. There can be any number of terminal devices, networks and servers according to implementation needs.

Example 1

Continuing to refer to FIG. 2 , a flow chart of an embodiment of the multi-memory card testing method of the present application is shown. The method for testing multiple memory cards includes the following steps:

Step S201: Obtain a write command for writing data and the serial number of the multi-memory card into the multi-memory card, where the write command includes the data and the serial number.

FIG. 3 is a test schematic diagram of multiple memory cards in the prior art. As shown in FIG. 3 , in the testing of multiple memory cards in the prior art, a test system is usually composed of a terminal, a USB hub and multiple memory cards. One end of the USB hub is a USB interface, and the other end can be multiple interfaces. Multiple interfaces can be the same or different. The multiple interfaces may include a SATA interface, a USB interface, a Type-C interface, and the like. Connect multiple memory cards through SATA interface, USB interface, Type-C and other interfaces. During the test, the tester needs to manually insert or remove each memory card such as the multi-memory card 1, the multi-memory card 2, the multi-memory card 3, and the multi-memory card 4 for testing. It can be seen that the test is time-consuming and labor-intensive.

FIG. 4 is a sequence diagram of test data transmission of multiple memory cards in the prior art. As shown in Figure 4, the same data is written from the terminal to multiple memory cards, and the data is composed of W1, W2, W3, and W4; at T1 time, data W1 is written into card 1, and at T2 time, data W2 is written into In card 1, data W3 is written into card 1 at time T3, and data W4 is written into card 1 at time T4. It can be seen that the data storage is carried out serially.

In some optional implementations of this embodiment, in step S201, a write command for writing the data and the serial number of the multi-memory card into the multi-memory card is obtained, and the write command includes the data and the serial number Before the step of , the above-mentioned electronic device may further perform the following step: set a rule for writing a command.

For example, the rules for setting the write command include: setting the first byte of the write command to represent the serial number of the multiple memory cards. Of course, the number of bytes representing the number of the multi-memory card can also be defined according to the actual needs and the number of multi-memory cards to be tested. Here, there is no restriction on the number of bytes of the multi-memory card number.

In this application, the multi-memory cards are numbered, and the numbering information is written into the multi-memory cards, which facilitates the tracking test.

In this embodiment, the electronic device (for example, the server/terminal device shown in FIG. 1 ) on which the multi-memory card testing method runs can receive the multi-memory card testing request through wired connection or wireless connection. It should be pointed out that the above wireless connection methods may include but are not limited to 3G/4G/5G connection, WiFi connection, Bluetooth connection, WiMA multi-memory card test connection, Zigbee connection, UWB (ultra wideband) connection, and other known or wireless connection methods developed in the future.

Step S202, parse the write command, obtain the data and the serial number, and write the data into the multi-memory card according to the serial number.

In some optional implementations of this embodiment, the step of parsing the write command, obtaining the data and the serial number, and writing the data into the multi-memory card according to the serial number specifically includes:

Parse the write command to obtain the data and the number;

Cache the obtained data in the cache area;

Write the data in the buffer area to the multi-memory card according to the stated number.

FIG. 5 is a test data transmission sequence diagram of the multi-memory card of the present application. As shown in Figure 5, the data W1, W2, W3 and W4 can be written into the memory card 1 simultaneously within a T1 time, and the control circuit (master) can also write the data W1, W2, W3 within the T1 time and W4 are written to memory card 2 or/and memory card 3 or/and memory card 4. The numbers of memory card 1, memory card 2, memory card 3, and memory card 4 are obtained by parsing the write command. Before writing the data W1, W2, W3 and W4 to the memory card 2 or/and the memory card 3 or/and the memory card 4 within the time T1, the data W1, W2, W3 and W4 can be cached in the buffer area first . Set the data output buffer to temporarily store the data during writing and reserve a certain space in the memory area. That is, the storage space of the main memory is used to temporarily store the information output from the disk. The purpose is to alleviate the contradiction between the speed mismatch between the CPU and the I/O device. Reduce the frequency of interrupts to the CPU and relax the restrictions on the response time of CPU interrupts. Improve parallelism between CPU and I/O devices. It can be seen that with this embodiment, data storage is performed in parallel, which can save time.

FIG. 6 is a schematic diagram of an embodiment of the present application for simultaneously writing data to multiple memory cards. As shown in FIG. 6 , the terminal issues an instruction to write data into each memory card, the CPU executes the instruction, and the CPU controls the terminal (host) data to be cached in the cache area SRAM first. The main control refers to the main control of the test device. The main control is soldered to a PCB. One end of the PCB has an interface for connecting to the host, and the other end has a card slot for inserting multiple memory cards to connect the cards to the test board.

Specifically, when starting the test, the CPU in the main control first writes the data W1, W2, W3 and W4 of the host into the buffer, and then writes the data of W1, W2, W3 and W4 in the buffer to each card , so as to realize the simultaneous writing of data to each card.

Step S203, read the data from each two different numbered multi-memory cards, store the read data in the comparison circuit and perform an XOR operation, and judge the two different according to the result of the XOR operation. Whether the numbered multi-memory card is normal.

In some optional implementations of this embodiment, the data is read from every two multi-memory cards with different numbers, and the read data is put into a comparison circuit to perform an exclusive OR operation, according to The steps of judging whether the multi-memory card is normal based on the result of the exclusive OR operation specifically include:

According to the number of the multiple memory cards, group them in pairs;

Read the data from every two multi-memory cards with different numbers, and put the read data into the comparison circuit for XOR operation;

If the result of the XOR operation is 0, it is judged that the two multi-memory cards with different numbers are normal; if the result of the XOR operation is 1, it is judged that one of the two multi-memory cards with different numbers is abnormal;

Identify the abnormal multi-memory card group, and then perform XOR operation on each multi-memory card in the abnormal multi-memory card group with the detected normal multi-memory card until all the abnormal multi-memory cards are detected. Normal and abnormal conditions of multiple memory cards.

The embodiment of the present application further requires protection to simultaneously read the data in each card, so as to judge whether the data can be read and accurately read (compared with the data written by the host, the data is correct). Testing of the performance of individual cards is accomplished based on the fact that the data can be read and accurately read.

FIG. 7 is a schematic diagram of another embodiment of the present application for simultaneously writing data to multiple memory cards. As shown in FIG. 7 , based on this, the master control in the embodiment of the present application further includes a comparison circuit, more specifically, an exclusive OR circuit. Since the same data is written to each card, the CPU in the main control controls to read data from every two cards, and puts the read and divided data into the comparison circuit for XOR operation. For the same data in the two cards, the data expression is binary "0", "1", and the XOR circuit is used to perform XOR operation on these data. If the two cards are OK, then the two cards are OK. The data read out from each card is XORed, and the result of XOR operation is "0"; if one of the two cards is NG (NotGood, Failed, that is, failed), then the result of XOR operation is is "1".

Specifically, since the data is read from the memory card, the data is read out byte by byte. Therefore, the data comparison, that is, the XOR operation, is a byte-by-byte comparison, and the data of the memory card is read and written. The principle is to read and write byte by byte.

Further, since the data is composed of multiple bytes, the comparison circuit, or the XOR circuit is actually a byte XOR accumulation circuit, the data is continuous, and the XOR operation is performed on a byte by byte basis. , which is actually an additive logic. The accumulated hardware can be a register.

Specifically, as long as the result of the XOR operation of one byte is "1", it means that the test result of one card is NG, and then the test result of the memory card can be known.

Exemplarily, there are 4 cards in Fig. 7, the data in card 1 and card 2 are XORed, the data in card 3 and card 4 are XORed, if the data in card 1 and card 2 are XORed The result of the operation is "0", and the result of the XOR operation on the data in card 3 and card 4 is "1", then it means that at least one card in card 3 and card 4 is NG. Perform XOR operation on the data in card 1 and card 4; or perform XOR operation on the data in card 2 and card 3 or perform XOR operation on the data in card 2 and card 4. In this way, the NG in all cards can be tested, or all cards can be tested.

The XOR of A and B is equivalent to the XOR of A and B, i.e.

The deformation yields the above-mentioned logical algebra.

The corresponding logic circuit is composed of two NOR gates and one AND gate. For 8-bit binary comparison, 8 groups of this logic circuit can be connected in series.

再经过与或非门得到A和B异或输出。Corresponding to a single cmos XOR gate circuit, it consists of a first-level NOR gate and a first-level NAND gate. For inputs A and B, first pass through the NOR gate to get

And then through the NOR gate to get A and B XOR output.

Truth table:

A B NOR gate output NAND gate output 0 0 1 0 0 1 0 1 1 0 0 1 1 1 0 0

The process of testing the memory card is as follows: the external data is input to the BULK FIFO of the SRAM through multiple interfaces such as the usb interface for processing. According to the data data of the SRAM1235, 2k or other is required at a time, that is, part of the input, and then the FIFO data is input according to the SRAM1235. The read and write requirements (SRAM needs to be passed to the XOR circuit data, w/r) are encoded and decoded, and the operation is completed and then returned to the SRAM, and re-stored to the USB or other operations as needed. Each write data will overwrite the previous data in the SRAM FIFO.

Data comparison example:

1001 1100 0011 0001 0101 1110 1011 0111 (32-bit binary data of the mother card);

9 c 3 1 5 e b 7 (32-bit hexadecimal);

1001 1100 0011 0011 0101 1100 1011 0111 (daughter card 32-bit binary data);

9 c3 35 c b 7 (hexadecimal);

It can be seen that the 4th and 6th 8bits have errors.

XOR comparison result:

0000 0000 0000 0010 0000 0010 0000 0000 (binary);

0 0 0 2 0 2 0 0 (hexadecimal).

FIG. 8 is an 8-bit XOR circuit diagram of the present application. As shown in Figure 8, it mainly includes two devices, NMOS and PMOS. The source S of PMOS1 is connected to the drain D of PMOS2, the source of PMOS2 is connected to the gate G of PMOS5, the gate G of NMOS3, the drain D of NMOS2, and the drain D of NMOS1 respectively, PMOS1, PMOS2, NMOS1, NMOS2 Form the NOR gate A. PMOS3, PMOS4, NMOS4, NMOS5 constitute NOR gate B. The drain D of PMOS3 is connected to the drain D of PMOS4, the gate of PMOS4 is connected to the gate of NMOS4, the source of NMOS4 is connected to the drain of NMOS5, the drain of NMOS4 is respectively connected to the source of PMOS5 and the drain of NMOS3 connect. PMOS5 and NMOS3 constitute NOT gate C. The source of PMOS5 is connected to the drain of NMOS3. For NMOS, the source and drain are turned on when G is very high level (1). On the contrary, in PMOS, the gate is low and the source and drain are turned on. The working principle is: for the input a and b of the NOR gate, only when a and b are 1 (high level) at the same time, the output is high level. For the output a and b of the NAND gate, only when a and b are 1 at the same time, the output is 0 (low level). The NOT gate negates the input.

A与B或非，输出值取反(非门)再与A和B的与非门进行与(对应串联)。NAND gate NAND gate series corresponding logic algebra:

A and B or not, the output value is inverted (not gate) and then with the NAND gate of A and B (corresponding in series).

A与B相与，输出值与A与B的或非值再进行或非操作。FIG. 9 is a logic circuit diagram of the present application. As shown in Figure 9, referring to the algebraic formula

A and B are combined, and the output value is NOR-operated with the NOR value of A and B.

In some optional implementations of this embodiment, in step S203, the data is read from every two multi-memory cards with different numbers, and the read data is stored in a comparison circuit for XOR operation, After judging whether the two multi-memory cards with different numbers are normal according to the result of the exclusive OR operation, the step of: displaying the abnormal multi-memory card numbers. By setting the display interface, the abnormal multi-memory card numbers are displayed, which is convenient for users to know which multi-memory cards need to be re-tested or repaired, etc., and it is convenient for users to follow up the quality of abnormal multi-memory cards.

By numbering multiple memory cards, data can be written to multiple multiple memory cards at the same time, without relying on manpower, the test of memory cards can be automated, cost saving and test efficiency can be improved. The test is reliable and easy to implement, and can be widely used in storage card testing.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through computer-readable instructions, and the computer-readable instructions can be stored in a computer-readable storage medium. , when the program is executed, it may include the processes of the foregoing method embodiments. The aforementioned storage medium may be a non-volatile storage medium such as a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM), or a random access memory (Random Access Memory, RAM).

It should be understood that although the various steps in the flowchart of the accompanying drawings are sequentially shown in the order indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order and may be performed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution sequence is also It does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of sub-steps or stages of other steps.

Embodiment 2

With further reference to FIG. 10 , as an implementation of the method shown in FIG. 2 above, the present application provides an embodiment of a multi-memory card testing device. The device embodiment corresponds to the method embodiment shown in FIG. 2 . The device can be specifically applied to various electronic devices.

As shown in FIG. 10 , the multi-memory card testing apparatus 400 according to this embodiment includes: an acquisition module 401 , a writing module 402 and a discriminating module 403 . in:

an acquisition module 401, configured to acquire a write command for writing the data and the number of the multi-memory card into the multi-memory card, and the write command includes the data and the number;

A writing module 402, configured to parse the write command, obtain the data and the serial number, and write the data into the multiple memory cards according to the serial number;

The discriminating module 403 is used to read the data from every two multi-memory cards with different numbers, store the read data in the comparison circuit for XOR operation, and judge the described data according to the result of the XOR operation. Whether two multi-memory cards with different numbers are normal.

By numbering multiple memory cards, data can be written to multiple multiple memory cards at the same time, without relying on manpower, the test of memory cards can be automatically performed, cost saving and test efficiency can be improved. The test is reliable and easy to implement, and can be widely used in storage card testing.

Referring to FIG. 11 , which is a schematic structural diagram of a specific implementation manner of the writing module 402 , the writing module 402 further includes a parsing module 4021 , a cache module 4022 and an output module 4023 . in,

Parsing module 4021, for parsing the write command to obtain the data and the serial number;

A cache module 4022, configured to cache the obtained data in a cache area;

The output module 4023 is configured to write the data in the buffer area into the multiple memory cards according to the number.

By setting the cache module, the contradiction between the speed mismatch between the CPU and the I/O device is alleviated. Reduce the interrupt frequency to the CPU, relax the restriction on the CPU interrupt response time, and protect the integrity of the written data.

Embodiment 3

To solve the above technical problems, the embodiments of the present application further provide computer equipment. Please refer to FIG. 12 for details. FIG. 12 is a block diagram of the basic structure of a computer device according to this embodiment.

The computer device 6 includes a memory 61 , a processor 62 , and a network interface 63 that communicate with each other through a system bus. It should be pointed out that only the computer device 6 with the component memory 61, the processor 62 and the network interface 63 is shown in the figure, but it should be understood that it is not required to implement all the shown components, and more can be implemented instead. or fewer components. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculation and/or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, special-purpose Integrated circuit (Application Specific Integrated Circuit, ASIC), Programmable Gate Array (Field-Programmable Gate Array, FPGA), Digital Signal Processor (Digital Signal Processor, DSP), embedded devices, etc.

The computer equipment may be a desktop computer, a notebook computer, a palmtop computer, a cloud server and other computing equipment. The computer device can perform human-computer interaction with the user through a keyboard, a mouse, a remote control, a touch pad or a voice control device.

The memory 61 includes at least one type of readable storage medium, the readable storage medium includes flash memory, hard disk, multiple memory cards, card-type memory (for example, test memory of SD or D multiple memory cards, etc.), random access Memory (RAM), Static Random Access Memory (SRAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Programmable Read Only Memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 61 may be an internal storage unit of the computer device 6 , such as a hard disk or a memory of the computer device 6 . In other embodiments, the memory 61 may also be an external storage device of the computer device 6, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, flash memory card (Flash Card) and so on. Of course, the memory 61 may also include both the internal storage unit of the computer device 6 and its external storage device. In this embodiment, the memory 61 is generally used to store the operating system and various application software installed on the computer device 6 , such as computer-readable instructions for a testing method for multiple memory cards. In addition, the memory 61 can also be used to temporarily store various types of data that have been output or will be output.

In some embodiments, the processor 62 may be a central processing unit (Central Processing Unit, CPU), a controller, a microcontroller, a microprocessor, or other data processing chips. This processor 62 is typically used to control the overall operation of the computer device 6 . In this embodiment, the processor 62 is configured to execute computer-readable instructions stored in the memory 61 or process data, for example, computer-readable instructions for executing the multi-memory card testing method.

The network interface 63 may include a wireless network interface or a wired network interface, and the network interface 63 is generally used to establish a communication connection between the computer device 6 and other electronic devices.

By numbering multiple memory cards, data can be written to multiple multiple memory cards at the same time, without relying on manpower, the test of memory cards can be automated, cost saving and test efficiency can be improved. The test is reliable and easy to implement, and can be widely used in storage card testing.

Embodiment 4

The present application also provides another embodiment, that is, to provide a computer-readable storage medium, where the computer-readable storage medium stores computer-readable instructions, and the computer-readable instructions can be executed by at least one processor to The at least one processor is caused to perform the steps of the method for testing multiple memory cards as described above.

By numbering multiple memory cards, data can be written to multiple multiple memory cards at the same time, without relying on manpower, the test of memory cards can be automated, cost saving and test efficiency can be improved. The test is reliable and easy to implement, and can be widely used in storage card testing.

From the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course hardware can also be used, but in many cases the former is better implementation. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence or in a part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to make a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of this application.

Obviously, the above-described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The accompanying drawings show the preferred embodiments of the present application, but do not limit the scope of the patent of the present application. This application may be embodied in many different forms, rather these embodiments are provided so that a thorough and complete understanding of the disclosure of this application is provided. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or perform equivalent replacements for some of the technical features. . Any equivalent structure made by using the contents of the description and drawings of the present application, which is directly or indirectly used in other related technical fields, is also within the scope of protection of the patent of the present application.

Claims (10)

1. A method for testing a multi-memory card, comprising the steps of:

acquiring a write-in command for writing data and the number of the multi-memory card into the multi-memory card, wherein the write-in command comprises the data and the number;

analyzing the write-in command, obtaining the data and the number, and writing the data into the multi-memory card according to the number;

and reading the data from every two multi-memory cards with different numbers, storing the read data into a comparison circuit for XOR operation, and judging whether the two multi-memory cards with different numbers are normal or not according to the result of the XOR operation.

2. The method for testing a multi-memory card according to claim 1, wherein before the step of obtaining a write command for writing data and a number of a multi-memory card into a multi-memory card, the write command carrying the data and the number, further comprises:

the rule of the write command is set.

3. The method for testing a multi-memory card according to claim 1, wherein the step of parsing the write command to obtain the data and the number, and writing the data into the multi-memory card according to the number specifically comprises:

analyzing the write-in command to obtain the data and the serial number;

caching the obtained data into a cache region;

and writing the data in the buffer area into the multi-memory card according to the number.

4. The method for testing a multi-memory card of claim 1, wherein the steps of reading the data from every two multi-memory cards with different numbers, placing the read data into a comparison circuit for xor operation, and determining whether the multi-memory cards are normal according to the xor operation result specifically include:

grouping every two memory cards according to the number of the multiple memory cards;

reading the data from every two multi-memory cards with different numbers, and putting the read data into a comparison circuit for XOR operation;

if the XOR operation result is 0, judging that the two multi-memory cards with different numbers are normal, and if the XOR operation result is 1, judging that one card of the two multi-memory cards with different numbers is abnormal;

and identifying the group of the abnormal multi-memory cards, and performing exclusive-OR operation on each multi-memory card in the group of the abnormal multi-memory cards and the detected normal multi-memory cards until the normal and abnormal conditions of all the multi-memory cards are detected.

5. The method for testing a multi-memory card according to claim 2, wherein the rule for setting the write command includes:

the first byte of the set write command represents the number of the multi-memory card.

6. The method for testing a multi-memory card according to any one of claims 1 to 5, wherein after the steps of reading the data from every two multi-memory cards with different numbers, putting the read data into a comparison circuit for exclusive-or operation, and judging whether the multi-memory cards are normal according to the exclusive-or operation result, the method further comprises:

and displaying the abnormal multi-memory card number.

7. A multi-memory card testing apparatus, comprising:

the device comprises an acquisition module, a storage module and a processing module, wherein the acquisition module is used for acquiring a write-in command for writing data and the serial number of the multi-memory card into the multi-memory card, and the write-in command comprises the data and the serial number;

the writing module is used for analyzing the writing command, obtaining the data and the number, and writing the data into the multi-memory card according to the number;

and the judging module is used for reading the data from every two multi-memory cards with different numbers, storing the read data into the comparison circuit for XOR operation, and judging whether the two multi-memory cards with different numbers are normal or not according to the result of the XOR operation.

8. The apparatus for testing a multi-memory card according to claim 7, wherein the writing module comprises:

the analysis module is used for analyzing the write-in command to obtain the data and the serial number;

the cache module is used for caching the obtained data into a cache region;

and the output module is used for writing the data in the buffer area into the multi-memory card according to the serial number.

9. A computer device comprising a memory having computer readable instructions stored therein and a processor which when executed implements the steps of the method of testing a multi-memory card of any of claims 1 to 6.

10. A computer-readable storage medium having computer-readable instructions stored thereon which, when executed by a processor, implement the steps of the method for testing a multi-memory card of any one of claims 1 to 6.

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