CN114446766A - Production process of ultra-high flatness silicon wafer - Google Patents
Production process of ultra-high flatness silicon wafer Download PDFInfo
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- CN114446766A CN114446766A CN202011222954.9A CN202011222954A CN114446766A CN 114446766 A CN114446766 A CN 114446766A CN 202011222954 A CN202011222954 A CN 202011222954A CN 114446766 A CN114446766 A CN 114446766A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 87
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 87
- 239000010703 silicon Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 claims abstract description 16
- 238000005498 polishing Methods 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 11
- 238000007789 sealing Methods 0.000 claims abstract description 10
- 239000000919 ceramic Substances 0.000 claims abstract description 6
- 230000000694 effects Effects 0.000 claims abstract description 6
- 238000000227 grinding Methods 0.000 claims abstract description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 18
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 12
- 230000007797 corrosion Effects 0.000 claims description 11
- 238000005260 corrosion Methods 0.000 claims description 11
- 239000003513 alkali Substances 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 230000035484 reaction time Effects 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims 1
- 239000007888 film coating Substances 0.000 abstract description 4
- 238000009501 film coating Methods 0.000 abstract description 4
- 238000009987 spinning Methods 0.000 abstract description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000002253 acid Substances 0.000 description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000002050 diffraction method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910000029 sodium carbonate Inorganic materials 0.000 description 2
- 235000017550 sodium carbonate Nutrition 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004018 waxing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
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Abstract
The invention relates to a production process of an ultra-high flatness silicon wafer, belonging to the technical field of silicon wafer processing, comprising the following operation steps: the first step is as follows: and slicing and processing the silicon wafer, and finishing the processes of excircle chamfering and grinding. The second step is that: and carrying out soda etching on the roughly processed silicon wafer. The third step: then the silicon wafer is cleaned, and the technological process of polycrystalline silicon back sealing is carried out by adopting the equipment model KV-J888. The fourth step: the edge of the silicon wafer is polished, then a thin layer of wax film is coated on the back of the silicon wafer in a spinning mode, the silicon wafer is attached to an aluminum oxide or silicon carbide ceramic plate through the bonding effect of the wax film, and then single-side polishing is conducted. The fifth step: after the single-side polishing is finished, dewaxing cleaning and final cleaning are carried out. Has the characteristics of good flatness and high quality stability. The microcosmic fluctuation of the back of the silicon wafer is reduced, and the problems of discontinuous wax film coating and slip sheet attachment are solved. Meanwhile, due to the random scattering of light on the surface of the polycrystalline silicon, the back surface glossiness of the silicon wafer is reduced.
Description
Technical Field
The invention relates to the technical field of silicon wafer processing, in particular to a production process of a silicon wafer with ultrahigh flatness.
Background
The flatness of the polished silicon single crystal wafer has a decisive influence on whether the device-side lithography process can be focused precisely. In a Chemical Mechanical Planarization (CMP) process, poor flatness of the silicon wafer also causes the possibility of uneven thickness and even failure of the polished film layer. At present, the process line width of an 8-inch CMOS device reaches the 90nm level, and according to ITRS Roadmap for Semiconductor (2006), for the 90nm device process, the SFQR of a silicon wafer needs to reach the level less than or equal to 0.1 mu m, which puts a strict requirement on the flatness of an 8-inch single-side polished silicon wafer.
The production process of the silicon single crystal polished wafer mainly comprises the following steps: single crystal pulling → roll grinding → linear cutting → chamfering → lapping → corrosion → (DK) → (CVD) → polishing → cleaning. Wherein the etching process is used for removing the mechanical damage layer caused by the grinding sheet. The etching process of the silicon wafer mainly comprises the following three processes: (1) acid etching (HF + HNO3+ acetic acid or phosphoric acid), (2) alkali etching (NaOH or KOH solution), and (3) mixed etching (alkali etching → acid etching or acid etching → alkali etching). Regardless of the etching process, the etching removal amount needs to reach 30 μm to ensure that the front damage layer can be removed cleanly. The acid etching process often causes the edge of the silicon wafer to collapse, which makes it difficult to achieve high local flatness of the silicon wafer after polishing. At present, the 8-inch silicon wafer with ultra-high flatness is usually subjected to soda etching or a mixed etching process based on soda etching, the edge collapse is also caused by an acid etching step in the mixed etching process in the prior art, and soda etching is the best choice for the silicon wafer which pursues extremely-high flatness.
The following two problems exist in the corrosion by using soda ash:
(1) sticking a slip sheet: the 8-inch silicon wafer is generally polished by using wax, a thin layer of wax film is required to be coated on the back surface of the silicon wafer in a spinning mode before polishing, the silicon wafer is attached to an alumina or silicon carbide ceramic plate by utilizing the bonding effect of the wax film, and then polishing is carried out. After the alkali Etching, the surface of the silicon wafer has a microscopic morphology (Etching Pit) with crystallographic characteristics (as shown in FIG. 1). The characteristic size of the silicon wafer Etching Pit corroded by soda ash is large (about 30-40 mu m), a complete and continuous wax film cannot be formed during rotary waxing, and the silicon wafer cannot be well bonded with a ceramic plate during attaching, so that the phenomenon of attaching a slide sheet occurs.
(2) Too high back gloss: the glossiness of the silicon wafer is far higher than that of the silicon wafer etched by acid due to the special micro-morphology of the surface of the silicon wafer by adopting the soda etching process. At the client, the silicon wafer undergoes a series of high temperature processes, and these high temperature processes mostly adopt radiation heating, and the excessively high glossiness leads to low heating efficiency and high thermal budget. For RTP (rapid thermal processing) processes, if the temperature of the silicon ingot is not rapidly raised, the thermal processing may not achieve the desired purpose.
Disclosure of Invention
The invention mainly solves the defects of easy attachment of the sliding sheet, poor flatness and low quality stability in the prior art, and provides a production process of a silicon wafer with ultrahigh flatness, which has the characteristics of good flatness and high quality stability. The microcosmic fluctuation of the back of the silicon wafer is reduced, and the problems of discontinuous wax film coating and slip sheet attachment are solved. Meanwhile, due to the random scattering of light on the surface of the polycrystalline silicon, the glossiness of the back surface of the silicon wafer is reduced.
The technical problem of the invention is mainly solved by the following technical scheme:
a production process of an ultra-high flatness silicon wafer comprises the following operation steps:
the first step is as follows: and (5) slicing and processing the silicon wafer, and finishing the processes of excircle chamfering and grinding.
The second step is that: carrying out soda etching on the roughly processed silicon wafer, wherein a chemical liquid tank cleaned before etching is set as follows: adding SC1 once, adding SC1 once again, and overflowing cold water; the chemical liquid tank cleaned after corrosion is set as follows: 1. SC1, 2 was added to carry out cold water overflow, and 3, HF, 4, HF, 5, cold water overflow. The alkali liquor adopted by the alkali corrosion is NaOH solution with the mass concentration of 30-49% or KOH solution with the mass concentration of 30-51%, and the temperature of the corrosion reaction is as follows: the reaction time is set according to the target removal amount at 70-98 ℃.
The third step: then cleaning the silicon wafer, and carrying out a polysilicon back sealing process by adopting equipment with the model of KV-J888; after the silicon wafer is subjected to polysilicon back sealing, the back surface of the silicon wafer is covered with a layer of polysilicon film, the crystallography characteristics are not obvious any more, the Etching Pit is filled with fine silicon crystal grains, and the inner wall of the smooth Etching Pit is covered with a rough polysilicon film layer.
The fourth step: the edge of the silicon wafer is polished, then a thin layer of wax film is coated on the back of the silicon wafer in a spinning mode, the silicon wafer is attached to an aluminum oxide or silicon carbide ceramic plate through the bonding effect of the wax film, and then single-side polishing is conducted.
The fifth step: after the single-side polishing is finished, dewaxing cleaning and final cleaning are carried out.
Preferably, the SC1 mixture ratio is as follows: NH4OH, H2O2, H2O =1:2, (5-20), and the concentration of HF is as follows: 1% -5% mass.
Preferably, the deposition temperature of the polysilicon back sealing process is 600-700 ℃, the flow rate of SiH4 is 0.3-0.5L/min, and the pressure is not more than 0.3 Pa.
Preferably, the gloss of the back side of the wafer is reduced by about 40GU after the polysilicon back seal.
Preferably, the Etching Pit is mostly in the shape of a truncated inverted pyramid with a smooth inner wall.
Preferably, the glossiness of the back surface of the silicon wafer after the soda etching is 106.2GU to 108.7GU, and the glossiness of the back surface of the silicon wafer after the deposition of the polycrystalline silicon film is 65.2GU to 65.6 GU.
The invention can achieve the following effects:
compared with the prior art, the production process of the ultra-high flatness silicon wafer has the characteristics of good flatness and high quality stability. The microcosmic fluctuation of the back of the silicon wafer is reduced, and the problems of discontinuous wax film coating and slip sheet attachment are solved. Meanwhile, due to the random scattering of light on the surface of the polycrystalline silicon, the glossiness of the back surface of the silicon wafer is reduced.
Drawings
FIG. 1 is a flow chart of the production process of the present invention.
FIG. 2 is a process flow diagram of soda etching and polysilicon back sealing according to the present invention.
Detailed Description
The technical scheme of the invention is further specifically described by the following embodiments and the accompanying drawings.
Example (b): as shown in fig. 1 and 2, a process for producing an ultra-high flatness silicon wafer comprises the following steps:
the first step is as follows: and (5) slicing and processing the silicon wafer, and finishing the processes of excircle chamfering and grinding.
The second step: carrying out soda etching on the roughly processed silicon wafer, wherein a chemical liquid tank cleaned before etching is set as follows: adding SC1 once, adding SC1 once again, and overflowing cold water; the chemical liquid tank cleaned after corrosion is set as follows: 1. SC1, 2 was added to carry out cold water overflow, and 3, HF, 4, HF, 5, cold water overflow. The SC1 mixture ratio is: NH4OH: H2O2: H2O =1:2:10, concentration of HF is: 1% -5% mass.
The alkali liquor adopted by the alkali corrosion is NaOH solution with the mass concentration of 49% or KOH solution with the mass concentration of 51%, and the temperature of the corrosion reaction is as follows: the reaction time was 7 minutes and 30 seconds at 85 ℃. The glossiness of the back surface of the silicon wafer after the soda etching is 107.5GU, and the glossiness of the silicon wafer after the deposition of the polycrystalline silicon film is 65.4 GU.
The third step: then the silicon wafer is cleaned, and the technological process of polycrystalline silicon back sealing is carried out by adopting the equipment model KV-J888. The deposition temperature of the polysilicon back sealing process is 630 ℃, the flow rate of SiH4 is 0.4L/min, and the pressure is 0.2 Pa. The gloss of the back side of the silicon wafer after the polysilicon back seal is reduced by about 40 GU.
After the silicon wafer is subjected to polysilicon back sealing, the back surface of the silicon wafer is covered with a layer of polysilicon film, the crystallography characteristics are not obvious any more, the Etching Pit is filled with fine silicon crystal grains, and the inner wall of the smooth Etching Pit is covered with a rough polysilicon film layer. Most of the Etching Pit is a truncated inverted pyramid with a smooth inner wall.
The fourth step: the edge of the silicon wafer is polished, then a thin layer of wax film is coated on the back of the silicon wafer in a spinning mode, the silicon wafer is attached to an aluminum oxide or silicon carbide ceramic plate through the bonding effect of the wax film, and then single-side polishing is conducted.
The fifth step: after the single-side polishing is finished, dewaxing cleaning and final cleaning are carried out.
In summary, the production process of the ultra-high flatness silicon wafer has the characteristics of good flatness and high quality stability. The microcosmic fluctuation of the back of the silicon wafer is reduced, and the problems of discontinuous wax film coating and slip sheet attachment are solved. Meanwhile, due to the random scattering of light on the surface of the polycrystalline silicon, the glossiness of the back surface of the silicon wafer is reduced.
The above description is only an embodiment of the present invention, but the structural features of the present invention are not limited thereto, and any changes or modifications within the scope of the present invention by those skilled in the art are covered by the present invention.
Claims (6)
1. A production process of an ultra-high flatness silicon wafer is characterized by comprising the following operation steps:
the first step is as follows: slicing and processing the silicon wafer, and finishing the processes of excircle chamfering and grinding;
the second step is that: carrying out soda etching on the roughly processed silicon wafer, wherein a chemical liquid tank cleaned before etching is set as follows: adding SC1 once, adding SC1 once again, and overflowing cold water; the chemical liquid tank cleaned after corrosion is set as follows: 1. adding SC1, 2, performing cold water overflow, 3, adding HF, 4, adding HF, 5, performing cold water overflow; the alkali liquor adopted by the alkali corrosion is NaOH solution with the mass concentration of 30-49% or KOH solution with the mass concentration of 30-51%, and the temperature of the corrosion reaction is as follows: setting the reaction time according to the target removal amount at 70-98 ℃;
the third step: then cleaning the silicon wafer, and carrying out a polysilicon back sealing process by adopting equipment with the model of KV-J888; after the silicon chip is back-sealed by polysilicon, the back surface of the silicon chip is covered with a layer of polysilicon film, the crystallographic characteristics are not obvious any more, the Etching Pit is filled with fine silicon crystal grains, and the smooth inner wall of the Etching Pit is covered with a rough polysilicon film layer;
the fourth step: polishing the edge of the silicon wafer, spin-coating a thin wax film on the back of the silicon wafer, attaching the silicon wafer to an alumina or silicon carbide ceramic plate by using the bonding effect of the wax film, and then polishing the single surface of the silicon wafer;
the fifth step: after the single-side polishing is finished, dewaxing cleaning and final cleaning are carried out.
2. The process for producing an ultra-high flatness silicon wafer according to claim 1, wherein: the SC1 mixture ratio is: NH4OH, H2O2, H2O =1:2, (5-20), and the concentration of HF is as follows: 1% -5% mass.
3. The process for producing an ultra-high flatness silicon wafer according to claim 1, wherein: the deposition temperature of the polysilicon back sealing process is 600-700 ℃, the flow of SiH4 is 0.3-0.5L/min, and the pressure is not more than 0.3 Pa.
4. The process for producing an ultra-high flatness silicon wafer according to claim 3, wherein: the gloss of the back side of the silicon wafer after the polysilicon back seal is reduced by about 40 GU.
5. The process for producing an ultra-high flatness silicon wafer according to claim 1, wherein: most of the Etching Pit is a truncated inverted pyramid with a smooth inner wall.
6. The process for producing an ultra-high flatness silicon wafer according to claim 1, wherein: after the soda is corroded, the glossiness of the back of the silicon wafer is 106.2 GU-108.7 GU, and the glossiness of the deposited polycrystalline silicon film is 65.2 GU-65.6 GU.
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|---|---|---|---|---|
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2020
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