JP3943869B2 - Semiconductor wafer processing method and semiconductor wafer - Google Patents

Description

【００５０】
この試験の結果から、ピット深さについては、酢酸をリン酸にすることで大きく改善できることがわかり、特に酢酸ではピット深さが７μｍ程度であったものが、リン酸に置き換えるとピット深さは３〜４μｍ程度となった。また、リン酸濃度（重量％）が高いほどピットが小さいと考えられる。
【００５１】
上記のようにピット深さについては、リン酸の効果が大きいことがわかる。
面状態については、試験番号９、１１、１２のように、フッ酸濃度（重量％）が硝酸の濃度より濃い場合は、表面がガサガサの状態となり表面が曇化し光沢度が低下してしまった。フッ酸が濃すぎるかまたは硝酸が薄すぎると面状態が悪くなる。従って、フッ酸濃度が硝酸よりも薄い状態でエッチングすることが好ましい。また、試験番号１のようにフッ酸濃度が硝酸濃度よりはるかに薄いとエッチングされない（殆ど反応しない）。従って、（フッ酸／硝酸）比は１／７以上とすることが好ましい。このようにエッチングされない（ほとんど反応しない）状態では、ウエーハ表面が元のアルカリエッチングの面状態であり、深いピットおよび表面粗さの粗い状態が残ってしまう。また仮にエッチングを続けた場合、ピットは小さくなるが、エッチング時間が大変長いものとなり操業上問題である。また、リン酸濃度が４０重量％以上でもエッチングがおそいことがある。これはフッ酸とリン酸の副反応等の影響によりエッチングが進まなくなるためと考えられる。
【００５２】
以上のことを考慮に入れると、特に（フッ酸／硝酸）の比は１／２程度で、リン酸濃度が４０重量％以下だと大変良好な面状態のウエーハが得られる。光沢度もエッチング時間の調整で２０〜７０％と広範囲に調整することができた。
【００５３】
ここで、表１の面状態は、目視による外観検査を行い、表面がガサガサになってしまい光沢度が低下する状態やアルカリエッチングの面状態が残ってしまう状態であり、そのままの表面状態では使用が困難なものを△（やや難あり）とした。アルカリエッチングの面状態が残ってしまう場合はエッチング時間を長時間にすることで、面状態の改善は可能であるが操業上は難がある。また表面がガサガサになったものでも、ピット深さは小さくなっているので、ウエーハの両面を研磨する場合の原料ウエーハとして使用することも可能である。表面はエッチングされ光沢度は良好なものの、ややまだら模様が残る場合を○（良好）とした。これらは特に問題なく使用できる。さらに光沢度も向上し従来の酢酸系混酸と同等であり製品として要望される光沢度の範囲に調整可能なものを◎（たいへん良好）とした。また、ピット深さは、ウエーハ表面をスキャンし、ピットのある部分で光学顕微鏡の焦点深度により求めた値であり、得られたピット深さの最大値を示したものである。
【００５４】
これら、ピット深さおよび面状態より、好ましいリン酸系混酸の濃度範囲は、調合時の初期濃度として、フッ酸（ＨＦ）が５〜１５重量％、硝酸（ＨＮＯ₃ ）が２０〜４５重量％、リン酸（Ｈ₃ ＰＯ₄ ）が１０〜４０重量％、残り水（Ｈ₂ Ｏ）程度である。
【００５５】
これは、調合時のフッ酸濃度を５重量％以下とするとエッチング効果（反応性）が悪くなる。また、１５重量％以上であると硝酸との関係で面状態が悪くなる。硝酸については、特に明確な知見は得られなかったものの、フッ酸、リン酸との関係から２０〜４５重量％の範囲が好ましいと考えられる。特に（ＨＦ／ＨＮＯ₃ ）比が１／（２〜７）が好ましい。リン酸については１０重量％以下だとピットの改善効果が小さくなり、４０重量％以上であるとフッ酸や水等との副反応が増し、エッチングが不安定になり、遂にはエッチング効果がなくなることがあり、面状態が悪くなることがある。
【００５６】
酸エッチングのエッチング代としては、両面で５〜２０μｍが適切な範囲である。特に両面で１０μｍ程度がピットを浅くし、平坦度も維持したまま、表面を滑らかにエッチングすることができる。これは、リン酸が持っている粘度の影響でラッピングによるピットや研削条痕部分のピット内に混酸が入り難くなり、ピット内のエッチング速度を他の平面よりも遅くしているためと考えられる。
【００５７】
次に、実際のエッチング中の各組成比について確認した。調合時は、上記濃度範囲が好ましいが、実際にはエッチング中に組成は変化して行く。シリコンウエーハをエッチングすると薬液中の各組成は、フッ酸濃度は減少、硝酸濃度は徐々に減少、リン酸濃度は殆ど変化せず、水の濃度は増加していく傾向がある。特にエッチング開始直後は組成が不安定である。
【００５８】
そこでエッチング液を安定させるために、予め混酸にシリコンを溶解させておくことが好ましい。このシリコン溶解をした時の組成（実際に使用する時の組成）を確認した。
表２は、シリコン溶解量を０〜２０ｇ／Ｌと変化させた時のエッチング液中の各成分濃度を示したものである。調合時（初期）のエッチング液組成は試験番号１３と同じ５０重量％フッ酸、７０重量％硝酸、８５重量％リン酸を容量比で１：３：２で調合したリン酸系混酸を用い、これにシリコンを溶解した時に実際のエッチング組成がどのように変化するかを確認したものである。
【００５９】
また、このシリコン溶解量によって、うねりや周辺ダレも大きく改善できることが確認されたため、表２に示した各エッチング液を用い、＃１２００のラップ砥粒でラッピングし、両面で２０μｍのアルカリエッチングをしたウエーハを両面で１０μｍ酸エッチングしてうねりを評価した。その結果を表２に併記した。
【００６０】
【表２】

【００６１】
表２から判るように、予めシリコンを溶解しておくことにより調合時の濃度（初期濃度）は変化する。５０重量％フッ酸、７０重量％硝酸、８５重量％リン酸を容量比で１：３：２で調合したリン酸系混酸では、使用時のエッチング組成はおよそフッ酸濃度は１〜７重量％程度、硝酸は２５〜３３重量％、リン酸は１８〜３３重量％程度となっており、このような組成範囲で使用することが好ましい。また、シリコン溶解を１０ｇ／Ｌ以上するとうねりが０．０５μｍ以下と大変良好なウエーハが製造できるのでさらに好ましい。シリコン溶解量は多い程、うねりを小さくすることができる。
【００６２】
ここで、うねり（Ｗａｖｉｎｅｓｓ）とは、測定開始地点と測定終了地点の高さを一致させて高さの原点とし、２ｍｍピッチで原点からの変位量の絶対値Ｙ₁ からＹ_２９を測定し、その平均値Ｙをうねりと定義している。
うねりの測定装置には、（株）小坂研究所製万能表面形状測定器（ＳＥ−３Ｆ型）を用いた。測定方法は、ウエーハ（直径２００ｍｍ）の表面の中央部６０ｍｍを触針によりなぞり、細かい表面粗さ成分を除いた形状成分のみを測定する。
【００６３】
また、シリコンを１０ｇ／Ｌ以上溶解しておくとエッチング組成が安定化する。調合した直後のエッチング液は反応性が不安定である。ある程度のシリコンを予め溶解しておくことで反応性およびエッチング液の組成が安定化する。また、シリコン溶解をしていない調合直後の濃度にエッチング組成を戻すにはエッチング液をほとんど全量交換する必要があるが、シリコン溶解した後の状態に戻すのは容易で、シリコン溶解していないエッチング液を部分的に交換（追加）するだけで済み、液交換量を減らすことができる。結果としてエッチング液の濃度、バラツキも小さくなり、かつ制御が容易になり、酸エッチング状態を安定化させることができる。
【００６４】
以上述べたように、リン酸を含む混酸を酸エッチングに使用することにより、従来の酢酸系混酸エッチングより下記の点で優れていることが判った。
すなわち、
１）ピットの深さを従来のアルカリエッチング＋酢酸系混酸エッチングより浅くすることができる。
２）平滑化の効率が高い。
３）うねり成分が少ない。
４）表面粗さが細かくなり、光沢度が上がる。
【００６５】
各種エッチング方法と得られたウエーハの品質、特性の関係を表３にまとめて比較した。なお、リン酸系の酸溶液のみでエッチングした場合、エッチング代を多くすると酢酸系の酸溶液のみでエッチングした場合と同様、平坦度が悪くなる傾向にある。またエッチング速度も遅く生産性が良くない。本発明のように（アルカリ＋リン酸系）のエッチング液で処理することによりリン酸系で処理するエッチング代が低減され、上記問題も改善でき更に研磨工程の研磨代を著しく少なくすることができ好ましい。以上から本発明の優位性が明らかである。
【００６６】
【表３】

【００６７】
なお、エッチング代（エッチングによる取り代）は、多すぎるとアルカリエッチング及び酸エッチングを行うエッチングによってもウエーハ外周ダレが生じ易い。従ってエッチング工程では両面で１０〜３０μｍ程度に従来の取り代より少なくする方がよい。好ましくはアルカリエッチングで両面で１５μｍ、酸エッチングで両面で５μｍ程度にする。
【００６８】
以上述べた本発明のアルカリエッチング＋リン酸系混酸エッチングの二段階化学エッチングによれば、ピット深さの最大値が４μｍ以下、２ｍｍピッチのうねりのＰＶ値が０．０５μｍ以下、かつ光沢度範囲が２０〜７０％である半導体ウエーハを容易に安定して製造することができる。
【００６９】
また本発明者等は、鏡面研磨工程前に加工歪みおよびこれに起因するピット等の残留が少ないウエーハの製造方法、特にエッチング工程や、その前工程を種々検討した結果、ラッピング工程の代わり、またはラッピング工程の後に平面研削工程を組み込むことで、スライシングあるいはラッピングによって生じていた歪み層を極めて少なくし、高平坦度を維持したウエーハを得、さらにアルカリエッチングを行い、平面研削で残ってしまう歪み層および研削条痕を除去し、さらに残った研削条痕によるピットを改善するために、フッ酸、硝酸、リン酸の混合水溶液を酸エッチング液として酸エッチングを行なうことを発想し、処理条件を究明して本発明を完成させた。
【００７０】
図１は、本発明の単結晶棒を加工して半導体鏡面ウエーハを製造する一連のフロー図である。図１（ａ）は平面研削工程、エッチング工程の順からなるフロー図であり、図１（ｂ）はラッピング工程を前に加えた平面研削工程、エッチング工程の順からなるフロー図である。
【００７１】
図１（ａ）は、ラッピング工程を完全に平面研削工程に置き換えた鏡面ウエーハの製造工程であって、単結晶棒をスライス工程でスライスしてウエーハを得、平面研削工程で平面研削にかけて、平坦度の改善及びスライス工程で生じた機械的加工変質層を除去する。次に面取り工程でウエーハに面取り加工を施し、エッチング工程に入る。エッチングは先ずアルカリエッチングを行って歪み層や研削条痕を除去し、あるいは浅くし、次いでリン酸系混酸で酸エッチングを行って研削条痕を浅くする。この際、アルカリエッチングのエッチング代を酸エッチングのエッチング代よりも大きくすることが好ましい。続いて鏡面研磨工程で鏡面研磨を施し、洗浄・乾燥工程で洗浄・乾燥して高平坦度の鏡面ウエーハを作製することができる。
【００７２】
図１（ｂ）は、平面研削工程の前にラッピング工程を加えた鏡面ウエーハの製造工程であって、単結晶棒をスライス工程でスライスしてウエーハを得、１次面取り工程でウエーハに粗面取り加工を施した後、ラッピング工程でラップし、平坦度の改善及びスライス工程で生じた機械的加工変質層を除去する。続いて平面研削工程で平面研削にかけて、更に平坦度を良くする。次に２次面取り工程で仕上げの面取り加工を施し、エッチング工程に入る。エッチングは先ずアルカリエッチングを行って歪み層や研削条痕を除去し、次いでリン酸系混酸で酸エッチングを行って研削条痕を浅くする。この際、アルカリエッチングのエッチング代を酸エッチングのエッチング代よりも大きくすることが好ましい。続いて鏡面研磨工程で鏡面研磨を施し、洗浄・乾燥工程で洗浄・乾燥して高平坦度鏡面ウエーハを作製することができる。
【００７３】
先ず、平面研削の標準的な条件としては、スピンドル回転数：４０００〜７０００ｒｐｍ、 ウエーハ回転数：５〜９ｒｐｍ（加工時）、３〜７ｒｐｍ（スパークアウト時）、 砥石送り速度：０．１〜０．３μｍ／ｓｅｃが好ましい。
使用する砥石は、高ヤング率タイプのものがよく、平面研削装置は砥石が中心切り込みであるインフィード型の平面研削装置が好ましい。
平面研削装置としては、両面を同時に研削する両頭研削装置や片面づつ、または片面のみを研削する装置があるが、特に装置の形態は限定されない。
平坦度の改善及びスライスによる機械的加工変質層を除去するためには一般的に両面で４０〜６０μｍ（片面２０〜３０μｍ）の研削でよい。
【００７４】
ここで、ラッピング工程では、ラップ砥粒の影響により、局所的な深いダメージ（ピット）が形成されていたが、平面研削ではこの局所的な機械的加工歪みも少なく加工できるようになる。
しかし平面研削工程の条件にも若干影響されるが、平面研削では研削条痕が残ってしまう。この研削条痕は、砥石の切れ込みの跡がウエーハ表面にすじ状に残ったものである。
【００７５】
そこで前述したようなエッチングを行う。先ずアルカリエッチングを行って歪み層や研削条痕を除去し、次いでリン酸系混酸で酸エッチングを行って研削条痕を浅くする。続いて鏡面研磨工程で鏡面研磨を施し、洗浄・乾燥工程で洗浄・乾燥して高平坦度鏡面ウエーハを作製することができる。
【００７６】
以上の一連の工程により加工して製造されたウエーハは、ピット等が非常に浅く、または完全に存在せず、また、うねり成分も少ない。表面粗さも細かくなり光沢度があがる。従って、研磨工程での研磨代（取り代）を著しく少なくすることができ、高平坦度のウエーハを高い生産性で得ることができる。
【００７７】
一方、前述のようにウエーハ加工工程において、ウエーハ裏面輝度（光沢度）の低下及びうねりの発生、更には低抵抗率結晶で生じ易いブルーステイン（以下単にステインということがある）といわれる汚れが生じることがある。エッチング工程の条件（例えばエッチング代を少なくした場合）によってはウエーハ裏面の光沢度は１５から２０％程度に低下してしまうことがあった。
そこで、本発明者らはこの問題を解決するため、鏡面研磨工程において、前記酸エッチング後、裏面研磨工程を行ない、その後表面研磨工程を行なうことを発想した。
【００７８】
以下に本発明の裏面研磨を行う場合につき説明する。図２は、本発明の裏面研磨工程を有する半導体ウエーハの加工する方法を例示した一連のフロー図である。前述の図１の半導体ウエーハの加工方法に加えて、ウエーハ表面を鏡面研磨する表面研磨工程の前に裏面研磨工程が行われることがこの方法の特徴である。
【００７９】
スライス工程では従来の方法・装置を用いれば良い。例えばワイヤーソーや内周刃のスライス装置を用い、ワープが少なくするようにスライスすることが好ましい。特にワープ（ソリ）を１０μｍ以下に抑えるようにスライスする。
【００８０】
面取り工程も、従来からある方法及び装置を用いれば良い。スライス後早い段階で、カケ、ワレを防止するために外周の角を丸めるべべリング加工（面取り加工）を行い、その後表面研磨工程までに面取り部を鏡面化する面取り加工を行なうのが好ましい。
特に面取り工程は平面研削工程の後に実施するのが好ましい。ラッピング工程がある場合はラッピング工程の前に入れるのが好ましい。もちろん面取り工程を複数箇所入れても良い。本案ではラッピング前に１次面取り工程、及び平面研削後に２次面取り、裏面研磨後に鏡面面取り工程を入れた例を示した。
【００８１】
平坦化工程では、ラッピング工程のみ、または平面研削工程のみでも良いが、前述のように平面研削工程の方が機械的歪みは小さく、またラッピング工程に比べ、ウエーハ形状を比較的容易に制御でき、同じ形状を安定的に得ることができ好ましい。ラッピング工程の後に平面研削工程を加え、ラッピング工程、平面研削工程、エッチング工程の順で加工を行なっても良い。
【００８２】
なお、平面研削では、深いピットを除去することも可能である。従って、エッチング工程の後、研磨工程前に平面研削工程を入れる場合も考えられるが、平面研削では、研削条痕と言われる模様が残ってしまう。また、研削によるダメージも数μｍ程度残ってしまう。従って、この研削条痕を消すために研磨工程での研磨代を多くする必要がある。従って、本発明では平面研削工程は、エッチング工程の前に行う。特にラッピング工程をそのまま残した工程ではラッピング工程、平面研削工程、エッチング工程の順に行なうことが好ましい。こうすることによって、ラッピングに起因する深いピットを除去できるし、平面研削に起因する研削条痕を除去又は浅くすることができる。
【００８３】
平坦化工程の条件としては、ラッピング工程の場合、＃１２００〜＃１５００程度のラッピング砥粒を用い平坦化することが好ましい。ラップ代（ラッピングによる取り代）は両面で４０〜６０μｍ程度で良い。好ましくは＃１２００のラッピング砥粒で両面で４０μｍ、更に＃１５００番で両面で２０μｍの２段ラップを行なうのが好ましい。このように後段は、＃１５００と細かな砥粒を含むラップスラリーを用いることが好ましい。
【００８４】
ラッピングに続き平面研削を行なう場合、＃１５００〜＃４０００程度の砥粒砥石を用いることが好ましい。研削代（平面研削による取り代）はおよそ片面１０μｍ程度で良い。平面研削に使用する砥石は、高ヤング率、研削装置は砥石が中心切り込みであるインフィード型の研削装置が好ましい。
【００８５】
平坦化工程として平面研削を用いると、例えば歪みの少ない研削工程後でも研削条痕が残ってしまう。研削条痕も一種の機械的加工歪み層で、若干の歪み（ダメージ）が入っていると考えられる。従って、この平面研削を行なったウエーハをアルカリエッチングすると、ラッピング工程の後にアルカリエッチングした時に現れていた局所的なピットは防止できるものの、平面研削を行った研削条痕の部分が、残留または強調されピット状になってしまう事がある。
【００８６】
従来も、高平坦度なウエーハを得るために平面研削を研磨前にすることがあったが、これでは研削条痕が残ってしまう等の問題がある。本発明では、表面研磨の前の工程において平面研削を行っても、その形状を維持したままエッチング及び研磨して、研削条痕を除去することができる。
【００８７】
すなわち、本発明のエッチング工程では、前述のように、エッチング工程でまずアルカリエッチングをした後、酸エッチングを行うものとした。さらに酸エッチングをフッ酸、硝酸、リン酸、水からなる酸エッチングを行うことにより、うねりが小さくなり、研削条痕も浅くすることができる。
【００８８】
裏面研磨工程は、酸エッチングの後、表面研磨工程前に実施する。裏面の光沢度の調整のみであれば、エッチング後のどの工程で実施することも可能であるが（例えば表面研磨工程後に実施してもよい）、酸エッチングの後、表面研磨工程前に実施すれば、裏面研磨によるウエーハ裏面のうねり成分も改善された状態で表面研磨されることになるので、裏面形状の転写等の影響を極力少なくすることができ、ナノトポグラフィレベルでの凹凸も軽減され、高平坦度な状態を維持したまま表面を研磨することができる。またこれによりウエーハ裏面の光沢度の調節はもとより、ブルーステインの除去等も行われ裏面品質の良好なウエーハが製造できる。裏面光沢度は３５〜５０％とすることが好ましい。これには研磨代（研磨による取り代）は片面で０．４μｍ以下０．０５μｍ以上、好ましくは０．１μｍから０．３μｍ程度が好ましい。
【００８９】
表面研磨工程は、研磨による外周ダレが生じない条件で研磨すれば特に限定されない。しかし、特に複数段で研磨する場合、表面側全体で研磨代を４μｍ以下とすることが好ましい。但し、良好な鏡面を得るには１μｍ程度は研磨するのが望ましい。
このように研磨代を抑える事で、それ以前の工程の平坦度を維持したまま高平坦度なウエーハを製造する事ができる。
【００９０】
特に、本発明の表面（鏡面）研磨工程においては、前記エッチング工程においてうねりが小さく、研削条痕（研削条痕によるピット）も非常に浅いウエーハが得られているので、研磨代を極めて小さくすることができ、高平坦度の鏡面ウエーハを得ることができる。また裏面研磨工程を研磨前に入れたことにより、裏面のうねりの転写がウエーハ表面に起こることが減少し表面研磨の研磨代も更に小さくすることができる。その結果、ナノトポグラフィレベルの凹凸も軽減され、研磨による平坦度の低下も抑えられ、高平坦度なウエーハが得られるという利点がある。また、研磨代を低減できることから研磨工程の生産性を著しく向上させることができる。
【００９１】
【実施例】
以下、本発明の実施例と比較例を挙げて具体的に説明するが、本発明はこれらに限定されるものではない。
（実施例１）
上記考察の結果、ピット深さ、面状態、エッチングレート、エッチング液の安定性等を考慮すると、調合比として５０重量％フッ酸：７０重量％硝酸：８５重量％リン酸＝１：３：２のエッチング液、つまりＨＦ＝６．６重量％、ＨＮＯ₃ ＝３４．０重量％、Ｈ₃ ＰＯ₄ ＝３２．５重量％、残分Ｈ₂ Ｏ（２６．９重量％）、シリコン溶解量＝１９ｇ／Ｌにしたエッチング液が好ましいことが判った。以下にこの酸エッチング液を用いた実施例を説明する。
【００９２】
直径２００ｍｍ（８インチ）のラップウエーハ（ラップ砥粒番手：＃１２００）を使用して次のエッチング処理を行った。このラップウエーハのＴＴＶはおよそ０．８μｍであった。
先ず、アルカリエッチングは、エッチング代目標を両面で２０μｍとし、濃度５０重量％のＮａＯＨ水溶液に８５℃で４５０秒間浸漬した。次に、親水化処理として０．３％の過酸化水素水に浸漬した後、最後に、上記した５０重量％フッ酸：７０重量％硝酸：８５重量％リン酸＝１：３：２（容積比）から成る混酸でエッチング代目標を両面で１０μｍとして液温２５℃で酸エッチングを行った。エッチングを終了したものについては、平坦度（ＴＴＶ）、表面粗さ（Ｒａ）、うねり、ピット深さ、光沢度を測定し、エッチングの効果を調査した。その結果を表４に示す。
【００９３】
（比較例１）
酸エッチング液を従来の酢酸系混酸である５０重量％フッ酸：７０重量％硝酸：１００重量％酢酸＝１：２：１（容積比）から成る混酸を使用した以外は実施例１と同条件でエッチングした。その結果を表４に併記した。
【００９４】
【表４】

【００９５】
表４より、実施例１（リン酸系混酸）では平坦度（ＴＴＶ）やうねりの大変良好なウエーハが得られた。またピット深さも非常に小さいウエーハが製造できた。光沢度は従来と同様な値になり、規格の範囲に調整できることがわかった。また、ウエーハ面取り部の表面粗さ（Ｒａ）もよく、鏡面面取り等の負荷が減る等の効果もある。
【００９６】
次に上記実施例１および比較例１のＣＷウエーハ表面を研磨した。研磨代は表面側全体で７μｍ（目標値）とした。研磨条件は、研磨装置：枚葉式研磨装置、研磨布：不織布タイプ研磨布、研磨剤：コロイダルシリカ研磨剤（ｐＨ＝１０．５）を用いて研磨した。
【００９７】
研磨品についてＴＴＶおよびＳＦＱＲmax を測定し、外観を検査した。
ここでＳＦＱＲ（Ｓｉｔｅ Ｆｒｏｎｔ ｌｅａｓｔ−ｓＱｕａｒｅｓ Ｒａｎｇｅ）とは、平坦度に関して表面基準の平均平面をサイト毎に算出し、その面に対する凹凸の最大範囲を表した値であり、ＳＦＱＲmax はウエーハ上の全サイトのＳＦＱＲの中の最大値を表している。
結果を表５に示す。また、比較例１については更に研磨を行い外観異常が見られなくなるまで研磨した（比較例１ｂ）。
【００９８】
【表５】

【００９９】
ここで、平坦度ＴＴＶ及びＳＦＱＲmaxの測定は、ＡＤＥ社製のフラットネス測定器（Ｕ／Ｇ９５００、Ｕ／Ｓ９６００）を用い、表面粗さ（Ｒａ）の測定は、（株）小坂研究所製万能表面形状測定器（ＳＥ−３Ｃ型）を用いた。
また、平坦度ＳＦＱＲｍａｘは、ＡＤＥ社製フラットネス測定器を用い、２０ｍｍ×２０ｍｍのエリアで評価した。外観については、ピットの有無を顕微鏡で確認した。
【０１００】
上記の結果から分かるように、実施例１では研磨代７μｍ以下の研磨で、高平坦度及び外観異常（ピット）のないウエーハが製造できた。これは、アルカリエッチ→リン酸含有酸エッチを行い、エッチング後のピット深さを従来に比べ小さくしたことにより達成することができた。また、研磨代を少なくできることで、研磨効率の向上が計れるとともに、研磨による外周ダレを防止し、ウエーハ外周の平坦度に優れたウエーハを製造することができる。
【０１０１】
以上述べたように、ＣＷウエーハは、アルカリエッチング、リン酸含有酸エッチングとすることで、平坦度及びピット深さが改善されている。またうねりも少ないウエーハが得られる。光沢度は比較例、実施例とも同じ程度に調整できる。
【０１０２】
ＰＷウエーハは、比較例では外観異常があり、研磨代が足りないことがわかる。通常、エッチング後のピットを完全に無くすため、ピット深さ＋３μｍ程度の過剰な研磨が必要である。研磨量を増やすことにより加工時間も長くなってしまう。また、比較例を見れば分かるように、ＳＦＱＲｍａｘは研磨代が増えると悪くなる。研磨代は少ない方が好ましい。リン酸含有酸エッチングでは研磨代を少なくすることができ、ＳＦＱＲｍａｘなどの平坦度を良くした鏡面研磨ウエーハが製造することができた。
【０１０３】
（実施例２）
図１（ｂ）に示すような工程で鏡面ウエーハを作製した。直径約２００ｍｍのインゴットをスライス、１次面取りし、その後ラップスラリー（ラップ砥粒番手＃１２００）を使用し，ラッピングしたウエーハ（ラップウエーハという）を使用して、次のような条件で平面研削を行った。
【０１０４】
平面研削はインフィード型の片面研削装置を用い、スピンドル回転数５５００ｒｐｍ、ウエーハ回転数７ｒｐｍ、砥石送り速度０．２μｍ／ｓｅｃで行った。その後、２次面取りを行った。
この平面研削後のウエーハの平坦度（ＴＴＶ）はおよそ０．６μｍであった。
【０１０５】
次に、アルカリエッチングは、エッチング代目標を両面で２０μｍとし、上記ウエーハを濃度５０重量％のＮａＯＨ水溶液に８５℃で４５０秒間浸漬しエッチングを行った。次に親水化処理として０．３％の過酸化水素水に浸漬した後、５０重量％フッ酸：７０重量％硝酸：８５重量％リン酸＝１：３：２（容量比）からなる混酸でエッチング代目標を両面で１０μｍとして液温２５℃で酸エッチングを行った。
【０１０６】
酸エッチングを終了したものについては、平坦度（ＴＴＶ）、表面粗さ（Ｒａ）、うねり、外観検査（およびピット深さ）、ウエーハ裏面の光沢度を測定し、平面研削＋エッチングの効果を調査した。
【０１０７】
ＴＴＶの測定は、ＡＤＥ社製フラットネス測定器（Ｕ／Ｇ９５００、Ｕ／Ｓ９６００）を用いた。Ｒａの測定は、（株）小坂研究所製万能表面形状測定器（ＳＥ−３Ｃ型）を用い、ウエーハ中央部分を測定した。
【０１０８】
うねりは、測定開始時点と測定終了時点の高さの差を一致させて高さの原点とし、２ｍｍピッチで原点からの変位量の絶対値Ｙ_１からＹ_２９を測定し、その平均値をうねりと定義している。うねりの測定装置には（株）小坂研究所製万能表面形状測定器（ＳＥ−３Ｆ型）を用いた。測定はウエーハの中央部分６０ｍｍを触針によりなぞり、細かい表面粗さ成分を除いた形状成分のみ測定した。
【０１０９】
外観検査については、ピットの有無を顕微鏡で観察した。
ピットが観察された場合、ピット深さを確認した。ピット深さは光学顕微鏡の焦点深度により求めた。ピット深さは、複数枚評価したウエーハの最大値で示す。
【０１１０】
光沢度は、ウエーハ裏面について、東洋精機製グロスメーターＳＤにより求めた。
以上の結果を表６に示す。
【０１１１】
【表６】

【０１１２】
次に、上記エッチング終了後のウエーハを、鏡面研磨した。先に平面研削した側の面を研磨し、研磨代は目標値４μｍとした。
研磨条件は、研磨装置；枚葉式研磨装置、 研磨布；不織布タイプ研磨布、
研磨剤；コロイダルシリカ研磨剤（ｐＨ＝１０．５）を用いて研磨した。
【０１１３】
研磨したウエーハについて、ＴＴＶおよびＳＦＱＲｍａｘを測定し、外観検査を行った。
ＳＦＱＲの測定は、ＡＤＥ社製フラットネス測定器を用い、サイトの大きさを２０ｍｍ×２０ｍｍのエリアで評価した。結果を表７に示す。
【０１１４】
【表７】

【０１１５】
上記の結果から判るように、実施例２では研磨代４μｍ以下の研磨で、高平坦度および外観異常（研削条痕やピット）のないウエーハが製造できた。これはエッチング、特にアルカリエッチングの前に平面研削を実施し、さらにエッチング工程でアルカリエッチングの後に、リン酸を含む混酸の酸エッチングしたことにより達成することができた。
【０１１６】
（比較例２）
実施例２と同様に、直径２００ｍｍのラップウエーハ（ラップ砥粒番手：＃１２００）を使用して次にエッチング処理を行った。エッチングは、アルカリエッチングおよびフッ酸、硝酸、酢酸系の混酸を用いた酸エッチングの２段で行った。
【０１１７】
アルカリエッチングは、エッチング代目標を両面で２０μｍとし、上記ウエーハを濃度５０重量％のＮａＯＨ水溶液に８５℃で４５０秒間浸漬しエッチングを行った。次に親水化処理として０．３％の過酸化水素水に浸漬した後、５０重量％フッ酸：７０重量％硝酸：１００重量％酢酸＝１：２：１（容量比）からなる混酸でエッチング代目標を両面で１０μｍとして液温２５℃で酸エッチングを行った。
【０１１８】
エッチングを終了したものについては、平坦度（ＴＴＶ）、表面粗さ（Ｒａ）、うねり、外観検査（およびピット深さ）、光沢度を測定した。その結果を表６に併記した。
【０１１９】
次に、上記エッチング終了後のウエーハを、鏡面研磨した。研磨代は目標４μｍとした。研磨条件は、実施例２と同様である。
研磨したウエーハについて、ＴＴＶおよびＳＦＱＲｍａｘを測定し、外観検査を行った。結果を表７に併記した。
上記の結果から判るように、比較例２では研磨代４μｍでは、ピットが存在していた（表７：比較例２−ａ）。
【０１２０】
さらに研磨を続け、ピットが消えるまで研磨を行った（表７：比較例２−ｂ）。その結果表面側全体で約１０μｍ研磨することでピットは消えたが、平坦度が若干悪くなってしまった。
【０１２１】
（実施例３）
図２に示すような工程で鏡面ウエーハを製造した。直径２００ｍｍ、抵抗率０．０２Ω・ｃｍの単結晶棒（インゴット）をワイヤーソーによりスライスし、１次面取りを行なった後、ラップスラリー（ラップ砥粒番手＃１２００）を使用し、両面で４０μｍラッピングした。次にラップスラリーのラップ砥粒番手＃１５００に切り替え、更に両面で２０μｍラッピングを行なった。
【０１２２】
次に平面研削を行なった。平面研削はインフィード型の片面研削装置を用い、表面を＃４０００の砥石を用い片面１０μｍ研削した。平面研削の条件は、スピンドル回転数５５００ｒｐｍ、ウエーハ回転数：７ｒｐｍ、砥石送り速度０．２μｍ／ｓｅｃで行なった。その後２次面取りを行なった。
【０１２３】
この段階で、従来はラッピング時には、ラップ砥粒の影響により、局所的なダメージ（ピット）が形成されていたが、平面研削ではこの局所的な機械的加工歪みも少なく加工できた。この平面研削後のウエーハの平坦度（ＴＴＶ）はおよそ０．６μｍであった。
【０１２４】
次に、エッチング工程として、初めにアルカリエッチングは、エッチング代目標を両面で１５μｍとし、上記ウエーハを濃度５０重量％のＮａＯＨ水溶液に８５℃で浸漬しエッチングを行った。次に親水化処理として０．３％の過酸化水素水に浸漬した後、５０重量％フッ酸：７０重量％硝酸：８５重量％リン酸＝１：３：２（容量比）からなる混酸でエッチング代目標を両面で５μｍとして液温２５℃で酸エッチングを行った。
【０１２５】
次にウエーハ裏面を研磨した。
研磨条件は、研磨装置：枚葉式研磨装置、研磨布：不織布タイプ研磨布、研磨剤：コロイダルシリカ研磨剤（ｐＨ＝１０．５）を用いて研磨した。研磨代は０．１μｍで行なった。
なお、この研磨代は光沢度によっては０．０５〜０．３μｍ程度とすることもできる。
【０１２６】
次に、ウエーハ外周部の面取り部分を鏡面研磨した。
このような工程を終了したウエーハの表面を鏡面研磨した。研磨は複数段（一次研磨、２次研磨、仕上げ研磨の３段）で行なった。表面側全体の研磨代は目標３μｍとした。主な研磨条件は、研磨装置：枚葉式研磨装置、研磨布：不織布タイプ研磨布、研磨剤：コロイダルシリカ研磨剤（ｐＨ＝１０．５）を用いて研磨した。
【０１２７】
研磨したウエーハについて、ＴＴＶおよびＳＦＱＲ_ｍａｘ、裏面光沢度、外観検査及びナノトポグラフィの確認を行った。
【０１２８】
ＴＴＶ及びＳＦＱＲの測定は、ＡＤＥ社製フラットネス測定器（Ｕ／Ｇ９５００、Ｕ／Ｓ９６００）を用いた。ＳＦＱＲの測定は、ＡＤＥ社製フラットネス測定器を用い、サイトの大きさを２０ｍｍ×２０ｍｍのエリアで評価した。
【０１２９】
外観検査については、ピットの有無を顕微鏡で観察した。
ピットが観察された場合、ピット深さを確認した。ピット深さは光学顕微鏡の焦点深度により求めた。またウエーハ裏面について目視によりステイン等の発生を確認した。
【０１３０】
光沢度は、JIS Z 8741（鏡面光沢度測定方法）を参考にし、同規格で指定の鏡面光沢度計（グロスメーターＳＤ）を使用、同法に準じた方法により測定した。
【０１３１】
ナノトポグラフィー（ナノトポロジーとも言われる）は、波長が０．１ｍｍから２０ｍｍ程度で振幅が数ｎｍから１００ｎｍ程度の凹凸のことであり、その評価法としては１辺が０．１ｍｍから１０ｍｍ程度の正方形、または直径が０．１ｍｍから１０ｍｍ程度の円形のブロック範囲（この範囲はWINDOW SIZE等と呼ばれる）の領域で、ウエーハ表面の凹凸の高低差（P-V値；peak to valley）を評価する。このP-V値はNanotopography Height等とも呼ばれる。ナノトポグラフィーとしては、特に評価したウエーハ面内に存在する凹凸の最大値が小さいことが望まれている。本実施例では１０ｍｍの正方形で複数のブロック範囲を評価し、そのＰＶ値の最大値で評価した。結果を表８に示す。
【０１３２】
【表８】

【０１３３】
上記の結果から分かるように、実施例３では研磨代４μｍ以下の研磨で、高平坦度であり外観異常（研削条痕やピット及び裏面のブルーステイン）のないウエーハが製造できた。特にナノトポグラフィーレベルの微小な凹凸も改善され、好ましい事がわかる。
【０１３４】
これはエッチング、特にアルカリエッチングの前に平面研削を実施し、さらにエッチング工程でアルカリエッチングの後に、リン酸を含む混酸のエッチングをしたこと、及び裏面を研磨したことにより達成することができたものである。またウエーハ裏面の状態もステイン等は見られず、光沢度も適当な値に制御され良好であった。
【０１３５】
（比較例３）
図３に示すような工程で鏡面ウエーハを製造した。実施例３と同様に、直径２００ｍｍ、抵抗率０．０２Ω・ｃｍの単結晶棒（インゴット）をワイヤーソーによりスライスし、１次面取りを行なった後、ラップスラリー（ラップ砥粒番手＃１２００）を使用し、両面で４０μｍラッピングした。次にラップスラリーのラップ砥粒番手＃１５００に切り替え、更に両面で２０μｍラッピングを行なった。
【０１３６】
次にエッチング処理を行った。エッチングは、アルカリエッチングおよびフッ酸、硝酸、酢酸系の混酸を用いた酸エッチングの２段で行った。
アルカリエッチングは、エッチング代目標を両面で２０μｍとし、上記ウエーハを濃度５０重量％のＮａＯＨ水溶液に８５℃で４５０秒間浸漬しエッチングを行った。次に親水化処理として０．３％の過酸化水素水に浸漬した後、５０重量％フッ酸：７０重量％硝酸：１００重量％酢酸＝１：２：１（容量比）からなる混酸でエッチング代目標を両面で１０μｍとして液温２５℃で酸エッチングを行った。
【０１３７】
このような工程を終了したウエーハの表面を実施例３と同様に鏡面研磨した。研磨は複数段（一次研磨、２次研磨、仕上げ研磨の３段）で行なった。全体の研磨代は目標３μｍとした。主な研磨条件は、研磨装置：枚葉式研磨装置、研磨布：不織布タイプ研磨布、研磨剤：コロイダルシリカ研磨剤（ｐＨ＝１０．５）を用いて研磨した。
【０１３８】
研磨したウエーハについて、実施例３と同様にＴＴＶおよびＳＦＱＲ_ｍａｘ、裏面光沢度、外観検査及びナノトポグラフィの確認を行った。結果を表８に併記した。
上記の結果から分かるように、ＴＴＶ、ＳＦＱＲ_ｍａｘおよびナノトポグラフィーとも実施例３よりも劣った値となっている。また、抵抗率の小さいこのウエーハではステインが見られた。
【０１３９】
なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。
【０１４０】
例えば、上記実施例より平坦度の高いラップウエーハを用い、エッチングすれば、上記実施例の平坦度より良いものが製造できる。つまり本発明でエッチングによる平坦度の悪化は少なくできるものの、ＴＴＶの絶対値はラップウエーハの品質にも影響されるものである。
【０１４１】
また、ピット深さについても、ラップ時に使用されるラップ砥粒の番手にも若干影響される。通常、ラッピング工程では＃１２００程度のラップ砥粒が用いられるが、＃１５００のラップ砥粒の使用により、さらにピット深さは改善できる。
【０１４２】
また、本実施例では、高平坦度なウエーハが得られる条件として、アルカリエッチングで両面で約２０μｍ、酸エッチングで両面で約１０μｍのエッチング代でエッチングすることを例示したが、エッチング代はこれに限らず、ラッピング後のウエーハの状態等により、アルカリエッチングの割合をもっと低くしてもよいし、全体的なエッチング代を少なくすることも可能である。要望されるウエーハ品質に応じ、アルカリエッチングおよび酸エッチングの割合を調節することで、高平坦度でありピット深さの浅いウエーハが製造できる。
【０１４３】
さらに例えば本実施例では、主に片面のみを高度に鏡面化したウエーハの製造について述べたが、本発明はこれに限らず、両面を高度に鏡面化したウエーハの製造にも適応できる。アルカリエッチング、リン酸含有酸エッチングにより得られたＣＷは、表裏両面ともピット深さは改善されているため、両面を研磨する場合にも研磨代は少なくすることができ、片面と同じく高平坦度を有するウエーハに加工することができる。
【０１４４】
特に、図１（ａ）に示すようなラッピング工程を省略した工程で行うのが好ましく、平面研削工程で両頭研削装置を用い両面を研削すればよい。その後アルカリエッチング、リン酸含有酸エッチングしたウェーハは、表裏両面ともピット深さは改善されているため、両面を研磨する場合にも研磨代は少なくすることができ、片面と同じく高平坦度を有するウエーハに加工することができる。
【０１４５】
また例えば、上記実施形態においては、直径２００ｍｍ（８インチ）のシリコンウエーハを製造する場合につき例を挙げて説明したが、本発明はこれには限定されず、直径４〜１６インチあるいはそれ以上のシリコン単結晶にも適用できる。
【０１４６】
【発明の効果】
以上説明したように、本発明によれば、アルカリエッチング後にリン酸系混酸を用いることで、リン酸添加による高粘度化効果により、アルカリエッチ面特有の深いピット部分のエッチングが抑制され、平滑な面が得られ、鏡面研磨代を削減でき、研磨工程の生産性が向上する。またうねりが改善され、鏡面研磨後の平坦度が大幅に向上する。さらに鏡面研磨での取り代を減少できるので、研磨工程での平坦度の劣化も抑えられ高平坦度のウエーハを容易に製造することができる。
【０１４７】
さらにウエーハの平坦度を維持しつつ、機械的加工歪み層を除去し、表面粗さを改善し、特に発生するピットの深さをより浅くし、滑らかな凹凸形状の化学エッチングウエーハを作製し、鏡面研磨工程における研磨代を表面全体で４μｍ位まで減少させた半導体ウエーハの製造方法と加工された半導体ウエーハを提供することができる。従って鏡面研磨の生産性とウエーハ平坦度の向上が可能となり、鏡面研磨工程のコストダウンと品質の向上を図ることができる。
またウエーハ裏面の光沢度やブルーステインとよばれる表面の汚れを防止することができる。
【図面の簡単な説明】
【図１】単結晶棒から半導体鏡面ウエーハを加工して製造する工程を示したフロー図である。
（ａ）本発明の製造工程の例を示したフロー図である。
（ｂ）本発明の別の製造工程を示したフロー図である。
【図２】本発明の裏面研磨工程を有する半導体ウエーハの加工方法を示したフロー図である。
【図３】従来の製造工程の例を示したフロー図である。[0001]
BACKGROUND OF THE INVENTION
The present invention provides an improvement in a method for removing a work-affected layer on a wafer surface by chemical etching, which occurs in a manufacturing process of a semiconductor wafer, particularly a single crystal silicon wafer, and an improvement in a wafer back surface condition generated in a manufacturing method of a single crystal silicon wafer. About.
[0002]
[Prior art]
Conventionally, the manufacturing process of a semiconductor mirror wafer is usually composed of a process of slicing a single crystal rod such as silicon and at least chamfering, lapping, etching, mirror polishing, cleaning and drying of the obtained semiconductor wafer. An example of a manufacturing process of such a semiconductor mirror wafer is shown in FIG. Depending on the purpose, some of these steps are replaced, repeated a plurality of times, or other steps such as heat treatment and grinding are added or replaced to perform various steps. For example, the polishing process may be performed in about three stages, or a surface grinding process may be added before the polishing process.
[0003]
Usually, the etching is performed for the purpose of removing a surface-processed deteriorated layer introduced during mechanical processing such as slicing, chamfering, and lapping, and an etching process is performed after a flattening process such as a lapping process. For example, an acid etching process in which etching is performed from the wafer surface to several to several tens of μm with a mixed acid aqueous solution including hydrofluoric acid, nitric acid, acetic acid, and water is common.
[0004]
According to the acid etching, the work-affected layer is removed, but the flatness of the wafer is easily damaged as the etching cost increases. In particular, the peripheral portion of the wafer has a larger etching amount than other portions, and the flatness is remarkably deteriorated. Also, harmful NO due to chemical reaction during acid etching _X There are also problems such as the occurrence of
[0005]
In order to avoid these problems, alkali etching is sometimes used. However, when etching is performed using an alkaline etching solution as an etching solution, the flatness after lapping is maintained as it is, but the depth is locally several μm on the wafer surface and the size is several to dozens. μm pits are easily formed. This is considered to be because a portion having a large local mechanical deformation generated in the lapping process is etched deeper than the other portion due to the anisotropy of alkali etching, and pits are formed.
[0006]
As described above, in acid etching, the flatness of the wafer deteriorates due to etching, and in alkaline etching, deep pits are formed. Therefore, in order to remove these, it is necessary to increase the polishing allowance for mirror polishing. . However, by increasing the polishing allowance, the flatness may be deteriorated by polishing, and the productivity of the polishing process is greatly reduced.
[0007]
Therefore, the applicant of the present application shall perform acid etching after alkali etching as disclosed in Japanese Patent Application Laid-Open No. 11-233485. In order to obtain a polished wafer (Polished Wafer, PW), although the solution was made by making it larger than the etching allowance of acid etching with a mixed acid solution of acetic acid and water, flattening could be achieved sufficiently. Reduction of the polishing allowance was not always sufficient. In recent years, since higher flatness is also demanded, it is more important to reduce the polishing allowance.
[0008]
For this reason, a technique has been considered in which the (planar) grinding step is performed immediately before the polishing step, and the wafer surface is then polished to reduce the polishing time and prevent the peripheral sag. However, it is difficult to control grinding residue and grinding damage due to grinding, and it is difficult to reduce the grinding damage to 3 μm or less.
[0009]
Further, in the wafer processing step, lowering of wafer back surface brightness (glossiness) and waviness (surface roughness with a period of 2 mm or more), and blue stain (hereinafter sometimes simply referred to as “stain”) that is likely to occur in a low resistivity crystal. It became clear that the so-called stains were likely to occur. In particular, depending on the conditions of the etching process (for example, when the etching allowance is reduced), the glossiness of the back surface of the wafer may be reduced to about 15 to 20%.
[0010]
The glossiness of the wafer (back surface) as used in the present invention refers to JIS Z 8741 (Specular Gloss Measurement Method) and uses a specular gloss meter (Gloss Meter SD) specified by the same standard. It was measured by the method. That is, the brightness in the state where nothing is placed at the objective position is assumed to be 0% for convenience, and the evaluation is performed under the setting condition where the glossiness of the mirror-finished wafer is 100%.
[0011]
Conventionally, both the front and back sides of the wafer were mirror-polished, but when the back side is completely mirror-finished (when the gloss level is close to 100%), particles are likely to adhere and re-detach and adsorb wafers. There is a problem such as a contact area of the electrostatic chuck or the like, and it is necessary to reduce the glossiness to a certain range. Although it depends on the device process and the like, generally a glossiness of about 30 to 60% is preferable.
[0012]
Usually, the glossiness of the backside of the wafer is mainly determined in the etching process. In order to obtain a wafer with high flatness, it is preferable to reduce the etching allowance in the etching process. In the method of acid etching after the alkali etching, it is preferable that the etching cost for conventional alkali etching is 10 to 30 μm on both sides, particularly 20 μm, and the etching cost for acid etching is 5 to 20 μm on both sides, particularly about 10 μm. The entire etching process had an etching allowance of about 30 to 40 μm on both sides. As a result, the glossiness can be adjusted to about 40%. However, if the etching allowance is further reduced, the glossiness is lowered to 20% or less, which may be a problem. Therefore, when a semiconductor wafer processing method in which acid etching is performed after alkali etching is performed, the quality on the back surface side may become a problem.
[0013]
[Problems to be solved by the invention]
Therefore, the present invention has been made in view of such a problem, and while maintaining the flatness of the wafer, the mechanically processed strain layer is removed, the surface roughness is improved, and a particularly deep local pit is further increased. A chemically etched wafer (CW) with a shallow, smooth rugged shape and an etched surface that is less prone to particles and contamination can be made to reduce the polishing allowance in the mirror polishing process, and the back side of the wafer. The main object is to provide a semiconductor wafer processing method and a processed semiconductor wafer that improve the quality (glossiness, waviness, stain) of the semiconductor wafer.
[0014]
[Means for Solving the Problems]
In order to solve the above problems, the invention of a semiconductor wafer processing method according to the present invention is a semiconductor wafer processing in which a semiconductor wafer obtained by slicing a single crystal rod is subjected to at least a chamfering process, a lapping process, an etching process, and a mirror polishing process. The method is characterized in that the etching step is an acid etching after an alkali etching, and the acid etching is performed with an acid etching solution comprising hydrofluoric acid, nitric acid, phosphoric acid, and water. ).
[0015]
Thus, in the etching process, alkali etching is first performed on the lapped wafer, the mechanically processed strained layer is removed while maintaining flatness after lapping, and then acid etching is performed. It is possible to improve the local deep pits, the surface roughness, and the sharp uneven shape.
[0016]
At that time, if acid etching is performed with an acid etching solution composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, it will bend more than the conventionally used hydrofluoric acid, nitric acid, and acetic acid based acid etching solutions (surface roughness with a period of 2 mm or more). And the pit depth can be reduced. Therefore, the polishing allowance in the polishing process can be reduced, and the productivity of the polishing process can be improved. Furthermore, by reducing the polishing allowance, deterioration of flatness in the polishing process is suppressed, and the manufacture of a wafer having high flatness becomes even easier. This is considered to be due to the viscosity of phosphoric acid, which makes it difficult for the mixed acid chemicals to enter the pits, and makes the etching rate in the pits slower than other planes.
[0017]
The present invention also relates to a semiconductor wafer processing method in which a semiconductor wafer obtained by slicing a single crystal rod is subjected to at least a chamfering process, a surface grinding process, an etching process, and a mirror polishing process, wherein the surface grinding process is an etching process. The etching step is performed earlier, and the acid etching is performed after the alkali etching. In this case, the acid etching is performed with an acid etching solution including hydrofluoric acid, nitric acid, phosphoric acid, and water ( Claim 2).
[0018]
In this case, it is preferable that in the semiconductor manufacturing method, a lapping process is further added, and processing is performed in the order of the lapping process, the surface grinding process, and the etching process.
[0019]
As described above, in the present invention, instead of the conventional lapping process, the surface grinding process is completely replaced, or the lapping process is added and the surface grinding process is performed before the etching process, so that it is locally generated by lapping. It is possible to remarkably reduce the large mechanically processed strain layer, which can suppress the generation of deep pits.
[0020]
In the surface grinding step, the wafer shape can be controlled relatively easily compared to the lapping step, and the same shape can be obtained stably. Furthermore, variations in thickness between wafers can be suppressed.
[0021]
Surface grinding can also remove pits that remain even if the lapped wafer is etched. Therefore, it is conceivable to perform a surface grinding process after the etching process, but in surface grinding, a pattern called a grinding streak remains on the wafer surface. It has been found that in order to eliminate the grinding streak, it is necessary to increase the polishing allowance in the polishing process, which deteriorates the flatness of the wafer. Therefore, in the present invention, the surface grinding process is performed before the etching process. In particular, in a process incorporating a lapping process, it is preferable to perform the processes in the order of a lapping process, a surface grinding process, and an etching process.
[0022]
The chamfering process is preferably performed after the surface grinding process. Moreover, when there exists a lapping process, it is preferable to put in the front | former stage of a lapping process. This is because, when a lapping slurry is used in the lapping process but the wafer is not chamfered, the lapping slurry is difficult to enter the center of the wafer, and the outer periphery of the wafer may be drooped extremely. Moreover, when there exists a lapping process and a surface grinding process, it is more preferable if a chamfering process is put in multiple places (at least 2 places). That is, the chamfering process is not particularly limited, and it may be inserted between the optimal processes depending on the purpose, and the chamfering process may be replaced or added to a plurality of locations.
[0023]
Further, in the surface grinding process, both the front and back surfaces of the wafer may be ground, or only the front surface (when one surface is mirror-polished, the polishing surface side in the polishing process) may be ground on one side. In particular, when the lapping step is performed before the surface grinding step, single-side grinding is preferable in which only the polishing surface to be polished in the polishing step is ground. This is because the back surface (unground surface) of the final mirror-finished wafer after polishing is in a state of light selectivity and roughness similar to the back surface of the wafer used conventionally.
[0024]
When the final mirror surface wafer is a double-sided mirror surface wafer, it is preferable to perform double-side grinding in a surface grinding process. In this case, the wrapping process is not necessarily required. Eliminating the lapping step is preferable because the number of steps is reduced and the polishing allowance can be reduced on both the front and back sides of the wafer in the polishing step. That is, the surface to be polished in the polishing process is surface ground. However, if the back surface shape of the final polished wafer is not particularly specified, a wafer with high flatness can be obtained by performing double-side grinding in the surface grinding process and single-side polishing in the polishing process.
[0025]
Next, in the present invention, the grinding striations generated in the surface grinding process must be removed in the etching process performed after the surface grinding process. This grinding streak is also a kind of mechanically processed strained layer and is considered to have a strain of about 6 μm. Therefore, if the wafer subjected to the surface grinding is subjected to alkali etching, local deep pits appearing when the alkali etching is performed after the lapping process can be prevented, but the surface of the grinding streaks subjected to the surface grinding remains or remains. Sometimes it was emphasized and became a pit.
[0026]
Therefore, in order to prevent such pits caused by grinding streaks from occurring in the etching process, alkali etching and acid etching were combined to remove distortion while maintaining the flatness of the wafer. That is, in the etching process, first, alkali etching is performed, and then acid etching is performed. In this way, in the etching process, first, alkali etching is performed on the wafer after surface grinding, the mechanically processed strain layer is removed while maintaining flatness after surface grinding, and then acid etching is performed. Grinding marks, surface roughness, and sharp irregularities remaining after alkali etching can be improved while maintaining flatness. At this time, it is preferable that the etching allowance for alkali etching is larger than the etching allowance for acid etching.
[0027]
At this time, if acid etching is performed using an acid etching solution composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, the acid etching using a conventional acid etching solution of hydrofluoric acid, nitric acid, and acetic acid is generally used. Furthermore, the undulation is further reduced, and the pits caused by the grinding striations can be made shallower. Accordingly, the polishing allowance in the subsequent polishing process can be reduced, and the productivity of the polishing process can be improved. Further, by reducing the polishing allowance, the deterioration of the flatness of the wafer in the polishing process is suppressed, and the production of a wafer having a high flatness becomes even easier.
[0028]
Further, the present invention provides a semiconductor wafer processing method in which a semiconductor wafer obtained by slicing a single crystal rod is subjected to at least a flattening step, an etching step, and a mirror polishing step. In the etching process, acid etching is performed after alkali etching. At that time, acid etching is performed with an acid etching solution composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, and the mirror polishing process is back-surface polishing after the acid etching. A method for processing a semiconductor wafer, comprising performing a step and then performing a surface polishing step.
[0029]
As described above, in the mirror polishing step, after the acid etching, the back surface polishing step is performed, and then the surface polishing step is performed, so that the quality (glossiness, waviness, stain) of the wafer back surface can be improved. . In addition, by introducing a backside polishing process before polishing the front surface, the transfer of back surface waviness is reduced on the wafer surface, and the polishing allowance for the surface polishing can be further reduced. This also has the advantage that a wafer with high flatness can be obtained. Further, since the polishing allowance can be reduced, the productivity of the polishing process can be remarkably improved.
[0030]
In this case, the flattening step can be a lapping step and / or a surface grinding step.
Thus, in the processing method of the present invention, the flattening step can be a lapping step and / or a surface grinding step, and the wafer shape and flatness are maintained and ground in the subsequent etching step and mirror polishing step. Since the streak is efficiently removed, the wafer can be processed into a wafer having high flatness and improved surface roughness and unevenness.
[0031]
In this case, the back surface polishing step is preferably polished so that the glossiness is 35 to 50%.
Thus, if it grind | polishes so that it may become 35 to 50% of glossiness, a particle will not generate | occur | produce and the contact area for the electrostatic chuck etc. which adsorb | suck a wafer will not be a problem.
[0032]
Furthermore, in the surface grinding process, it is desirable to perform grinding so that the thickness of the outer peripheral portion of the wafer is increased.
Surface grinding can process a wafer with high flatness, but in order to make the polished wafer more flat, the outer periphery (about 5 mm from the periphery) is about 0.06 μm for the polishing allowance of 1 μm during polishing. It is preferable to prepare a thick wafer. This is because the peripheral portion of the wafer tends to be thinner in the etching process and the polishing process, which are processes after the surface grinding process. In the surface grinding process, the outer peripheral portion can be controlled to have a thick shape and can be stably manufactured. As a result, a wafer with high flatness can be obtained after polishing. Also, variations in thickness between wafers can be suppressed.
[0033]
In this case, it is preferable that the total etching allowance in the etching step is 30 μm or less on both sides.
Thus, a wafer with high flatness can be obtained by making the etching allowance 30 μm or less on both sides. In particular, it is possible to prevent the wafer from sagging due to etching.
[0034]
Moreover, in this invention, the grinding | polishing allowance in a mirror polishing process can be 7 micrometers or less (Claim 9).
In the mirror polishing process of the present invention, a wafer having a small undulation and a very shallow pit is obtained in the above etching process, so that the polishing allowance can be extremely reduced to 7 μm or less, and a highly flat mirror wafer. And the productivity of the polishing process can be significantly improved.
In this case, in order to obtain a good polished surface, the polishing allowance is preferably 2 μm or more.
[0035]
In the etching of the present invention, the composition ratio when the acid etching solution is prepared is preferably such that the hydrofluoric acid concentration is 5 to 15% by weight and the phosphoric acid concentration is 10 to 40% by weight.
Thus, in order to reduce the polishing allowance, in order to reduce the depth of the pit generated by lapping or alkali etching after grinding, the hydrofluoric acid concentration at the time of preparation of the acid etching solution (initial concentration) is 5 to 15% by weight. Below, it is preferable that phosphoric acid concentration exists in the range of 10 to 40 weight%. Under this condition, the viscosity of the etching solution becomes appropriate, the effect of reducing the depth of the pit is high, and there is little influence of side reaction in which phosphoric acid and hydrofluoric acid react, and stable silicon surface etching can be performed. it can.
[0036]
In this case, the acid etching solution is preferably a solution in which silicon is dissolved at a concentration of 10 g / L or more.
When the amount of silicon dissolved is set to be large in this way, the amount of liquid exchange can be reduced to obtain the original liquid state. As a result, the concentration control of the etching solution becomes easy and the acid etching state can be stabilized. In addition, the quality such as swell can be improved.
[0037]
In this case, the composition ratio when the acid etching solution is used is preferably such that the hydrofluoric acid concentration is 1 to 7% by weight and the phosphoric acid concentration is 18 to 33% by weight.
The initial concentration (concentration at the time of preparation) is preferably within the above concentration range, but the composition ratio (concentration at the time of use) when actually etching the wafer is 1 to 7% by weight of hydrofluoric acid concentration and 18 to 18% phosphoric acid concentration. It is preferably 33% by weight. When etching is performed in such a range, the pit becomes shallow and a wafer having a good surface condition can be obtained. The hydrofluoric acid gradually decreases as the etching process is repeated, but when the hydrofluoric acid concentration is 1% by weight or less, the etching effect becomes too small. When the concentration is out of the above range, a stable treatment can be performed by performing etching while replacing part or all of the chemical solution.
[0038]
The alkaline etching solution for alkaline etching in the present invention is preferably an aqueous NaOH solution or an aqueous KOH solution.
With such an etching solution, the effect of the etching treatment is more reliably exhibited, the wafer has a high flatness, the etching cost can be controlled relatively easily, and the adjustment can be made at low cost.
[0039]
Next, the semiconductor wafer processed by the method of the present invention (Claim 14) is subjected to alkali etching to remove the mechanically processed strain layer while maintaining the flatness after lapping or grinding, and then containing phosphoric acid. By performing acid etching, the etching of deep pits peculiar to an alkali etching surface is suppressed, and the semiconductor wafer is improved in surface roughness and sharp concavo-convex shape. In particular, the pit depth and waviness are improved, resulting in a flatter semiconductor wafer. Furthermore, a semiconductor wafer having good quality (glossiness, waviness, stain) on the back surface of the wafer can be obtained.
[0040]
Further, the semiconductor wafer according to the present invention is a chemically etched semiconductor wafer (CW) having a maximum pit depth of 4 μm or less, a waviness of 0.05 μm or less, and a glossiness of 20 to 70%. (Claim 15).
Thus, according to the present invention, a chemically etched semiconductor wafer having an extremely small pit depth can be manufactured.
[0041]
Further, by performing mirror polishing of 7 μm or less using the CW, a semiconductor wafer (PW) whose surface is mirror-polished has a SFQRmax of 0.1 μm or less and the other mirror-polished surface has a pit depth. A semiconductor wafer having a maximum thickness of 4 μm or less, a waviness of 0.05 μm or less, and a glossiness of 20 to 70% can be provided.
Since the CW pit depth can be reduced, the polishing allowance can be remarkably reduced when the surface of the wafer is polished. As the polishing allowance increases, flatness deterioration (especially sagging around the wafer) tends to occur, but this can be prevented by reducing the polishing allowance, and the SFQRmax is also extremely high flatness of 0.1 μm or less. It was possible to be a wafer. Further, the glossiness of the back surface of the wafer can be controlled in the same manner as in the conventional wafer.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to tables and drawings, but the present invention is not limited thereto.
[0043]
The inventors of the present invention, as a result of various investigations on a semiconductor wafer processing method, particularly an etching method, for producing a chemical etching wafer having an etching surface in which particles and contamination hardly occur, while maintaining the flatness after lapping of the wafer, First, alkali etching is performed to remove the strained layer while maintaining flatness after lapping, and acid etching is used to improve the remaining deep pits, surface roughness or waviness, and particularly hydrofluoric acid which has been conventionally used. Acid etching using a mixed aqueous solution of hydrofluoric acid, nitric acid and phosphoric acid (sometimes called a phosphoric acid-based mixed acid) instead of a mixed aqueous solution of nitric acid and acetic acid (sometimes called an acetic acid-based mixed acid). The present invention was completed by investigating the processing conditions.
[0044]
First, as a basic processing condition for alkali etching, for example, an 8-inch (200 mm) diameter wafer may be lapped with # 1200 lapping abrasive grains and then subjected to alkali etching at 85 ° C. and a 50% concentration NaOH aqueous solution. And as an etching allowance of alkali etching, 10-30 micrometers is a suitable range on both surfaces. In particular, as a condition that the local deep pit depth is close to the minimum value and TTV and Ra do not deteriorate so much, about 20 μm is preferable.
[0045]
Here, the local deep pit is a pit formed by lapping abrasive grains piercing the wafer surface at the time of lapping, and its size and depth are increased by alkali etching. Therefore, it slightly affects the count of lapping abrasive grains used during lapping. In addition, when the alkali concentration is low, the pit depth tends to increase. On the other hand, when the alkali concentration is high, the pit depth can be reduced, but to that end, it is necessary to increase the etching allowance. There is poor efficiency. The depth of the pits is determined by the depth of focus of the optical microscope. In order to remove the pits, it is necessary to polish in a mirror polishing process that is a subsequent process. Therefore, since the mirror polishing amount needs to be equal to or greater than the maximum value of such deep pit depth, it is desirable to make the pits as shallow as possible.
[0046]
Here, TTV [Total Thickness Variation] (μm) is a numerical value indicating a difference in thickness between the thickest portion and the thinnest portion of one wafer, and is an index of the flatness of the wafer.
Ra (μm) is called centerline average roughness and is one of the most commonly used surface roughness parameters.
[0047]
Next, the composition of the acid etching solution was investigated and examined.
Instead of the acetic acid-based mixed acid composed of hydrofluoric acid, nitric acid, and acetic acid, the phosphoric acid-based mixed acid composed of hydrofluoric acid, nitric acid, and phosphoric acid was examined.
That is, the acid etching solution is mainly composed of hydrofluoric acid and nitric acid capable of improving the surface roughness, and the liquid mixed therewith is usually phosphoric acid where acetic acid is used. The reason for this is that phosphoric acid is stable even in strong acids, and after entering the pits due to the viscosity of phosphoric acid, the supply of new solution is cut off and etching in the pits is performed on other planes. It was because it was thought that it could be made later than that, and the tendency could be grasped qualitatively.
[0048]
Then, the preparation ratio of hydrofluoric acid, nitric acid, and phosphoric acid was examined.
Table 1 shows that an 8 inch diameter wafer was lapped by 60 μm on both sides using a lapping abrasive grain count # 1200 to improve the flatness and remove a mechanically altered layer by slicing, and then a 20 μm alkali etched wafer on both sides (hereinafter referred to as the following) Of the wafer to be processed) with a mixed acid aqueous solution of hydrofluoric acid, nitric acid, phosphoric acid, and water, the mixing ratio of the acid, and the local deep pit depth and surface condition of the acid-etched wafer It is an observation result.
Test numbers 1 to 13 are when the mixing ratio of hydrofluoric acid, nitric acid, and phosphoric acid is changed, and test numbers 14 and 15 are cases of a conventional mixed aqueous solution of hydrofluoric acid, nitric acid, and acetic acid.
After 11 g / L of silicon was dissolved in these etching solutions to stabilize the etching solution, the processed wafer was etched by 10 μm on both sides, and the pit depth and the surface state were evaluated.
[0049]
[Table 1]

[0050]
From the results of this test, it can be seen that the pit depth can be greatly improved by changing the acetic acid to phosphoric acid. In particular, the pit depth of about 7 μm with acetic acid was changed to phosphoric acid. It became about 3-4 micrometers. Moreover, it is thought that a pit is so small that phosphoric acid concentration (weight%) is high.
[0051]
As described above, it can be seen that the effect of phosphoric acid is great for the pit depth.
As for the surface state, as in Test Nos. 9, 11, and 12, when the hydrofluoric acid concentration (% by weight) was higher than the concentration of nitric acid, the surface became rugged and the surface became cloudy and the glossiness decreased. . If the hydrofluoric acid is too concentrated or the nitric acid is too thin, the surface condition will deteriorate. Therefore, it is preferable to etch in a state where the hydrofluoric acid concentration is lower than that of nitric acid. Moreover, when the hydrofluoric acid concentration is much lower than the nitric acid concentration as in test number 1, etching is not performed (almost does not react). Therefore, the (hydrofluoric acid / nitric acid) ratio is preferably 1/7 or more. In such a state where the etching is not performed (almost does not react), the surface of the wafer is the original alkaline etching surface state, and deep pits and a rough surface remain. If the etching is continued, the pits become small, but the etching time becomes very long, which is an operational problem. Etching may be slow even when the phosphoric acid concentration is 40% by weight or more. This is thought to be because etching does not proceed due to the side reaction between hydrofluoric acid and phosphoric acid.
[0052]
Taking the above into consideration, a wafer having a very good surface condition can be obtained especially when the ratio of (hydrofluoric acid / nitric acid) is about 1/2 and the phosphoric acid concentration is 40% by weight or less. The glossiness could be adjusted over a wide range of 20 to 70% by adjusting the etching time.
[0053]
Here, the surface state in Table 1 is a state in which a visual appearance inspection is performed, the surface becomes rugged, the glossiness decreases, and the surface state of alkali etching remains, and the surface state is used as it is. △ (slightly difficult) was assigned. When the surface state of the alkali etching remains, the surface state can be improved by increasing the etching time, but it is difficult in operation. Even if the surface is rough, the pit depth is small, so it can be used as a raw material wafer when polishing both surfaces of the wafer. The surface was etched and the glossiness was good, but a case where a slightly mottled pattern remained was marked as ◯ (good). These can be used without any particular problem. Further, the glossiness is improved, and it is equivalent to the conventional acetic acid mixed acid and can be adjusted within the glossiness range required for the product. Further, the pit depth is a value obtained by scanning the wafer surface and obtaining the focal depth of the optical microscope at a portion where the pit is present, and indicates the maximum value of the obtained pit depth.
[0054]
From these pit depths and surface conditions, a preferable concentration range of the phosphoric acid-based mixed acid is 5 to 15% by weight of hydrofluoric acid (HF) and nitric acid (HNO) as an initial concentration at the time of preparation. _Three ) Is 20 to 45% by weight, phosphoric acid (H _Three PO _Four ) Is 10 to 40% by weight, remaining water (H ₂ O) degree.
[0055]
This is because the etching effect (reactivity) deteriorates when the hydrofluoric acid concentration at the time of preparation is 5 wt% or less. On the other hand, if it is 15% by weight or more, the surface condition becomes worse due to the relationship with nitric acid. Regarding nitric acid, although no clear knowledge has been obtained, it is considered that the range of 20 to 45% by weight is preferable from the relationship with hydrofluoric acid and phosphoric acid. Especially (HF / HNO _Three The ratio is preferably 1 / (2-7). When phosphoric acid is less than 10% by weight, the effect of improving the pit is reduced, and when it is 40% by weight or more, side reaction with hydrofluoric acid or water increases, etching becomes unstable, and finally the etching effect is lost. And the surface condition may be deteriorated.
[0056]
The appropriate etching allowance for acid etching is 5 to 20 μm on both sides. In particular, about 10 μm on both sides makes the pit shallow, and the surface can be smoothly etched while maintaining the flatness. This is thought to be because the mixed acid is less likely to enter the pits due to lapping and pits due to the viscosity of phosphoric acid, and the etching rate in the pits is slower than other planes. .
[0057]
Next, each composition ratio during actual etching was confirmed. The above concentration range is preferable at the time of blending, but actually the composition changes during etching. When the silicon wafer is etched, each composition in the chemical solution has a tendency that the hydrofluoric acid concentration decreases, the nitric acid concentration gradually decreases, the phosphoric acid concentration hardly changes, and the water concentration increases. In particular, the composition is unstable immediately after the start of etching.
[0058]
Therefore, in order to stabilize the etching solution, it is preferable to previously dissolve silicon in the mixed acid. The composition when this silicon was dissolved (the composition when actually used) was confirmed.
Table 2 shows the concentration of each component in the etching solution when the silicon dissolution amount is changed to 0 to 20 g / L. The composition of the etching solution at the time of preparation (initial) was the same as that of Test No. 13 using a phosphoric acid mixed acid prepared by mixing 50% hydrofluoric acid, 70% nitric acid, and 85% phosphoric acid at a volume ratio of 1: 3: 2. This confirms how the actual etching composition changes when silicon is dissolved.
[0059]
In addition, since it was confirmed that the swell and peripheral sag can be greatly improved by this silicon dissolution amount, each etching solution shown in Table 2 was used, lapping was performed with # 1200 lap abrasive grains, and alkali etching of 20 μm was performed on both sides. Wafers were acid etched on both sides to evaluate swell. The results are also shown in Table 2.
[0060]
[Table 2]

[0061]
As can be seen from Table 2, the concentration at the time of preparation (initial concentration) changes by dissolving silicon in advance. In a phosphoric acid-based mixed acid prepared by mixing 50% by weight hydrofluoric acid, 70% by weight nitric acid, and 85% by weight phosphoric acid at a volume ratio of 1: 3: 2, the etching composition at the time of use is approximately 1 to 7% by weight of the hydrofluoric acid concentration. Nitric acid is about 25 to 33% by weight, and phosphoric acid is about 18 to 33% by weight, and it is preferable to use in such a composition range. Further, it is more preferable that silicon dissolution is 10 g / L or more because a very good wafer having a swell of 0.05 μm or less can be produced. As the silicon dissolution amount increases, the swell can be reduced.
[0062]
Here, the waviness is the origin of the height by matching the height of the measurement start point and the measurement end point, and the absolute value Y of the displacement amount from the origin at a pitch of 2 mm. ₁ To Y ₂₉ And the average value Y is defined as waviness.
A universal surface shape measuring instrument (SE-3F type) manufactured by Kosaka Laboratory Ltd. was used as the undulation measuring apparatus. In the measurement method, the central portion 60 mm of the surface of the wafer (diameter 200 mm) is traced with a stylus, and only the shape component excluding the fine surface roughness component is measured.
[0063]
Further, if silicon is dissolved at 10 g / L or more, the etching composition is stabilized. The reactivity of the etching solution immediately after blending is unstable. By dissolving a certain amount of silicon in advance, the reactivity and the composition of the etching solution are stabilized. In order to return the etching composition to the concentration immediately after preparation without dissolving silicon, it is necessary to replace almost all of the etching solution, but it is easy to return to the state after dissolving silicon, and etching without dissolving silicon. It is only necessary to partially replace (add) the liquid, and the liquid replacement amount can be reduced. As a result, the concentration and variation of the etching solution are reduced, the control is facilitated, and the acid etching state can be stabilized.
[0064]
As described above, it was found that the use of a mixed acid containing phosphoric acid for acid etching is superior to the conventional acetic acid-based mixed acid etching in the following points.
That is,
1) The depth of the pit can be made shallower than the conventional alkali etching + acetic acid mixed acid etching.
2) High smoothing efficiency.
3) Less swell component.
4) Surface roughness becomes finer and glossiness increases.
[0065]
Table 3 summarizes and compares the relationship between various etching methods and the quality and characteristics of the obtained wafer. When etching is performed only with a phosphoric acid-based acid solution, the flatness tends to be deteriorated as in the case of etching only with an acetic acid-based acid solution when the etching cost is increased. Also, the etching rate is slow and the productivity is not good. By treating with an (alkali + phosphoric acid) etching solution as in the present invention, the etching cost for the phosphoric acid system is reduced, the above problems can be improved, and the polishing cost for the polishing process can be significantly reduced. preferable. From the above, the superiority of the present invention is clear.
[0066]
[Table 3]

[0067]
If the etching allowance (removal allowance by etching) is too large, the wafer outer peripheral sag is likely to occur even by etching that performs alkali etching and acid etching. Therefore, in the etching process, it is better to reduce the surface allowance to about 10 to 30 μm on both sides from the conventional machining allowance. Preferably, the thickness is about 15 μm on both sides by alkali etching and about 5 μm on both sides by acid etching.
[0068]
According to the above-described two-stage chemical etching of the alkali etching + phosphoric acid mixed acid etching of the present invention, the maximum value of the pit depth is 4 μm or less, the PV value of the waviness of 2 mm pitch is 0.05 μm or less, and the glossiness range A semiconductor wafer having a content of 20 to 70% can be easily and stably manufactured.
[0069]
In addition, the inventors of the present invention have studied the wafer manufacturing method with less processing distortion and pits remaining due to the processing before the mirror polishing process, in particular, the etching process, and various results of the previous process. By incorporating a surface grinding process after the lapping process, the strained layer caused by slicing or lapping is extremely reduced, a wafer that maintains high flatness is obtained, and further, a strained layer that remains by surface grinding after performing alkali etching. In order to remove the grinding streak and improve the pits due to the remaining grinding streak, the idea was to perform acid etching using a mixed aqueous solution of hydrofluoric acid, nitric acid, and phosphoric acid as the acid etching solution, and the processing conditions were investigated. Thus, the present invention has been completed.
[0070]
FIG. 1 is a series of flowcharts for manufacturing a semiconductor mirror wafer by processing the single crystal rod of the present invention. FIG. 1A is a flow chart including the order of the surface grinding process and the etching process, and FIG. 1B is a flowchart including the order of the surface grinding process and the etching process in which the lapping process is added before.
[0071]
FIG. 1 (a) shows a mirror surface wafer manufacturing process in which the lapping process is completely replaced with a surface grinding process. A wafer is obtained by slicing a single crystal rod in a slicing process, and is subjected to surface grinding in a surface grinding process. The mechanically altered layer generated by the improvement of the degree and the slicing process is removed. Next, the wafer is chamfered in a chamfering process, and an etching process is started. For the etching, first, alkali etching is performed to remove or shallow the strained layer and the grinding striation, and then the acid etching is performed with phosphoric acid mixed acid to shallow the grinding striation. At this time, it is preferable that the etching allowance for alkali etching is larger than the etching allowance for acid etching. Subsequently, mirror polishing is performed in the mirror polishing step, and cleaning and drying are performed in the cleaning / drying step, so that a mirror wafer with high flatness can be manufactured.
[0072]
FIG. 1B shows a mirror surface wafer manufacturing process in which a lapping process is added before a surface grinding process, and a wafer is obtained by slicing a single crystal rod in a slicing process, and roughing the wafer in a primary chamfering process. After the processing, lapping is performed in a lapping process, and the mechanically deteriorated layer generated in the improvement of flatness and the slicing process is removed. Subsequently, flatness is further improved by surface grinding in the surface grinding process. Next, finish chamfering is performed in the secondary chamfering process, and the etching process is started. In the etching, first, alkali etching is performed to remove the strained layer and the grinding streak, and then the acid streaking is performed with phosphoric acid mixed acid to make the grinding streak shallow. At this time, it is preferable that the etching allowance for alkali etching is larger than the etching allowance for acid etching. Subsequently, mirror polishing is performed in the mirror polishing step, and cleaning and drying are performed in the cleaning / drying step, so that a high flatness mirror surface wafer can be manufactured.
[0073]
First, as standard conditions for surface grinding, spindle rotation speed: 4000 to 7000 rpm, wafer rotation speed: 5 to 9 rpm (during machining), 3 to 7 rpm (during spark-out), grinding wheel feed speed: 0.1 to 0 .3 μm / sec is preferable.
The grindstone to be used is preferably of a high Young's modulus type, and the surface grinding apparatus is preferably an infeed type surface grinding apparatus in which the grindstone is centered.
As the surface grinding device, there are a double-head grinding device that grinds both surfaces simultaneously, a device that grinds only one surface or only one surface, but the form of the device is not particularly limited.
In order to improve the flatness and remove the mechanically affected layer due to slicing, it is generally sufficient to grind at 40 to 60 μm (20 to 30 μm on one side) on both sides.
[0074]
Here, in the lapping process, local deep damage (pits) has been formed due to the influence of lapping abrasive grains, but surface grinding enables processing with less local mechanical processing distortion.
However, although it is slightly affected by the conditions of the surface grinding process, grinding streaks remain in the surface grinding. The grinding striations are traces of the grindstone remaining on the wafer surface in a streak shape.
[0075]
Therefore, etching as described above is performed. First, alkali etching is performed to remove the strained layer and grinding striations, and then acid etching is performed with phosphoric acid-based mixed acid to shallow the grinding striations. Subsequently, mirror polishing is performed in the mirror polishing step, and cleaning and drying are performed in the cleaning / drying step, so that a high flatness mirror surface wafer can be manufactured.
[0076]
A wafer manufactured by the above-described series of processes has very shallow or completely non-existing pits and has few swell components. The surface roughness becomes finer and the glossiness increases. Therefore, the polishing allowance (removal allowance) in the polishing step can be remarkably reduced, and a wafer with high flatness can be obtained with high productivity.
[0077]
On the other hand, as described above, in the wafer processing step, lowering of wafer backside luminance (glossiness) and waviness, and stains called blue stain (hereinafter sometimes simply referred to as “stain”), which are likely to occur in low resistivity crystals, occur. Sometimes. Depending on the conditions of the etching process (for example, when the etching allowance is reduced), the glossiness of the back surface of the wafer may be reduced to about 15 to 20%.
In order to solve this problem, the present inventors have conceived that in the mirror polishing process, after the acid etching, a back surface polishing process is performed, and then a surface polishing process is performed.
[0078]
The case where the back surface polishing of the present invention is performed will be described below. FIG. 2 is a series of flowcharts illustrating a method for processing a semiconductor wafer having a back surface polishing step of the present invention. In addition to the semiconductor wafer processing method of FIG. 1 described above, this method is characterized in that a back surface polishing step is performed before the surface polishing step of mirror polishing the wafer surface.
[0079]
A conventional method or apparatus may be used in the slicing process. For example, it is preferable to use a wire saw or an inner peripheral slicing device and slice so as to reduce warp. In particular, slicing is performed so that the warp (warp) is 10 μm or less.
[0080]
A conventional method and apparatus may be used for the chamfering process. In an early stage after slicing, it is preferable to perform a beveling process (chamfering process) that rounds the corners of the outer periphery to prevent chipping and cracking, and then a chamfering process that mirrors the chamfered part by the surface polishing process.
In particular, the chamfering process is preferably performed after the surface grinding process. If there is a wrapping step, it is preferably put before the wrapping step. Of course, a plurality of chamfering steps may be included. In this proposal, an example in which a primary chamfering process before lapping, a secondary chamfering after surface grinding, and a mirror chamfering process after back surface polishing is shown.
[0081]
In the flattening process, only the lapping process or only the surface grinding process may be used, but as described above, the surface grinding process has less mechanical distortion, and the wafer shape can be controlled relatively easily compared to the lapping process. The same shape can be obtained stably, which is preferable. A surface grinding process may be added after the lapping process, and processing may be performed in the order of the lapping process, the surface grinding process, and the etching process.
[0082]
In surface grinding, deep pits can be removed. Therefore, a surface grinding process may be performed after the etching process and before the polishing process. However, in surface grinding, a pattern called a grinding streak remains. In addition, the damage caused by grinding remains on the order of several μm. Therefore, it is necessary to increase the polishing allowance in the polishing process in order to eliminate the grinding streak. Therefore, in the present invention, the surface grinding process is performed before the etching process. In particular, in the process in which the lapping process is left as it is, it is preferable to perform the lapping process, the surface grinding process, and the etching process in this order. By doing so, deep pits caused by lapping can be removed, and grinding striations caused by surface grinding can be removed or shallowed.
[0083]
As a condition for the flattening process, in the case of the lapping process, it is preferable to flatten by using lapping abrasive grains of about # 1200 to # 1500. The lapping margin (removal allowance by lapping) may be about 40 to 60 μm on both sides. It is preferable to perform a two-stage wrapping of # 1200 with lapping abrasive grains of 40 μm on both sides and # 1500 and 20 μm on both sides. Thus, it is preferable to use a lapping slurry containing # 1500 and fine abrasive grains in the subsequent stage.
[0084]
When surface grinding is performed following lapping, it is preferable to use an abrasive wheel of about # 1500 to # 4000. The grinding allowance (removal allowance by surface grinding) may be about 10 μm on one side. The grindstone used for the surface grinding is preferably an in-feed type grinder with a high Young's modulus and the grinder is a center cut.
[0085]
When surface grinding is used as the flattening process, for example, grinding marks remain even after a grinding process with little distortion. Grinding streaks are also a kind of mechanically processed strain layer, which is considered to have some strain (damage). Therefore, when this surface-grinded wafer is subjected to alkali etching, local pits appearing when alkali etching is performed after the lapping process can be prevented, but the surface of the grinding striations subjected to surface grinding remains or is emphasized. It may become a pit shape.
[0086]
Conventionally, surface grinding has been performed before polishing in order to obtain a wafer with high flatness. However, this causes problems such as leaving grinding marks. In the present invention, even if surface grinding is performed in the step before surface polishing, etching and polishing can be performed while the shape is maintained, and the grinding streaks can be removed.
[0087]
That is, in the etching process of the present invention, as described above, first, alkali etching is performed in the etching process, and then acid etching is performed. Further, by performing acid etching with hydrofluoric acid, nitric acid, phosphoric acid, and water, the undulation can be reduced and the grinding striations can be made shallower.
[0088]
The back surface polishing step is performed after the acid etching and before the surface polishing step. If only the glossiness of the back surface is adjusted, it can be performed in any step after the etching (for example, it may be performed after the surface polishing step), but after the acid etching and before the surface polishing step. For example, since the surface of the wafer back surface is also improved by the back surface polishing, the influence of the transfer of the back surface shape and the like can be reduced as much as possible, and the unevenness at the nanotopography level is also reduced. The surface can be polished while maintaining a high flatness state. In addition, the wafer back surface can be manufactured not only by adjusting the glossiness of the back surface of the wafer but also by removing blue stain. The back surface glossiness is preferably 35 to 50%. For this, the polishing allowance (removal allowance by polishing) is 0.4 μm or less and 0.05 μm or more, preferably about 0.1 μm to 0.3 μm on one side.
[0089]
The surface polishing step is not particularly limited as long as polishing is performed under conditions that do not cause peripheral sag due to polishing. However, particularly when polishing in a plurality of stages, it is preferable that the polishing allowance is 4 μm or less on the entire surface side. However, it is desirable to polish about 1 μm in order to obtain a good mirror surface.
By suppressing the polishing allowance in this way, a wafer with high flatness can be manufactured while maintaining the flatness of the previous process.
[0090]
In particular, in the surface (mirror surface) polishing step of the present invention, a wafer with very small waviness in the etching step and a very shallow grinding trace (pit due to the grinding trace) is obtained, so the polishing allowance is extremely reduced. And a mirror surface wafer with high flatness can be obtained. In addition, since the back surface polishing step is performed before polishing, transfer of back surface waviness is reduced on the wafer surface, and the polishing allowance for surface polishing can be further reduced. As a result, the unevenness of the nanotopography level is reduced, and the decrease in flatness due to polishing is suppressed, and there is an advantage that a wafer with high flatness can be obtained. Further, since the polishing allowance can be reduced, the productivity of the polishing process can be remarkably improved.
[0091]
【Example】
Hereinafter, although an example and a comparative example of the present invention are given and explained concretely, the present invention is not limited to these.
Example 1
As a result of the above consideration, in consideration of the pit depth, the surface state, the etching rate, the stability of the etching solution, etc., the mixing ratio is 50 wt% hydrofluoric acid: 70 wt% nitric acid: 85 wt% phosphoric acid = 1: 3: 2. Etching solution of HF = 6.6% by weight, HNO _Three = 34.0 wt%, H _Three PO _Four = 32.5 wt%, balance H ₂ It was found that an etching solution with O (26.9% by weight) and silicon dissolution amount = 19 g / L is preferable. Examples using this acid etching solution will be described below.
[0092]
The following etching process was performed using a 200 mm (8 inch) diameter lap wafer (lap abrasive grain count: # 1200). The TTV of this lap wafer was approximately 0.8 μm.
First, the alkali etching was performed by dipping in an aqueous solution of NaOH having a concentration of 50% by weight at 85 ° C. for 450 seconds, with an etching allowance target set to 20 μm on both sides. Next, after being immersed in a 0.3% hydrogen peroxide solution as a hydrophilic treatment, finally, the above-described 50 wt% hydrofluoric acid: 70 wt% nitric acid: 85 wt% phosphoric acid = 1: 3: 2 (volume) Etching was carried out at a liquid temperature of 25 ° C. with a mixed acid consisting of: With respect to the finished etching, the flatness (TTV), surface roughness (Ra), waviness, pit depth, and glossiness were measured to investigate the effect of etching. The results are shown in Table 4.
[0093]
(Comparative Example 1)
The same conditions as in Example 1 except that a mixed acid composed of 50% by weight hydrofluoric acid: 70% by weight nitric acid: 100% by weight acetic acid = 1: 2: 1 (volume ratio), which is a conventional acetic acid-based mixed acid, was used as the acid etching solution. Etched with. The results are also shown in Table 4.
[0094]
[Table 4]

[0095]
From Table 4, in Example 1 (phosphoric acid-based mixed acid), a wafer with very good flatness (TTV) and swell was obtained. Also, a wafer with a very small pit depth could be manufactured. It was found that the glossiness was the same value as before and could be adjusted within the standard range. Moreover, the surface roughness (Ra) of the wafer chamfered portion is good, and there is an effect that the load such as mirror chamfering is reduced.
[0096]
Next, the CW wafer surfaces of Example 1 and Comparative Example 1 were polished. The polishing allowance was 7 μm (target value) on the entire surface side. Polishing conditions were as follows: polishing apparatus: single wafer polishing apparatus, polishing cloth: non-woven cloth type polishing cloth, polishing agent: colloidal silica polishing agent (pH = 10.5).
[0097]
The polished product was measured for TTV and SFQRmax and examined for appearance.
Here, the SFQR (Site Front least-sQuares Range) is a value representing the maximum range of unevenness with respect to the surface by calculating the average plane of the surface standard for the flatness for each site, and SFQRmax is the total site on the wafer. Represents the maximum value in the SFQR.
The results are shown in Table 5. Moreover, about the comparative example 1, it grind | polished further and grind | polished until an external appearance abnormality was no longer seen (comparative example 1b).
[0098]
[Table 5]

[0099]
Here, the flatness TTV and SFQRmax are measured using a flatness measuring instrument (U / G9500, U / S9600) manufactured by ADE, and the surface roughness (Ra) is measured by Kosaka Laboratory Co., Ltd. A surface shape measuring instrument (SE-3C type) was used.
Further, the flatness SFQRmax was evaluated in an area of 20 mm × 20 mm using a flatness measuring device manufactured by ADE. About the external appearance, the presence or absence of the pit was confirmed with the microscope.
[0100]
As can be seen from the above results, in Example 1, a wafer having a high flatness and no abnormal appearance (pits) could be produced by polishing with a polishing allowance of 7 μm or less. This could be achieved by performing alkali etching → phosphoric acid-containing acid etching, and reducing the pit depth after etching compared to the prior art. Further, since the polishing allowance can be reduced, it is possible to improve the polishing efficiency, prevent the sagging of the outer periphery due to the polishing, and manufacture a wafer having excellent flatness of the outer periphery of the wafer.
[0101]
As described above, the flatness and the pit depth of the CW wafer are improved by using alkali etching and phosphoric acid-containing acid etching. Moreover, a wafer with less undulation can be obtained. The glossiness can be adjusted to the same extent in both the comparative example and the example.
[0102]
It can be seen that the PW wafer has an appearance abnormality in the comparative example, and the polishing allowance is insufficient. Usually, in order to completely eliminate pits after etching, excessive polishing of about pit depth +3 μm is required. Increasing the amount of polishing also increases the processing time. Further, as can be seen from the comparative example, SFQRmax becomes worse as the polishing allowance increases. It is preferable that the polishing allowance is small. With phosphoric acid-containing acid etching, the polishing allowance could be reduced, and a mirror-polished wafer with improved flatness such as SFQRmax could be produced.
[0103]
(Example 2)
A mirror-finished wafer was produced by a process as shown in FIG. Slicing an ingot with a diameter of about 200 mm, chamfering first, then using lapping slurry (lapping abrasive grain count # 1200) and lapping wafer (referred to as lapping wafer) for surface grinding under the following conditions went.
[0104]
Surface grinding was performed using an in-feed type single-side grinding apparatus at a spindle rotation speed of 5500 rpm, a wafer rotation speed of 7 rpm, and a grindstone feed speed of 0.2 μm / sec. Then, secondary chamfering was performed.
The flatness (TTV) of the wafer after this surface grinding was approximately 0.6 μm.
[0105]
Next, the alkali etching was performed by setting the etching allowance target to 20 μm on both sides and immersing the wafer in an aqueous NaOH solution having a concentration of 50% by weight at 85 ° C. for 450 seconds. Next, after being immersed in 0.3% hydrogen peroxide as a hydrophilization treatment, a mixed acid consisting of 50 wt% hydrofluoric acid: 70 wt% nitric acid: 85 wt% phosphoric acid = 1: 3: 2 (volume ratio) is used. Acid etching was performed at a liquid temperature of 25 ° C. with an etching allowance target of 10 μm on both sides.
[0106]
For those that have finished acid etching, measure the flatness (TTV), surface roughness (Ra), waviness, appearance inspection (and pit depth), and gloss of the backside of the wafer, and investigate the effects of surface grinding and etching. did.
[0107]
For the measurement of TTV, a flatness measuring instrument (U / G9500, U / S9600) manufactured by ADE was used. The Ra was measured by using a universal surface shape measuring device (SE-3C type) manufactured by Kosaka Laboratory Ltd. and measuring the central portion of the wafer.
[0108]
Waviness is the origin of the height by matching the difference in height between the measurement start time and the measurement end time, and the absolute value Y of the displacement from the origin at a pitch of 2 mm. ₁ To Y ₂₉ And the average value is defined as waviness. A universal surface shape measuring device (SE-3F type) manufactured by Kosaka Laboratory Ltd. was used as the undulation measuring device. The measurement was performed by tracing the central portion of the wafer 60 mm with a stylus and measuring only the shape component excluding the fine surface roughness component.
[0109]
For appearance inspection, the presence or absence of pits was observed with a microscope.
When pits were observed, the pit depth was confirmed. The pit depth was obtained from the depth of focus of the optical microscope. The pit depth is indicated by the maximum value of wafers evaluated for multiple sheets.
[0110]
The glossiness was determined on the back side of the wafer using a gloss meter SD manufactured by Toyo Seiki.
The results are shown in Table 6.
[0111]
[Table 6]

[0112]
Next, the wafer after the etching was mirror polished. The surface on which the surface was ground first was polished, and the polishing allowance was set at a target value of 4 μm.
Polishing conditions are: polishing device; single wafer type polishing device, polishing cloth; non-woven cloth type polishing cloth,
Abrasive: Polished using a colloidal silica abrasive (pH = 10.5).
[0113]
About the polished wafer, TTV and SFQRmax were measured, and an appearance inspection was performed.
SFQR was measured using an ADE flatness measuring instrument, and the site size was evaluated in an area of 20 mm × 20 mm. The results are shown in Table 7.
[0114]
[Table 7]

[0115]
As can be seen from the above results, in Example 2, a wafer having a high flatness and no appearance abnormality (grinding marks or pits) could be produced by polishing with a polishing allowance of 4 μm or less. This could be achieved by performing surface grinding before etching, particularly alkali etching, and further performing acid etching of a mixed acid containing phosphoric acid after alkali etching in the etching step.
[0116]
(Comparative Example 2)
In the same manner as in Example 2, a lap wafer having a diameter of 200 mm (lap abrasive grain number: # 1200) was used for etching. Etching was performed in two stages: alkali etching and acid etching using hydrofluoric acid, nitric acid, and acetic acid based mixed acid.
[0117]
Alkaline etching was performed by immersing the wafer in an aqueous NaOH solution having a concentration of 50% by weight at 85 ° C. for 450 seconds with an etching allowance of 20 μm on both sides. Next, after being immersed in 0.3% hydrogen peroxide as a hydrophilization treatment, etching is performed with a mixed acid of 50 wt% hydrofluoric acid: 70 wt% nitric acid: 100 wt% acetic acid = 1: 2: 1 (volume ratio). Acid etching was performed at a liquid temperature of 25 ° C. with a target of 10 μm on both sides.
[0118]
For the samples that had been etched, flatness (TTV), surface roughness (Ra), waviness, appearance inspection (and pit depth), and gloss were measured. The results are also shown in Table 6.
[0119]
Next, the wafer after the etching was mirror polished. The target for polishing was 4 μm. The polishing conditions are the same as in Example 2.
About the polished wafer, TTV and SFQRmax were measured, and an appearance inspection was performed. The results are also shown in Table 7.
As can be seen from the above results, in Comparative Example 2, pits were present at a polishing allowance of 4 μm (Table 7: Comparative Example 2-a).
[0120]
The polishing was further continued until the pit disappeared (Table 7: Comparative Example 2-b). As a result, pits disappeared by polishing about 10 μm on the entire surface side, but the flatness was slightly deteriorated.
[0121]
(Example 3)
A mirror-finished wafer was manufactured by a process as shown in FIG. A single crystal rod (ingot) with a diameter of 200 mm and a resistivity of 0.02 Ω · cm is sliced with a wire saw, and after primary chamfering, lapping slurry (lap abrasive grain count # 1200) is used and 40 μm wrapping on both sides did. Next, the lap slurry was switched to lap abrasive grain count # 1500, and 20 μm wrapping was performed on both sides.
[0122]
Next, surface grinding was performed. For surface grinding, an infeed single-side grinding apparatus was used, and the surface was ground by 10 μm on one side using a # 4000 grindstone. Surface grinding conditions were as follows: spindle rotation speed 5500 rpm, wafer rotation speed 7 rpm, and grindstone feed speed 0.2 μm / sec. After that, secondary chamfering was performed.
[0123]
At this stage, local damage (pits) was conventionally formed at the time of lapping due to the influence of lapping abrasive grains. However, surface grinding could reduce the local mechanical processing distortion. The flatness (TTV) of the wafer after this surface grinding was approximately 0.6 μm.
[0124]
Next, as an etching process, first, alkaline etching was performed by setting the etching allowance to 15 μm on both sides and immersing the wafer in an aqueous NaOH solution having a concentration of 50% by weight at 85 ° C. Next, after being immersed in 0.3% hydrogen peroxide as a hydrophilization treatment, a mixed acid consisting of 50 wt% hydrofluoric acid: 70 wt% nitric acid: 85 wt% phosphoric acid = 1: 3: 2 (volume ratio) is used. Acid etching was performed at a liquid temperature of 25 ° C. with an etching allowance of 5 μm on both sides.
[0125]
Next, the back surface of the wafer was polished.
Polishing conditions were as follows: polishing apparatus: single wafer polishing apparatus, polishing cloth: non-woven cloth type polishing cloth, polishing agent: colloidal silica polishing agent (pH = 10.5). The polishing allowance was 0.1 μm.
Note that this polishing allowance may be about 0.05 to 0.3 μm depending on the glossiness.
[0126]
Next, the chamfered portion of the outer periphery of the wafer was mirror polished.
The wafer surface after such a process was mirror-polished. Polishing was performed in a plurality of stages (three stages of primary polishing, secondary polishing, and final polishing). The polishing allowance for the entire surface side was set to a target of 3 μm. The main polishing conditions were polishing using a polishing apparatus: single-wafer polishing apparatus, polishing cloth: non-woven cloth type polishing cloth, and polishing agent: colloidal silica polishing agent (pH = 10.5).
[0127]
For polished wafers, TTV and SFQR _max The back glossiness, appearance inspection and nanotopography were confirmed.
[0128]
For the measurement of TTV and SFQR, flatness measuring instruments (U / G9500, U / S9600) manufactured by ADE were used. SFQR was measured using an ADE flatness measuring instrument, and the site size was evaluated in an area of 20 mm × 20 mm.
[0129]
For appearance inspection, the presence or absence of pits was observed with a microscope.
When pits were observed, the pit depth was confirmed. The pit depth was obtained from the depth of focus of the optical microscope. Further, the occurrence of stains or the like was confirmed visually on the back surface of the wafer.
[0130]
Glossiness was measured by a method according to the same method using Specimen Glossmeter (Gloss Meter SD) specified in the standard with reference to JIS Z 8741 (Specular Gloss Measurement Method).
[0131]
Nanotopography (also referred to as nanotopology) is unevenness having a wavelength of about 0.1 mm to 20 mm and an amplitude of about several nm to 100 nm. As an evaluation method, one side is about 0.1 mm to 10 mm. The height difference (PV value: peak to valley) of the unevenness of the wafer surface is evaluated in a square or circular block range having a diameter of about 0.1 mm to 10 mm (this range is called WINDOW SIZE etc.). This PV value is also called Nanotopography Height. As nanotopography, it is desired that the maximum value of the unevenness existing in the evaluated wafer surface is small. In this example, a plurality of block ranges were evaluated with a 10 mm square, and the maximum PV value was evaluated. The results are shown in Table 8.
[0132]
[Table 8]

[0133]
As can be seen from the above results, in Example 3, a wafer with a polishing allowance of 4 μm or less and a high flatness and no appearance abnormality (grinding streaks, pits and blue stain on the back surface) could be produced. In particular, the micro unevenness at the nanotopography level is also improved, which shows that it is preferable.
[0134]
This can be achieved by performing surface grinding before etching, especially alkali etching, and further etching the mixed acid containing phosphoric acid after the alkali etching in the etching step and polishing the back surface. It is. In addition, no stain or the like was observed on the back surface of the wafer, and the glossiness was controlled to an appropriate value.
[0135]
(Comparative Example 3)
A mirror-finished wafer was manufactured by a process as shown in FIG. Similarly to Example 3, after slicing a single crystal rod (ingot) having a diameter of 200 mm and a resistivity of 0.02 Ω · cm with a wire saw and performing primary chamfering, lapping slurry (lapping abrasive grain number # 1200) was obtained. Used, 40 μm wrapping on both sides. Next, the lap slurry was switched to lap abrasive grain count # 1500, and 20 μm wrapping was performed on both sides.
[0136]
Next, an etching process was performed. Etching was performed in two stages: alkali etching and acid etching using hydrofluoric acid, nitric acid, and acetic acid based mixed acid.
Alkaline etching was performed by immersing the wafer in an aqueous NaOH solution having a concentration of 50% by weight at 85 ° C. for 450 seconds with an etching allowance of 20 μm on both sides. Next, after being immersed in 0.3% hydrogen peroxide as a hydrophilization treatment, etching is performed with a mixed acid of 50 wt% hydrofluoric acid: 70 wt% nitric acid: 100 wt% acetic acid = 1: 2: 1 (volume ratio). Acid etching was performed at a liquid temperature of 25 ° C. with a target of 10 μm on both sides.
[0137]
The surface of the wafer after such a process was mirror-polished in the same manner as in Example 3. Polishing was performed in a plurality of stages (three stages of primary polishing, secondary polishing, and final polishing). The overall polishing allowance was set at 3 μm. The main polishing conditions were polishing using a polishing apparatus: single-wafer polishing apparatus, polishing cloth: non-woven cloth type polishing cloth, and polishing agent: colloidal silica polishing agent (pH = 10.5).
[0138]
For the polished wafer, as in Example 3, TTV and SFQR _max The back glossiness, appearance inspection and nanotopography were confirmed. The results are also shown in Table 8.
As can be seen from the above results, TTV, SFQR _max In addition, both the nanotopography values are inferior to those of Example 3. Stain was observed on this wafer with a low resistivity.
[0139]
The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
[0140]
For example, if a lap wafer having a flatness higher than that of the above embodiment is used and etching is performed, a wafer having a better flatness than that of the above embodiment can be manufactured. That is, although the flatness deterioration due to etching can be reduced in the present invention, the absolute value of TTV is also influenced by the quality of the lap wafer.
[0141]
Also, the pit depth is slightly affected by the number of lap abrasive grains used during lapping. Normally, lapping abrasive grains of about # 1200 are used in the lapping process, but the pit depth can be further improved by using # 1500 lapping abrasive grains.
[0142]
In this embodiment, as an example of the condition for obtaining a wafer with high flatness, it is illustrated that etching is performed with an etching margin of about 20 μm on both sides by alkali etching and about 10 μm on both sides by acid etching. Not limited to this, the ratio of alkali etching may be further reduced depending on the state of the wafer after lapping, and the overall etching cost may be reduced. By adjusting the ratio of alkali etching and acid etching according to the desired wafer quality, a wafer with high flatness and a shallow pit depth can be manufactured.
[0143]
Further, for example, in the present embodiment, manufacturing of a wafer in which only one side is highly mirror-finished has been described. However, the present invention is not limited to this and can be applied to manufacturing a wafer in which both sides are highly mirror-finished. CW obtained by alkali etching and phosphoric acid-containing acid etching has improved pit depth on both the front and back surfaces, so the polishing allowance can be reduced even when both surfaces are polished. Can be processed into a wafer having
[0144]
In particular, it is preferable to carry out the process in which the lapping process as shown in FIG. 1A is omitted, and both sides may be ground using a double-head grinding apparatus in the surface grinding process. Since the pit depth is improved on both the front and back surfaces of the wafer etched with alkali etching and phosphoric acid-containing acid after that, the polishing allowance can be reduced even when both surfaces are polished, and has the same high flatness as one side. Can be processed into wafers.
[0145]
Further, for example, in the above embodiment, the case where a silicon wafer having a diameter of 200 mm (8 inches) is manufactured has been described as an example. However, the present invention is not limited to this, and the diameter is 4 to 16 inches or more. It can also be applied to silicon single crystals.
[0146]
【The invention's effect】
As described above, according to the present invention, by using a phosphoric acid-based mixed acid after alkali etching, the etching of deep pits peculiar to an alkali-etched surface is suppressed due to the effect of increasing the viscosity due to the addition of phosphoric acid. A surface can be obtained, the mirror polishing cost can be reduced, and the productivity of the polishing process is improved. Further, the waviness is improved, and the flatness after mirror polishing is greatly improved. Further, since the machining allowance in mirror polishing can be reduced, deterioration of flatness in the polishing process can be suppressed, and a wafer with high flatness can be easily manufactured.
[0147]
Furthermore, while maintaining the flatness of the wafer, the mechanically processed strain layer is removed, the surface roughness is improved, the depth of the generated pits is made shallower, and a smooth uneven chemical etching wafer is produced. It is possible to provide a semiconductor wafer manufacturing method and a processed semiconductor wafer in which the polishing allowance in the mirror polishing step is reduced to about 4 μm on the entire surface. Therefore, it is possible to improve the mirror polishing productivity and the wafer flatness, thereby reducing the cost and quality of the mirror polishing process.
Further, it is possible to prevent surface gloss called blue stain and glossiness on the backside of the wafer.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a process of manufacturing a semiconductor mirror wafer from a single crystal rod.
(A) It is the flowchart which showed the example of the manufacturing process of this invention.
(B) It is the flowchart which showed another manufacturing process of this invention.
FIG. 2 is a flowchart showing a method for processing a semiconductor wafer having a back surface polishing step of the present invention.
FIG. 3 is a flowchart showing an example of a conventional manufacturing process.

Claims (16)

In a semiconductor wafer processing method in which a semiconductor wafer obtained by slicing a single crystal rod is subjected to at least a chamfering process, a lapping process, an etching process, and a mirror polishing process, the etching process is performed after alkali etching and then acid etching. In this case, the semiconductor wafer processing method is characterized in that the acid etching is performed with an acid etching solution comprising hydrofluoric acid, nitric acid, phosphoric acid, and water. A semiconductor wafer processing method in which a semiconductor wafer obtained by slicing a single crystal rod is subjected to at least a chamfering process, a surface grinding process, an etching process, and a mirror polishing process, wherein the surface grinding process is performed before the etching process. The method for processing a semiconductor wafer is characterized in that the etching step is performed by acid etching after alkali etching, and in this case, the acid etching is performed with an acid etching solution comprising hydrofluoric acid, nitric acid, phosphoric acid, and water. 3. The semiconductor wafer processing method according to claim 2, wherein in the semiconductor wafer processing method, a lapping step is further added, and the processing is performed in the order of a lapping step, a surface grinding step, and an etching step. In a semiconductor wafer processing method in which a semiconductor wafer obtained by slicing a single crystal rod is subjected to at least a flattening step, an etching step, and a mirror polishing step, the flattening step is preceded by an etching step, and the etching step is alkali etching. After that, acid etching is performed. At that time, acid etching is performed with an acid etching solution composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, and the mirror polishing step is performed after the acid etching and then the back surface polishing step. A method for processing a semiconductor wafer, comprising performing a surface polishing step. 5. The method for processing a semiconductor wafer according to claim 4, wherein the flattening step is a lapping step and / or a surface grinding step. 6. The semiconductor wafer processing method according to claim 4, wherein the back surface polishing step is performed so that the glossiness is 35 to 50%. 7. The method for processing a semiconductor wafer according to claim 2, wherein the wafer is ground so that the thickness of the outer peripheral portion of the wafer is increased by the surface grinding step. The method for processing a semiconductor wafer according to claim 1, wherein the total etching allowance in the etching step is 30 μm or less on both sides. 9. The method for processing a semiconductor wafer according to claim 1, wherein a polishing allowance in the mirror polishing step is set to 7 [mu] m or less. The composition ratio at the time of preparation of the acid etching solution is that the hydrofluoric acid concentration is 5 to 15% by weight and the phosphoric acid concentration is 10 to 40% by weight. The processing method of the semiconductor wafer described in 2. 11. The method of processing a semiconductor wafer according to claim 1, wherein the acid etching solution is a solution in which silicon is dissolved at a concentration of 10 g / L or more. The composition ratio when the acid etching solution is used is that the hydrofluoric acid concentration is 1 to 7% by weight and the phosphoric acid concentration is 18 to 33% by weight. The processing method of the semiconductor wafer described in 2. 13. The method for processing a semiconductor wafer according to claim 1, wherein the alkali etching solution for the alkali etching is an aqueous NaOH solution or an aqueous KOH solution. A semiconductor wafer processed by the method according to any one of claims 1 to 13. A chemically etched semiconductor wafer having a maximum pit depth of 4 μm or less, a waviness of 0.05 μm or less, and a glossiness of 20 to 70%. A semiconductor wafer having a mirror-polished surface, the SFQRmax is 0.1 μm or less, and the other mirror-polished surface has a maximum pit depth of 4 μm or less, a waviness of 0.05 μm or less, and a glossiness of 20 A semiconductor wafer characterized by being -70%.

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