CN114325357A - DEBUG system, method, device and medium - Google Patents
DEBUG system, method, device and medium Download PDFInfo
- Publication number
- CN114325357A CN114325357A CN202111452712.3A CN202111452712A CN114325357A CN 114325357 A CN114325357 A CN 114325357A CN 202111452712 A CN202111452712 A CN 202111452712A CN 114325357 A CN114325357 A CN 114325357A
- Authority
- CN
- China
- Prior art keywords
- observed
- signal
- data
- collector
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000004590 computer program Methods 0.000 claims description 12
- 239000002699 waste material Substances 0.000 abstract description 13
- 230000003993 interaction Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 7
- 230000009471 action Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 238000013024 troubleshooting Methods 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The application discloses DEBUG system, including main control unit and collector. And the main controller is connected with the JTAG simulator, and receives the access of the JTAG simulator and decodes the access information to acquire the IP of the signal to be observed. The main controller is connected with each collector through a JTAG protocol to carry out information interaction. And each collector is connected with the signal to be observed in the chip to acquire the data of the signal to be observed. And the main controller controls the corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located. By adopting the technical scheme, the signal to be observed is directly connected to the collector of the system, the main controller directly controls the collector to acquire the data of the signal to be observed through the access of the simulator, the data of other signals is not required to be acquired, and the waste of resources and time is reduced when the signal to be observed is observed. The application also discloses a DEBUG method, a device and a medium, which correspond to the system and have the same effects as the system.
Description
Technical Field
The present application relates to the field of troubleshooting technologies, and in particular, to a DEBUG system, method, apparatus, and medium.
Background
The boundary scan test technique is a very common technique for troubleshooting (DEBUG), which is used to solve the test difficulty caused by the excessive pins of the chips on the printed circuit board block, and also used to test the connection between the chips and the whole system. The boundary scan test technology is a test method for testing excitation information and serial transmission by adding a scan chain and a test access port between the boundary of internal logic of a chip and an external pin.
However, the observation of the chip signal by the method can only be step-by-step observation, and the observation of the signal to be observed requires the observation of the preceding signal in advance, which causes the waste of observation resources and time.
Therefore, how to reduce the waste of resources and time when observing the signal to be observed is an urgent problem to be solved by the technical personnel in the field.
Disclosure of Invention
The present application aims to provide a DEBUG system, method, apparatus and medium, which are used for reducing waste of resources and time when observing a signal to be observed.
In order to solve the above technical problem, the present application provides a DEBUG system, including:
a main controller 1 and a collector 2;
the main controller 1 is connected with the JTAG simulator 3, receives the access of the JTAG simulator 3 and decodes the access to acquire the IP of the signal to be observed;
the main controller 1 is connected with each collector 2 through a Joint Test Action Group (JTAG) protocol;
each collector 2 is connected with the signal to be observed in the chip;
and the main controller 1 controls a corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located.
In order to solve the above technical problem, the present application further provides a DEBUG method applied to the DEBUG system, including:
acquiring an IP where a signal to be observed sent by a JTAG simulator is located;
selecting a corresponding target collector according to the IP where the signal to be observed is located;
and controlling the target collector to latch the data of the signal to be observed.
Preferably, before the step of controlling the target collector to latch the data of the signal to be observed, the method further includes:
acquiring an observation mode of the signal to be observed, wherein the observation mode comprises a direct observation mode and a condition observation mode;
further, the controlling the target collector to latch the data of the signal to be observed includes: and controlling the target collector to latch the data of the signal to be observed according to the observation mode.
Preferably, if the observation mode is a direct observation mode, the controlling the target collector to latch the data of the signal to be observed according to the observation mode includes:
and controlling the target collector to latch the data of the signal to be observed at the current moment.
Preferably, if the observation mode is a conditional observation mode, the controlling the target collector to latch the data of the signal to be observed according to the observation mode includes:
acquiring addresses of registers of the signals to be observed and corresponding target data;
and under the condition that the real-time data corresponding to the address of each register of the signal to be observed meets the target data, controlling the target collector to latch the real-time data meeting the target data and the address of the corresponding register.
Preferably, the method further comprises the following steps:
and inquiring whether the state of each register of the target collector is empty, and if not, closing the collector.
Preferably, the method further comprises the following steps:
and acquiring time information of the data moment when the target acquisition device latches the signal to be observed.
Preferably, the method further comprises the following steps:
acquiring observation chain information sent by the JTAG simulator, wherein the observation chain information comprises the IP where each signal to be observed is located in an observation chain;
and controlling all the target collectors on the observation chain to latch the corresponding data of the signal to be observed according to the observation chain information.
In order to solve the above technical problem, the present application further provides a DEBUG apparatus, including a memory for storing a computer program;
a processor for implementing the steps of the DEBUG method as described above when executing the computer program.
To solve the above technical problem, the present application further provides a computer-readable storage medium, having a computer program stored thereon, where the computer program, when executed by a processor, implements the steps of the DEBUG method as described above.
The DEBUG system comprises a main controller and a collector. When the JTAG simulator sends access, the main controller receives the access and decodes the access information to acquire the IP where the signal to be observed is located. The main controller is connected with each collector through a JTAG protocol to carry out information interaction. Each collector is connected with the signal to be observed in the chip and is used for acquiring the data of the signal to be observed. The main controller can control the corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the prior art, the signals of the chip need to be observed stage by stage. By adopting the technical scheme, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, the main controller directly controls the collector to acquire the data of the signal to be observed through the access of the JTAG simulator, the data of other signals is not required to be acquired, and the waste of resources and time is reduced when the signal to be observed is observed.
In addition, the DEBUG method, the device and the medium provided by the application correspond to the DEBUG system, and the effects are the same as those of the DEBUG system.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a structural diagram of a DEBUG system provided in an embodiment of the present application;
fig. 2 is a structural diagram of a main controller according to an embodiment of the present disclosure;
fig. 3 is a structural diagram of a collector provided in an embodiment of the present application;
fig. 4 is a flowchart of a DEBUG method provided in an embodiment of the present application;
fig. 5 is a structural diagram of a DEBUG device provided in an embodiment of the present application;
the reference numbers are as follows: the system comprises a main controller 1, a collector 2, a JTAG simulator 3, a TAP controller 4, a multiplexer 5, a signal acquisition controller 6, a decoder 7 and a signal latch 8.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The boundary scan test technique is a very common technique for DEBUG, and is used to solve the test difficulty caused by excessive pins of the chips on the printed circuit board block, and also used to test the connection between the chips and the whole system. The boundary scan test technology is a test method for testing excitation information and serial transmission by adding a scan chain and a test access port between the boundary of internal logic of a chip and an external pin.
However, the observation of the chip signal by the method can only be step-by-step observation, and the observation of the signal to be observed requires the observation of the preceding signal in advance, which causes the waste of observation resources and time.
The core of the application is to provide a DEBUG system, method, device and medium, which are used for reducing the waste of resources and time when a signal to be observed is observed.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
Fig. 1 is a structural diagram of a DEBUG system provided in an embodiment of the present application, and as shown in fig. 1, the DEBUG system includes:
a main controller 1 and a collector 2;
the main controller 1 is connected with the JTAG simulator 3, receives the access of the JTAG simulator 3 and decodes the access to acquire the IP of the signal to be observed; the main controller 1 is connected with each collector 2 through a JTAG protocol; each collector 2 is connected with a signal to be observed in the chip; the main controller 1 controls the corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located.
IP: abbreviations for Intellectual Property mean: impact the asset. Is an intellectual property, which in this embodiment can be understood as a module of a chip. Each IP is designed to provide that important signals, namely the signals to be observed, are uniformly connected to the top layer of the IP. The signal to be observed may be a separate signal or data of an IP internal register.
In the embodiment of the application, the main controller 1 is connected with the JTAG emulator 3 through a JTAG pin, receives access of the JTAG emulator 3, decodes the access to acquire an IP where a signal to be observed is located, and controls the corresponding collector 2 to operate through the IP to acquire data of the signal to be observed.
Fig. 2 is a block diagram of a main controller according to an embodiment of the present application, and as shown in fig. 2, the main controller 1 includes a TAP controller 4 and a multiplexer 5. The TAP controller 4 includes a JTAG protocol state machine and a part of control logic, and implements preliminary analysis of the JTAG protocol coming from the JTAG pin of the JTAG emulator 3, selects and controls a certain collector 2, or selects and connects a certain JTAG link between the TDI and TDO interfaces of the JTAG protocol, to complete access to the inside of the chip, and sends selected information to the multiplexer 5 for implementation. The multiplexer 5 analyzes the output information according to the output of the TAP controller 4, selects a certain JTAG link, outputs TDI to the selected JTAG link, and returns the output TDO signal of the JTAG link to the TAP controller 4, thereby realizing information interaction between the main controller 1 and the collector 2.
Fig. 3 is a structural diagram of an acquirer provided in an embodiment of the present application, and as shown in fig. 3, an acquirer 2 includes a signal acquisition controller 6, a decoder 7, and a signal latch 8. The signal acquisition controller 6 is used for analyzing the JTAG protocol transmitted by the main controller 1 or other collectors 2, and converting the analyzed protocol into an internal register read-write protocol, that is, converting serial TDI into parallel read or write, and converting read data into serial TDO for output. Meanwhile, the signal acquisition controller 6 provides a self-defined control register group, and the self-defined control register group mainly realizes the following functions: controlling an enabling switch of the collector 2; the latch mode of the register is selected. The latching mode of the selection register is mainly realized by the following registers:
mode selection register: two modes, direct latch mode and conditional latch mode, are provided. When configured in direct latch mode, collector 2 will directly latch the latch value of the currently selected signal to be observed after configuration signal latch 8 is enabled. When the configuration is in the conditional latch mode, after the configuration signal latch 8 is enabled, the latches configured with the selected signal to be observed are monitored until the latches reach the configured target value, and the latch values of all the signals to be observed in the IP are latched.
A latch register: after the register is configured, the control collector 2 latches the latch value of the current signal to be observed, and real-time change does not occur any more.
A latch condition register: the latched condition includes two conditions of address and data, and the latch is performed when the signal value of the collector 2 corresponding to the configured address reaches the configured data value.
A latch state register: for feeding back the latch state of the currently selected signal latch 8.
The decoder 7 in the collector 2 can select a corresponding offset address register according to the address of the register read-write protocol converted by the signal acquisition controller 6, so as to be used for acquiring specific certain data in the signal to be observed.
The signal latch 8 in the collector 2 is used for receiving the signal to be observed and receiving the control information of the signal acquisition controller 6. And when the latch signal is received, the latch of the signal to be observed is realized, and the latched signal value does not change in real time any more.
The DEBUG system provided by the embodiment of the application comprises a main controller and a collector. When the JTAG simulator sends access, the main controller receives the access and decodes the access information to acquire the IP where the signal to be observed is located. The main controller is connected with each collector through a JTAG protocol to carry out information interaction. Each collector is connected with the signal to be observed in the chip and is used for acquiring the data of the signal to be observed. The main controller can control the corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the prior art, the signals of the chip need to be observed stage by stage. By adopting the technical scheme, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, the main controller directly controls the collector to acquire the data of the signal to be observed through the access of the JTAG simulator, the data of other signals is not required to be acquired, and the waste of resources and time is reduced when the signal to be observed is observed.
In the foregoing embodiment, the DEBUG system is described in detail, and an embodiment of the present application further provides a DEBUG method applied to the DEBUG system. Fig. 4 is a flowchart of a DEBUG method provided in an embodiment of the present application, and as shown in fig. 4, the method includes:
s10: and acquiring the IP where the signal to be observed sent by the JTAG emulator 3 is located.
The JTAG emulator 3 is also called a JTAG debugger, and is a device that performs debugging through a JTAG boundary scan port of the ARM chip. In step S10, the user selects a signal to be observed of the chip to be observed by setting the JTAG emulator 3, and the main controller 1 acquires information sent by the JTAG emulator 3 through the JTAG pin and analyzes the information to obtain the IP where the signal to be observed is located. The number of the signals to be observed may be one or more.
S11: and selecting a corresponding target collector according to the IP where the signal to be observed is located.
In a specific implementation, each signal to be observed has a corresponding collector 2. There are often multiple collectors 2 on a JTAG chain, and if multiple signals to be observed are located on the same JTAG chain, all collectors 2 on the chain can be selected according to the JTAG chain.
S12: and controlling the target acquisition device to latch the data of the signal to be observed.
In step S12, the main controller 1 controls the target collector to latch the data of the signal to be observed. The latch time may be immediately when the target acquisition receives the control signal of the main controller 1, or may be when the value of the register of the signal to be observed reaches a preset threshold value.
The DEBUG method provided by the embodiment of the application is applied to the DEBUG system. And when the JTAG simulator sends access, the main controller acquires the access and decodes the access information to acquire the IP where the signal to be observed is located. The main controller is connected with each collector through a JTAG protocol to carry out information interaction. Each collector is connected with the signal to be observed in the chip and is used for acquiring the data of the signal to be observed. The main controller can control the corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the prior art, the signals of the chip need to be observed stage by stage. By adopting the technical scheme, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, the main controller directly controls the collector to acquire the data of the signal to be observed through the access of the JTAG simulator, the data of other signals is not required to be acquired, and the waste of resources and time is reduced when the signal to be observed is observed.
In specific implementation, for the latch of the signal to be observed, for some simpler DEBUG scenes, only the states of some signals need to be observed. For the higher complexity DEBUG scenario, the technician needs to acquire the states of certain signals under certain conditions.
Therefore, on the basis of the above embodiment, in this embodiment, before the step of controlling the target collector to latch the data of the signal to be observed, the method further includes:
acquiring an observation mode of a signal to be observed, wherein the observation mode comprises a direct observation mode and a condition observation mode;
further, controlling the target collector to latch the data of the signal to be observed includes: and controlling the target collector to latch the data of the signal to be observed according to the observation mode.
In the present embodiment, the observation mode includes a direct observation mode and a conditional observation mode. It should be noted that, when the observation mode is the direct observation mode, the collector 2 latches data of the signal to be observed at the current time. When the observation mode is the condition observation mode, the collector 2 can always monitor the data of the signal to be observed, and the data of the signal to be observed is latched when reaching the preset value. It can be understood that there are different registers in the signal to be observed, when the observation mode is the conditional observation mode, the collector 2 monitors each register according to the address of each register in the signal to be observed, each register in the signal to be observed has respective corresponding target data, when the data of the register reaches the target data, that is, the latch condition, the collector 2 latches the latch values of all the signals to be observed in the IP at the moment, so that the technician can obtain the data of the signal to be observed under the specific condition.
The DEBUG method provided by the embodiment of the application is used for dividing the observation of a signal to be observed into a direct observation mode and a condition observation mode. In the direct observation mode, the signal to be observed can be dynamically observed in real time. In the condition observation mode, the data of the signal to be observed in a special and static scene can be acquired, and the verification personnel can be more effectively and directly helped to acquire the internal state information of the chip to be acquired. By adopting the technical scheme, technicians can select different observation modes according to requirements, so that the observation flexibility is improved.
On the basis of the foregoing embodiment, in this embodiment, if the observation mode is the direct observation mode, controlling the target collector to latch the data of the signal to be observed according to the observation mode includes:
and controlling the target acquisition device to latch the data of the signal to be observed at the current moment.
According to the DEBUG method provided by the embodiment of the application, under the condition that the observation mode is the direct observation mode, the target collector latches the data of each register of the signal to be observed at the current moment, and the signal to be observed can be observed dynamically in real time.
On the basis of the foregoing embodiment, in this embodiment, if the observation mode is the conditional observation mode, controlling the target collector to latch the data of the signal to be observed according to the observation mode includes:
acquiring addresses of registers of signals to be observed and corresponding target data;
and under the condition that the real-time data corresponding to the address of each register of the signal to be observed meets the target data, controlling the register of the target collector to latch the real-time data meeting the target data and the address of the corresponding register.
In this embodiment, after setting the addresses of the registers of the signals to be observed and the corresponding target data, the collector 2 monitors the registers. When the real-time data corresponding to each register reaches the target data, the collector 2 latches. Specifically, the decoder 7 in the collector 2 selects a corresponding offset address according to the address of the register read-write protocol converted by the signal collection controller 6, and the address of the register of the signal to be observed can be obtained by adding the offset address to the address of the register read-write protocol, so as to collect a specific certain data in the signal to be observed. It can be understood that collector 2 latches when the real-time data in the register in the signal to be observed reaches the target data, and if the target data is not reached, collector 2 continues to monitor and latch after it reaches the target data.
The DEBUG method provided by the embodiment of the application can acquire the data of the signal to be observed in a special and static scene under the condition that the observation mode is the conditional observation mode, and can more effectively and directly help a verifier to acquire the internal state information of the chip to be acquired.
In specific implementation, after each register in the collector 2 acquires data of a signal to be observed, the collector 2 is not used any more, but the collector 2 is still in an enabled state, which causes waste of resources.
On the basis of the above embodiment, in this embodiment, the method further includes:
and inquiring whether the state of each register of the target collector is empty, and if not, closing the collector 2.
According to the DEBUG method provided by the embodiment of the application, whether the states of all registers of the target collector are empty or not is inquired, and if not, the situation that the collector acquires the data of the signal to be observed is indicated, so that the collector is closed, and the waste of resources is reduced.
TCK is used as test clock input pin of JTAG, and can add time information to JTAG system. On the basis of the above embodiment, in this embodiment, the method further includes:
and acquiring time information of the data moment when the target acquisition device latches the signal to be observed.
According to the DEBUG method provided by the embodiment of the application, the main controller acquires time information and adds a timestamp to data of a signal to be observed latched by the target acquisition unit each time, so that the change trend of the signal to be observed can be judged.
It should be noted that collector 2 is located on the JTAG chain, which is in TDI and TDO of main controller 1. There may be many collectors 2 on one JTAG chain, and in the specific implementation, if it is desired to observe a signal to be observed on one JTAG chain, the method further includes:
acquiring observation chain information sent by a JTAG simulator 3, wherein the observation chain information comprises the IP of each signal to be observed on an observation chain; and controlling all the collectors 2 on the observation chain to latch the data of the corresponding signals to be observed according to the observation chain information.
The DEBUG method provided by the embodiment of the application controls all collectors on one JTAG chain to work according to the observation chain information, acquires the data of all signals to be observed on the JTAG chain, and realizes the large-scale monitoring of the signals to be observed.
In the above embodiments, the DEBUG method is described in detail, and the present application also provides embodiments corresponding to the DEBUG device.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
Fig. 5 is a structural diagram of a DEBUG device provided in an embodiment of the present application, and as shown in fig. 5, the DEBUG device includes: a memory 20 for storing a computer program;
a processor 21, configured to implement the steps of the DEBUG method according to the above embodiment when executing the computer program.
The DEBUG device provided by the embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 21 may be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
The memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing the following computer program 201, wherein after being loaded and executed by the processor 21, the computer program can implement the relevant steps of the DEBUG method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, and the like, and the storage manner may be a transient storage manner or a permanent storage manner. Operating system 202 may include, among others, Windows, Unix, Linux, and the like. Data 203 may include, but is not limited to, the IP on which the signal to be observed is located, data of the signal to be observed, time information, and the like.
In some embodiments, the DEBUG device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the configuration shown in fig. 5 does not constitute a limitation of the DEBUG apparatus and may include more or fewer components than those shown.
The DEBUG device provided by the embodiment of the application comprises a memory and a processor, and when the processor executes a program stored in the memory, the following method can be realized: acquiring an IP where a signal to be observed sent by a JTAG simulator is located; selecting a corresponding target collector according to the IP where the signal to be observed is located; and controlling the target acquisition device to latch the data of the signal to be observed.
According to the DEBUG device provided by the embodiment of the application, when the JTAG emulator sends access, the main controller receives the access and decodes the access information to acquire the IP where the signal to be observed is located. The main controller is connected with each collector through a JTAG protocol to carry out information interaction. Each collector is connected with the signal to be observed in the chip and is used for acquiring the data of the signal to be observed. The main controller can control the corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the prior art, the signals of the chip need to be observed stage by stage. By adopting the technical scheme, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, the main controller directly controls the collector to acquire the data of the signal to be observed through the access of the JTAG simulator, the data of other signals is not required to be acquired, and the waste of resources and time is reduced when the signal to be observed is observed.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
According to the computer-readable storage medium provided by the embodiment of the application, when the JTAG emulator sends access, the main controller receives the access and decodes the access information to acquire the IP where the signal to be observed is located. The main controller is connected with each collector through a JTAG protocol to carry out information interaction. Each collector is connected with the signal to be observed in the chip and is used for acquiring the data of the signal to be observed. The main controller can control the corresponding target collector to obtain the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the prior art, the signals of the chip need to be observed stage by stage. By adopting the technical scheme, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, the main controller directly controls the collector to acquire the data of the signal to be observed through the access of the JTAG simulator, the data of other signals is not required to be acquired, and the waste of resources and time is reduced when the signal to be observed is observed.
A DEBUG system, method, apparatus and medium provided by the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A DEBUG system, comprising:
a main controller (1) and a collector (2);
the main controller (1) is connected with the JTAG simulator (3), receives the access of the JTAG simulator (3) and decodes the access to acquire the IP of the signal to be observed;
the main controller (1) is connected with each collector (2) through a JTAG protocol;
each collector (2) is connected with the signal to be observed in the chip;
and the main controller (1) controls a corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located.
2. A DEBUG method applied to the DEBUG system of claim 1, comprising:
acquiring an IP where a signal to be observed sent by a JTAG simulator is located;
selecting a corresponding target collector according to the IP where the signal to be observed is located;
and controlling the target collector to latch the data of the signal to be observed.
3. The DEBUG method of claim 2, wherein prior to said step of controlling said target collector to latch data of a signal to be observed, further comprising:
acquiring an observation mode of the signal to be observed, wherein the observation mode comprises a direct observation mode and a condition observation mode;
further, the controlling the target collector to latch the data of the signal to be observed includes: and controlling the target collector to latch the data of the signal to be observed according to the observation mode.
4. The DEBUG method of claim 3, wherein if the observation mode is a direct observation mode, the controlling the target collector to latch the data of the signal to be observed according to the observation mode comprises:
and controlling the target collector to latch the data of the signal to be observed at the current moment.
5. The DEBUG method of claim 3, wherein if the observation mode is a conditional observation mode, the controlling the target collector to latch the data of the signal to be observed according to the observation mode comprises:
acquiring addresses of registers of the signals to be observed and corresponding target data;
and under the condition that the real-time data corresponding to the address of each register of the signal to be observed meets the target data, controlling the target collector to latch the real-time data meeting the target data and the address of the corresponding register.
6. The DEBUG method according to any one of claims 2 to 5, further comprising:
and inquiring whether the state of each register of the target collector is empty, and if not, closing the collector.
7. The DEBUG method according to claim 6, further comprising:
and acquiring time information of the data moment when the target acquisition device latches the signal to be observed.
8. The DEBUG method of claim 2, further comprising:
acquiring observation chain information sent by the JTAG simulator, wherein the observation chain information comprises the IP where each signal to be observed is located in an observation chain;
and controlling all the target collectors on the observation chain to latch the corresponding data of the signal to be observed according to the observation chain information.
9. A DEBUG apparatus, comprising a memory for storing a computer program;
a processor for implementing the steps of the DEBUG method of any of claims 2 to 8 when executing said computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored thereon, which, when being executed by a processor, carries out the steps of the DEBUG method according to any one of claims 2 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111452712.3A CN114325357A (en) | 2021-11-30 | 2021-11-30 | DEBUG system, method, device and medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111452712.3A CN114325357A (en) | 2021-11-30 | 2021-11-30 | DEBUG system, method, device and medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114325357A true CN114325357A (en) | 2022-04-12 |
Family
ID=81049367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111452712.3A Pending CN114325357A (en) | 2021-11-30 | 2021-11-30 | DEBUG system, method, device and medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114325357A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
| CN112527710A (en) * | 2020-12-17 | 2021-03-19 | 西安邮电大学 | JTAG data capturing and analyzing system |
-
2021
- 2021-11-30 CN CN202111452712.3A patent/CN114325357A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
| CN112527710A (en) * | 2020-12-17 | 2021-03-19 | 西安邮电大学 | JTAG data capturing and analyzing system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113312879B (en) | Chip circuit function verification system, method, device and storage medium | |
| CN108446215B (en) | POS machine test method, device, system and terminal | |
| US10203371B2 (en) | Methods and systems for generating functional test patterns for manufacture test | |
| CN105787164A (en) | Debugging method and system for programmable logic device | |
| CN109240965B (en) | FPGA logic capturing processing display suite and use method thereof | |
| CN107273249B (en) | Mainboard test method, processor and mainboard test system | |
| CN111722968A (en) | Hardware debugging method, device and system and readable storage medium | |
| CN113014339A (en) | Quality test method, device and equipment for PCIe external plug-in card receiving channel | |
| CN109407655B (en) | Method and device for debugging chip | |
| CN114281624A (en) | Method, system, device and equipment for testing I2C signal integrity | |
| CN117076337B (en) | Data transmission method and device, electronic equipment and readable storage medium | |
| CN113849419A (en) | Method, system, equipment and storage medium for generating test vector of chip | |
| CN116521468B (en) | FPGA online debugging method and FPGA supporting online debugging | |
| EP3961403A1 (en) | Bus monitoring device and method, storage medium, and electronic device | |
| CN112485699A (en) | Server power supply test system | |
| CN114325357A (en) | DEBUG system, method, device and medium | |
| CN108693466B (en) | Boundary scanning device, control method and scanning method | |
| CN115017080A (en) | Circuit and method for multiplexing JTAG pin in FPGA chip | |
| CN116087752A (en) | Chip testing method, system, device and medium | |
| US9946624B1 (en) | Systems and methods to capture data signals from a dynamic circuit | |
| US6973607B2 (en) | Method and apparatus for testing electronic components | |
| CN106650006B (en) | Debugging method and system of programmable logic device and electronic design automation terminal | |
| CN111367729A (en) | Debug method, system and equipment combining CPLD and UART | |
| CN111428691A (en) | Chip debugging method, chip debugging device, storage medium and processor | |
| CN116719746B (en) | Debugging method, equipment, product to be debugged and computer storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |