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CN114093756A - Thin film etching method and manufacturing method of array substrate - Google Patents

Thin film etching method and manufacturing method of array substrate Download PDF

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Publication number
CN114093756A
CN114093756A CN202111383275.4A CN202111383275A CN114093756A CN 114093756 A CN114093756 A CN 114093756A CN 202111383275 A CN202111383275 A CN 202111383275A CN 114093756 A CN114093756 A CN 114093756A
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photoresist
layer
thin film
baking
pattern
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李治朝
马冬冬
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InfoVision Optoelectronics Kunshan Co Ltd
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InfoVision Optoelectronics Kunshan Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0231Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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Abstract

本发明提供一种薄膜蚀刻方法,主要包括以下步骤:在薄膜上涂覆光阻,形成光阻层;对光阻层进行烘烤固化,使光阻层形成固化程度不一样的光阻表层和光阻底层;利用光罩对上述烘烤之后的光阻进行曝光、显影,形成倒梯形结构的光阻图案;以倒梯形结构的光阻图案为遮罩,对薄膜进行蚀刻以形成薄膜图案;剥离倒梯形结构的光阻图案。本发明利用对光阻层进行烘烤固化,使得光阻的表层和底层得到硬度性质不一样的光阻,光阻的硬度从上至下逐渐减小,使得曝光、显影后得到倒梯形结构,从而能蚀刻更细的薄膜图案,有利于清除光阻。

Figure 202111383275

The invention provides a thin film etching method, which mainly comprises the following steps: coating a photoresist on the thin film to form a photoresist layer; baking and curing the photoresist layer, so that the photoresist layer forms a photoresist surface layer and a photoresist layer with different curing degrees. Resist bottom layer; use a photomask to expose and develop the photoresist after the baking to form a photoresist pattern of an inverted trapezoidal structure; use the photoresist pattern of an inverted trapezoidal structure as a mask, etch the film to form a film pattern; peel off Photoresist pattern with inverted trapezoid structure. In the invention, the photoresist layer is cured by baking, so that the surface layer and the bottom layer of the photoresist can obtain photoresist with different hardness properties, and the hardness of the photoresist gradually decreases from top to bottom, so that the inverted trapezoid structure is obtained after exposure and development. Thereby, finer thin film patterns can be etched, which is beneficial to remove the photoresist.

Figure 202111383275

Description

Thin film etching method and manufacturing method of array substrate
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a film etching method and a manufacturing method of an array substrate.
Background
With the continuous maturity and development of display technologies, the requirements of consumers on display devices are higher and higher, and one of them is that consumers prefer display devices having larger display screen occupation ratio and narrower frame setting.
In the currently introduced display device with narrow frame or ultra-narrow frame, the stripping of the coating material (such as metal) is crucial in the actual production process, and the coating material which needs to be stripped and the coating material which does not need to be stripped cannot be connected. In order to isolate the coating material, the photoresist above the film is typically developed to form a trapezoidal structure (see fig. 1), i.e., a structure with a wide top and a narrow bottom. As shown in fig. 1, a1 represents the width of the conventional resist pattern 91, and B1 represents the width of the conventional thin film pattern 92 obtained after etching. The trapezoid structure of the existing photoresist pattern 91 manufactured after exposure and development is etched to obtain the existing thin film pattern 92, the bottom of the trapezoid structure is larger, so that the adhesion force is enhanced, the trapezoid structure is not easy to remove in the subsequent removal stage, and the residual film is easy to form; meanwhile, the manufactured wires are wide, and the space between the wires is small, so that short circuit is easily caused, and the yield is reduced.
Disclosure of Invention
In view of the above-mentioned disadvantages, an object of the present invention is to provide a thin film etching method and a method for fabricating an array substrate, which can form a thinner thin film pattern by etching and can remove a photoresist more easily.
The embodiment of the invention provides a film etching method, which comprises the following steps:
coating a layer of photoresist on the film to form a photoresist layer;
baking and curing the light resistance layer to form a light resistance surface layer and a light resistance bottom layer with different curing degrees on the light resistance layer, wherein the curing hardness of the light resistance surface layer is greater than that of the light resistance bottom layer;
exposing and developing the baked photoresist layer by using a photomask to form a photoresist pattern with an inverted trapezoidal structure;
etching the film by taking the photoresist pattern of the inverted trapezoidal structure as a mask to form a film pattern;
and stripping the photoresist pattern of the inverted trapezoid structure.
Further, the curing hardness of the photoresist layer gradually decreases from the photoresist surface layer to the photoresist bottom layer.
Further, baking and curing the photoresist layer to form a photoresist surface layer and a photoresist bottom layer with different curing degrees on the photoresist layer, comprising:
baking the front side of the photoresist layer for the first time by adopting a heat source; and
and adopting the heat source to carry out secondary baking on the back of the photoresist layer, wherein the temperature of the secondary baking is lower than that of the primary baking.
Further, the temperature of the first baking is 120-125 ℃, and the temperature of the second baking is 100-105 ℃.
Further, the thickness of light resistance layer is 1.2 ~ 1.8um, the time of first toasting is 30 ~ 50s, the time of second toasting is 100 ~ 130 s.
Further, the heat source is a hot plate.
Further, the photoresist is a negative photoresist or a positive photoresist.
Further, the film is a first metal layer film for etching the gate electrode or a second metal layer film for etching the drain electrode.
The embodiment of the invention also discloses a manufacturing method of the array substrate, which is used for etching at least one layer of film on the array substrate to form a film pattern.
Further, the film is a metal layer film, an insulating layer film or a transparent conducting layer film.
In the film etching method and the array substrate manufacturing method provided by this embodiment, the photoresist layer is baked and cured, so that the photoresist layer with different hardness properties is obtained on the photoresist surface layer and the photoresist bottom layer, and an etching pattern with an inverted trapezoidal structure is obtained after exposure and development, so that a finer film pattern can be etched. Meanwhile, due to the inverted trapezoidal structure of the light resistor, the contact surface between the light resistor and the film is smaller, and the subsequent stripping is more facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic view of a partial structure of a photoresist pattern and a thin film pattern manufactured in a conventional manner.
FIG. 2 is a process flow diagram of a thin film etching method in an embodiment of the invention.
FIG. 3 is a schematic diagram of the structural product of S10 in an example of the present invention.
FIG. 4 is a schematic diagram of the structural product of S21 in example of the present invention.
FIG. 5 is a schematic diagram of the structural product of S22 in example of the present invention.
Fig. 6 is a schematic structural diagram of S30 exposure and development in the embodiment of the present invention.
FIG. 7 is a schematic diagram of a structure of a thin film pattern formed after etching at S40 according to an embodiment of the present invention.
FIG. 8 is a schematic diagram of the structure of the peeled S50 in this embodiment of the present invention.
FIG. 9 is a schematic view of a partial structure of a photoresist pattern and a thin film pattern according to an embodiment of the present invention.
Fig. 10 is a schematic structural diagram of an array substrate according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The steps of the thin film etching method of the embodiment of the invention are as follows,
as shown in fig. 3, S10: a first side of the film 10 is coated with a photoresist to form a photoresist layer 20.
Specifically, the photoresist may be a positive photoresist or a negative photoresist. In the present embodiment, the photoresist is a positive photoresist, and the photoresist includes a linear novolac resin, a photosensitizer and an aqueous solvent.
The film 10 is a metal layer film or an insulating layer film. In this embodiment, a metal layer film 10 is first deposited on a substrate 100.
As shown in fig. 4, S20: baking and curing the photoresist layer 20 to form a photoresist surface layer 21 and a photoresist bottom layer 22 with different curing degrees on the photoresist layer 20, wherein the curing hardness of the photoresist surface layer 21 is greater than that of the photoresist bottom layer 22, and for this characteristic, a differentiation between the surface layer and the bottom layer is formed during the photoresist exposure and development.
Specifically, the curing hardness of the photoresist layer 20 gradually decreases from the photoresist surface layer 21 to the photoresist underlayer 22.
Baking and curing the photoresist layer 20 to form a photoresist surface layer 21 and a photoresist bottom layer 22 with different curing degrees on the photoresist layer 20, including S21: the front surface of the film 10 is first baked using the heat source 30.
And S22 as shown in fig. 5: and (3) performing secondary baking on the back surface of the photoresist layer 20 by using the heat source 30, wherein the temperature of the secondary baking is lower than that of the primary baking.
The heat source 30 is preferably a hot plate, which allows the film 10 to be heated more uniformly. The heat source 30 may be heat treated by infrared radiation, thermal plate conduction, or the like. The vacuum hot plate baking is adopted, so that the temperature can be conveniently controlled, and meanwhile, uniform heating can be ensured.
Specifically, the first baking temperature is 120-125 ℃, and the first baking time is 30-50 s. By the first baking, the photoresist surface layer 21 of the photoresist layer 20 can be quickly baked, so that the photoresist surface layer 21 is preferentially cured. It is worth mentioning that the temperature of the first baking should not exceed 125 ℃, otherwise the photoresist could not be shaped and delaminated. In this embodiment, the thickness of the photoresist layer 20 is 1.2-1.8 um, the first baking time is controlled within 30-50 s, the formed photoresist surface layer 21 and the formed photoresist bottom layer 22 can be obtained, the second baking temperature is 100-105 ℃, and the second baking time is 100-130 s. In other embodiments, the thickness of the photoresist layer 20 may be less than 1.2um or greater than 1.8um, the first baking time and the second baking time are adjusted according to the actual production situation, the photoresist layer 20 forms the photoresist surface layer 21 and the photoresist bottom layer 22 with different curing degrees through the first baking, and the photoresist bottom layer 22 is cured through the second baking.
It is noted that the front side of the photoresist layer 20 refers to the side of the photoresist layer 20 not in contact with the film 10, and the back side of the photoresist layer 20 refers to the side of the photoresist layer 20 in contact with the film 10.
The thicknesses of the photoresist surface layer 21 and the photoresist underlayer 22 are divided according to the actual curing state after the first baking, but the invention is not limited thereto.
As shown in fig. 6, S30: the baked photoresist layer 20 is exposed and developed by a mask 40 to form a photoresist pattern 23 having an inverted trapezoidal structure.
In the photolithography process, the photoresist layer 20 is subjected to light irradiation and then chemically reacts, and the internal molecular structure thereof is changed, thereby forming a structure that can be dissolved or not dissolved in development.
In the present embodiment, the photoresist layer 20 is exposed to light by using the mask 40 to prepare a desired pattern. In the case of positive photoresists, exposure can cleave molecules in the photosensitive material (PAC), and the cleaved molecules are readily dissolved in a developer. During the subsequent development, the dissolution rates of the light-sensitive portions and the non-light-sensitive portions of the photoresist layer 20 are very different. After baking and curing, the photo-sensitive reaction of the photoresist surface layer 21 is small, the dissolution rate is slow, and the photo-sensitive reaction of the photoresist bottom layer 22 is large, the dissolution rate is fast, so that the corresponding photoresist layer 20 will form the photoresist pattern 23 with the inverted trapezoid structure of "wide upper portion and small lower portion". That is, under the same etching conditions, the etching rate of the photoresist underlayer 22 is greater than that of the photoresist surface layer 21.
As shown in fig. 7, S40: the thin film 10 is etched using the resist pattern 23 having a trapezoidal structure as a mask to form a thin film pattern 11.
As shown in fig. 8, S50: the resist pattern 23 of the ladder structure is peeled off.
The film 10 is chemically or physically removed at the portions not covered and protected by the photoresist layer 20 to complete the purpose of the photoresist pattern 23 to the film pattern 11. The etching process may be wet etching or dry etching, which is not limited in the present invention.
Referring to fig. 9, in fig. 9, a2 is a width of the photoresist pattern 23, and B2 is a width of the thin film pattern 11 obtained after etching. Referring to fig. 1 and 9, in the case where the width of the photoresist pattern 23 is the same as the width of the conventional photoresist pattern 91 in the present application (i.e., a1 is equal to a2), since the photoresist layer 20 forms the photoresist pattern 23 having an inverted trapezoidal structure with a wider upper portion and a narrower lower portion, the contact area between the bottom of the photoresist pattern 23 and the thin film 10 is reduced, and during the etching process, a thinner thin film pattern 11 (i.e., B2< B1) can be obtained by etching the photoresist pattern 23, which is beneficial to meeting the requirement of a narrow pitch between lines when manufacturing a narrow-frame display device.
Because the width of the bottom of the inverted trapezoid structure of the photoresist layer 20 is smaller, the photoresist layer is easier to strip and remove in the water flow impact process, the probability of the residual photoresist layer 20 can be reduced, and the problem that the photoresist layer 20 is easy to remain is solved.
As shown in fig. 10, the present invention also provides a method for fabricating an array substrate, which can fabricate thinner lines by using the above-mentioned thin film etching method when at least one thin film on the array substrate is etched to form a thin film pattern. Specifically, a first metal layer film for etching the gate electrode 121 or a second metal layer film for etching the drain electrode 125. .
As will be understood by those skilled in the art, a TFT array including a plurality of TFTs 120 arranged in an array is formed on the substrate 100. Each TFT 120 includes a gate electrode 121, a gate insulating layer 122, an active layer 123, a source electrode 124, and a drain electrode 125.
When the array substrate is manufactured, a first metal layer film is formed on the substrate 100, and is etched and patterned to form a scan line (not shown) and a gate electrode 121, wherein the gate electrode 121 is electrically connected to the scan line; depositing a gate insulating layer 122 covering the scan line and the gate electrode 121 on the substrate 100; depositing an active layer thin film on the gate insulating layer thin film 122, and etching and patterning the active layer thin film to form an active layer 123, where the active layer 123 may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), a metal oxide semiconductor (e.g., IGZO), or the like; depositing a second metal layer film on the gate insulating layer 122, and performing etching patterning on the second metal layer film to form a data line (not shown), a source electrode 124, and a drain electrode 125, wherein the source electrode 124 is electrically connected to the data line; depositing a first insulating layer film 13 covering the TFT array; forming a planarization layer 14 on the first insulating film 13, patterning the planarization layer 14, and removing the planarization layer 14 at a position corresponding to the drain electrode 125 to expose the underlying first insulating film 13; depositing a first transparent conductive layer film on the planarization layer 14, and etching and patterning the first transparent conductive layer film to form a common electrode 15; forming a second insulating film 16 on the common electrode 15, and etching and patterning the second insulating film 16 and the first insulating film 13 to form a contact hole 19 at a position corresponding to the drain electrode 125 and expose the drain electrode 125 thereunder; a second transparent conductive layer film is deposited on the second insulating layer film 16, and is etched and patterned to form a pixel electrode 17, and the pixel electrode 17 is in contact with and electrically connected to the drain electrode 125. The pixel electrode 17 and the common electrode 15 are made of Indium Tin Oxide (ITO) or the like, for example.
In the above manufacturing process, when at least one of the first metal layer thin film, the second metal layer thin film, the first insulating layer thin film, the second insulating layer thin film, the first transparent conductive layer thin film, and the second transparent conductive layer thin film is subjected to etching patterning, the above film etching method is used for manufacturing. By adopting the method to manufacture the array substrate, the manufactured photoresist pattern 23 can etch thinner film patterns 11, namely thinner lines, and is more beneficial to the subsequent manufacture of narrow-frame display devices.
Understandably, the thin film etching method and the manufacturing method of the array substrate provided in the above embodiments utilize baking and curing to make the photoresist surface layer 21 and the photoresist bottom layer 22 obtain the photoresist layer 20 with different hardness properties, and after exposure and development, the photoresist pattern 23 with the inverse trapezoid structure is obtained, so that the thinner thin film pattern 11 can be etched through the photoresist pattern 23. Meanwhile, due to the photoresist pattern 23 with the inverted trapezoid structure, the contact surface between the photoresist layer 20 and the film 10 is smaller, which is more beneficial to subsequent removal and reduces the probability of photoresist residue.
In this document, the upper and lower directional terms are defined as the positions of the components in the drawings and the positions of the components relative to each other, and are used for clarity and convenience of the technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1.一种薄膜蚀刻方法,其特征在于,包括以下步骤:1. a thin film etching method, is characterized in that, comprises the following steps: 在薄膜(10)上涂覆一层光阻,形成光阻层(20);A layer of photoresist is coated on the film (10) to form a photoresist layer (20); 对所述光阻层(20)进行烘烤固化,使所述光阻层(20)形成固化程度不一样的光阻表层(21)和光阻底层(22),其中,所述光阻表层(21)的固化硬度大于所述光阻底层(22)的固化硬度;Baking and curing the photoresist layer (20), so that the photoresist layer (20) forms a photoresist surface layer (21) and a photoresist bottom layer (22) with different curing degrees, wherein the photoresist surface layer ( The curing hardness of 21) is greater than the curing hardness of the photoresist bottom layer (22); 利用光罩(40)对上述烘烤之后的所述光阻层(20)进行曝光、显影,以形成倒梯形结构的光阻图案(23);The photoresist layer (20) after the above-mentioned baking is exposed and developed using a photomask (40) to form a photoresist pattern (23) with an inverted trapezoidal structure; 以所述倒梯形结构的光阻图案(23)为遮罩,对所述薄膜(10)进行蚀刻以形成薄膜图案(11);Using the photoresist pattern (23) of the inverted trapezoid structure as a mask, etching the thin film (10) to form a thin film pattern (11); 剥离所述倒梯形结构的光阻图案(23)。The photoresist pattern (23) of the inverted trapezoid structure is peeled off. 2.如权利要求1所述的薄膜蚀刻方法,其特征在于,所述光阻层(20)的固化硬度从所述光阻表层(21)到所述光阻底层(22)逐渐减小。2. The thin film etching method according to claim 1, characterized in that the curing hardness of the photoresist layer (20) gradually decreases from the photoresist surface layer (21) to the photoresist bottom layer (22). 3.如权利要求1所述的薄膜蚀刻方法,其特征在于,对所述光阻层(20)进行烘烤固化,使所述光阻层(20)形成固化程度不一样的光阻表层(21)和光阻底层(22),包括:3. The thin film etching method according to claim 1, wherein the photoresist layer (20) is cured by baking, so that the photoresist layer (20) forms a photoresist surface layer (20) with different curing degrees. 21) and a photoresist bottom layer (22), including: 采用热源(30)对所述光阻层(20)的正面进行第一次烘烤;以及A heat source (30) is used to bake the front side of the photoresist layer (20) for the first time; and 采用所述热源(30)对所述光阻层(20)的背面进行第二次烘烤,且所述第二次烘烤的温度低于所述第一次烘烤的温度。The backside of the photoresist layer (20) is baked for the second time by using the heat source (30), and the temperature of the second baking is lower than the temperature of the first baking. 4.如权利要求3所述的薄膜蚀刻方法,其特征在于,所述第一次烘烤的温度为120℃~125℃,所述第二次烘烤的温度为100℃~105℃。4 . The thin film etching method according to claim 3 , wherein the temperature of the first baking is 120° C.˜125° C., and the temperature of the second baking is 100° C.˜105° C. 5 . 5.如权利要求3所述的薄膜蚀刻方法,其特征在于,所述光阻层(20)的厚度为1.2~1.8um,所述第一次烘烤的时间为30~50s,所述第二次烘烤的时间为100~130s。5. The thin film etching method according to claim 3, wherein the thickness of the photoresist layer (20) is 1.2-1.8um, the first baking time is 30-50s, and the first baking time is 30-50s. The time of secondary baking is 100-130s. 6.如权利要求3所述的薄膜蚀刻方法,其特征在于,所述热源(30)为热板。6. The thin film etching method according to claim 3, wherein the heat source (30) is a hot plate. 7.如权利要求1所述的薄膜蚀刻方法,其特征在于,所述光阻为负性光阻或正性光阻。7. The thin film etching method of claim 1, wherein the photoresist is a negative photoresist or a positive photoresist. 8.如权利要求1所述的薄膜蚀刻方法,其特征在于,所述薄膜(10)为金属层薄膜或绝缘层薄膜或透明导电层薄膜。8. The thin film etching method according to claim 1, wherein the thin film (10) is a metal layer thin film or an insulating layer thin film or a transparent conductive layer thin film. 9.一种阵列基板的制作方法,其特征在于,在对所述阵列基板上的至少一层薄膜进行蚀刻以形成薄膜图案时,采用如权利要求1-8中任一项所述的薄膜蚀刻方法。9 . A method for manufacturing an array substrate, wherein when at least one layer of thin film on the array substrate is etched to form a thin film pattern, the thin film etching method according to any one of claims 1 to 8 is used. method. 10.根据权利要求9所述的阵列基板的制作方法,其特征在于,所述薄膜为用于蚀刻出栅极(121)的第一金属层薄膜或者用于蚀刻出漏极(125)的第二金属层薄膜。10. The manufacturing method of an array substrate according to claim 9, wherein the thin film is a first metal layer thin film for etching out the gate electrode (121) or a first metal layer thin film for etching out the drain electrode (125). Two metal layer films.
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CN117525164A (en) * 2024-01-04 2024-02-06 惠科股份有限公司 Array substrate, preparation method of array substrate and display panel
CN118983274A (en) * 2024-10-17 2024-11-19 杭州合盛微电子有限公司 Method for preparing contact hole of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117525164A (en) * 2024-01-04 2024-02-06 惠科股份有限公司 Array substrate, preparation method of array substrate and display panel
CN118983274A (en) * 2024-10-17 2024-11-19 杭州合盛微电子有限公司 Method for preparing contact hole of semiconductor device

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