CN103915443A - Array substrate, preparation method thereof and liquid crystal display device - Google Patents
Array substrate, preparation method thereof and liquid crystal display device Download PDFInfo
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- CN103915443A CN103915443A CN201310113604.2A CN201310113604A CN103915443A CN 103915443 A CN103915443 A CN 103915443A CN 201310113604 A CN201310113604 A CN 201310113604A CN 103915443 A CN103915443 A CN 103915443A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 title claims abstract description 8
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 8
- 239000010410 layer Substances 0.000 claims abstract description 116
- 238000005530 etching Methods 0.000 claims abstract description 85
- 239000011241 protective layer Substances 0.000 claims abstract description 83
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims description 31
- 238000002161 passivation Methods 0.000 claims description 22
- 238000001459 lithography Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000011218 segmentation Effects 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 5
- 239000012528 membrane Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 3
- 230000003071 parasitic effect Effects 0.000 abstract description 17
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000013039 cover film Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 241000931705 Cicada Species 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention provides an array substrate and a preparation method thereof, wherein data lines and gate lines on the array substrate are manufactured in the same layer, the continuously arranged gate lines are arranged into a plurality of independent data line segments at intervals in a segmented mode, a gate insulating layer and an etching protective layer are covered on the data lines, the etching protective layer covered on the data lines and the etching protective layer formed on an active layer of a thin film transistor are manufactured in the same layer, and extra process steps are not added. Moreover, the thickness of the etching protective layer is very thick, so that the distance between the data line and the common electrode is increased, and the parasitic capacitance between the data line and the common electrode is reduced. Meanwhile, the data line is covered with the etching protection layer which can be made of organic film materials, so that the dielectric constant between the data line and the common electrode is reduced, and the parasitic capacitance between the data line and the common electrode can be further reduced.
Description
Technical field
The present invention relates to technical field of flat panel display, relate in particular to a kind of array base palte and preparation method thereof, liquid crystal indicator.
Background technology
At present; in sull field-effect transistor (Thin Film Transistor, the TFT) design of array base palte, having a kind of design is to utilize organic film (Organic Film) as island etching protective layer (Etch-stop layer; ESL layer), to realize low temperature process.
Utilize the organic film can be as shown in Figure 1 as the structural representation of the array base palte of island ESL layer, Fig. 1 shows the structure of a pixel cell in array base palte, and in array base palte as shown in Figure 1, the cross sectional representation of AA ' position as shown in Figure 2.
In array base palte as depicted in figs. 1 and 2, comprise thin-film transistor, data wire 01 and gate line 02.Described thin-film transistor is included in the grid 05(forming on transparency carrier 00 due to described grid 05 and the same layer manufacture of described gate line 02; therefore; utilize identical pattern to represent described gate line 02 and described grid 05), the gate insulation layer 08 of cover gate 05, be positioned at active layer 07 on gate insulation layer 08, be positioned at the etching protective layer 06 on active layer 07; and separate source electrode 04 is same material with drain electrode 03(source electrode 04 and drain electrode 03; and be positioned at same layer; therefore, adopt identical pattern to represent).
Meanwhile, array base palte also further comprises pixel electrode 09 and passivation layer 10.Because pixel electrode 09 is transparency electrode, so in Fig. 1, at the lap of pixel electrode 09 and drain electrode 03, drain electrode 03 is visible.Passivation layer 10 is the one decks that are positioned on pixel electrode 09, and because passivation layer 10 is transparent, and passivation layer 10 covers the most regions on described transparency carrier 00, and therefore, in Fig. 1, passivation layer 10 is not shown.In Fig. 2, passivation layer 10 can be understood as covering transparency carrier 00 and surrounds the white space in part with dotted line.
On passivation layer 10, array base palte can also comprise public (common) electrode 11.Concrete, in Fig. 2, passivation layer 10 can be understood as and covers transparency carrier 00, public electrode 11 surrounds the white space in part with dotted line.Public electrode 11 transparencies are better, and public electrode 11 can be understood as and cover whole pixel electrode 09, but cover film transistor region not.In order to clearly illustrate that the position of source electrode 04, and the position relationship of drain electrode 03 and pixel electrode 09, in Fig. 1, public electrode 11 can be understood as, and covers dotted line and surrounds in part, except other regions of thin-film transistor region.
In the array base palte shown in Fig. 1 and Fig. 2, data wire 01 and source electrode 04, drain electrode 03 are at same layer, on the one hand, for the parasitic capacitance that reduces data wire 01, gate line 02 respectively and produce between pixel electrode 09, generally pixel electrode 09 and data wire 01, gate line 02 can be spaced a distance, so just reduce the aperture opening ratio of display panels; On the other hand, due to data wire 01 and public electrode 11 parts overlapping, therefore, between data wire 01, gate line 02 and public electrode 11 produce parasitic capacitance all larger.On the make, when the array base palte of large scale and high screen resolution (Pixels Per inch, PPI), panel load (Panel Loading) and signal delay (Delay) all larger, the performance of array base palte is difficult to be guaranteed.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, liquid crystal indicator, for reducing the parasitic capacitance of array base palte.
A kind of array base palte, described array base palte comprises that thin-film transistor and transverse and longitudinal intersection enclose the data wire and the gate line that form multiple pixel cells, described gate line and described data line bit be in same layer, and described data wire is arranged to some independent data line segments taking the described gate line that arranges continuously as space segmentation; Gate insulation layer is formed on described data wire and gate line; Thin-film transistor, comprises source electrode and drain electrode, and described source electrode penetrates the through hole of described gate insulation layer by described data wire top, adjacent described independent data line segment is electrically connected.
A kind of liquid crystal indicator, comprising: above-mentioned array base palte, with the color membrane substrates that described array base palte is oppositely arranged, is arranged on the liquid crystal layer between described array base palte and described color membrane substrates.
A kind of preparation method of array base palte, described method comprises: on transparency carrier, deposition the first metal layer makes gate line and data wire by lithography on this first metal layer, and described data wire is arranged to some independent data line segments taking the described gate line that arranges continuously as space segmentation; On described gate line and data wire, deposition forms gate insulation layer, and described gate insulation layer covers described gate line and described data wire; Above described data wire, etch through hole; On described gate insulation layer, deposition the second metal level makes pattern by lithography on this second metal level, forms separate source electrode and drain electrode, and described source electrode is by the through hole of described data wire top, and adjacent described independent data line segment is electrically connected.
The scheme providing according to the embodiment of the present invention; data wire on array base palte adopts with gate line and manufactures with layer; be arranged to some independent data line segments taking the gate line that arranges continuously as space segmentation; covering gate insulating barrier and etching protective layer on data wire; thereby the distance between data wire and public electrode is strengthened, reduce the parasitic capacitance between data wire and public electrode.
In addition; etching protective layer and thin-film transistor source electrode penetrate the through hole of described gate insulation layer and described the first etching protective layer by described data wire top; adjacent described independent data line segment is electrically connected, does not increase other processing step, processing procedure is simple.
Brief description of the drawings
The structural representation of the array base palte that Fig. 1 provides for prior art;
The cross sectional representation of AA ' position in Fig. 1 that Fig. 2 provides for prior art;
The structural representation of the array base palte that Fig. 3 provides for the embodiment of the present invention one;
The cross sectional representation of AA ' position in Fig. 3 that Fig. 4 provides for the embodiment of the present invention one;
The preparation method's that Fig. 5 provides for the embodiment of the present invention two flow chart of steps.
Embodiment
Below in conjunction with Figure of description, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.And in the situation that not conflicting, the feature in embodiment and embodiment in the application can combine mutually.
Embodiment mono-,
The embodiment of the present invention one provides a kind of array base palte, the structure of this array base palte can be as shown in Figure 3, and in array base palte as shown in Figure 3, the cross sectional representation of AA ' position can be as shown in Figure 4, the array base palte embodiment of the present invention one being provided below in conjunction with Fig. 3 and Fig. 4 describes, described array base palte comprises that thin-film transistor and transverse and longitudinal intersection enclose the data wire 01 and the gate line 02 that form multiple pixel cells, wherein:
Described gate line 02 and described data wire 01 are positioned at same layer, in Fig. 4, due to described gate line 02 and the same layer manufacture of described data wire 01, therefore, utilize identical pattern to represent described gate line 02 and described data wire 01, and described data wire 01 is arranged to some independent data line segments taking the described gate line 02 that arranges continuously as space segmentation;
Described thin-film transistor; comprise that the grid 05(being formed on transparency carrier 00 is due to described grid 05 and the same layer manufacture of described gate line 02; therefore; utilize identical pattern to represent described gate line 02 and described grid 05), gate insulation layer 08, active layer 07, etching protective layer 06, source electrode 04 and drain electrode 03; described etching protective layer 06 comprises the first etching protective layer and the second etching protective layer, wherein:
Described grid 05 is electrically connected with described gate line 02;
Described gate insulation layer 08 covers described grid 05 and described data wire 01;
Described active layer 07, is formed on described gate insulation layer 08, and overlapping with described grid 05 region;
Described the first etching protective layer, be formed on described data wire 01, the width of wherein said the first etching protective layer is greater than the width of data wire 01, in Fig. 3, for the clear position relationship that represents described data wire 01 and described the first etching protective layer, in described data wire 01 and the overlapping part of described the first etching protective layer, show described data wire 01;
Described the second etching protective layer, is formed on described source-drain electrode region;
Described source electrode 04 and described drain electrode 03; separate being formed on described the second etching protective layer, active layer 07 and gate insulation layer 08; and described source electrode 04 penetrates the through hole of described gate insulation layer 08 and described the first etching protective layer by described data wire top, adjacent described independent data line segment is electrically connected.
Further, be also provided with pixel electrode 09 above described drain electrode, described drain electrode 03 is electrically connected with described pixel electrode 09.Because pixel electrode 09 transparency is better, in Fig. 3, at the lap of pixel electrode 09 and drain electrode 03, drain electrode 03 is visible.
Preferably, as shown in Figure 3, in the present embodiment, described pixel electrode 09 can partly overlap with described data wire 01 region.Thereby expand the area of pixel electrode 09, increase effective vent rate.
Further, described array base palte also comprises the passivation layer 10 that covers described pixel electrode 09, described thin-film transistor, described data wire 01 and described gate line 02.Because passivation layer 10 is transparent, and passivation layer 10 covers the most regions on described transparency carrier 00, and therefore, in Fig. 3, passivation layer 10 is not shown.In Fig. 4, passivation layer 10 can be understood as covering transparency carrier 00 and surrounds the white space in part with dotted line.
Further, described array base palte also comprises the public electrode 11 being formed on described pixel electrode 09.Concrete, in Fig. 4, passivation layer 10 can be understood as and covers transparency carrier 00, public electrode 11 surrounds the white space in part with dotted line.Described public electrode 11 is overlapping with described data wire 01 region part, and overlapping with described gate line 02 region part.Public electrode 11 transparencies are better, and public electrode 11 can be understood as and cover whole pixel electrode 09, but cover film transistor region not.In order to clearly illustrate that the position of source electrode 04, and the position relationship of drain electrode 03 and pixel electrode 09, in Fig. 3, public electrode 11 can be understood as, and covers dotted line and surrounds in part, except other regions of thin-film transistor region.
Preferably, described the second etching protective layer and described the first etching protective layer are positioned at same layer.Be that described the second etching protective layer and described the first etching protective layer can be manufactured with layer, thereby reduce the preparation process of array man substrate, simplify preparation technology, save preparation cost.
Preferably; described the second etching protective layer also covers described gate line 02, in Fig. 3, for the clear position relationship that represents described gate line 02 and described the second etching protective layer; in described gate line 02 and the overlapping part of described the second etching protective layer, show described gate line 02.Make array base palte that the present embodiment provides except can reducing the parasitic capacitance between data wire and public electrode, can also reduce the parasitic capacitance between data wire and gate line, gate line and public electrode, thereby further reduce the parasitic capacitance of array base palte.
Preferably, in the present embodiment, described active layer is oxide semiconductor material, for example indium gallium zinc oxide.
In the present embodiment; etching protective layer can be the organic film of organic material formation; and can there is lower dielectric constant; can be generally 2 or 3; under normal circumstances for being less than 4 dielectric constant; for example: etching protective layer material is polyimides (polymide) etc., thereby can further reduce parasitic capacitance.Meanwhile, the thickness of this etching protective layer can be greater than 2 μ m(and comprise 2 μ m), for example, is the thickness of 2～3 μ m.But about dielectric constant and the thickness of etching protective layer, the present invention is not limited to this, concrete dielectric constant and thickness can be selected according to demand in above-mentioned provided scope.
Preferably, with respect to prior art, the etching protective layer that the present embodiment can provide thickness to increase.For example, the thickness of described the first etching protective layer and the second etching protective layer can be 0.5 micron～3 microns.Concrete, can realize by coating processes the increase of etching protective layer thickness.In the present embodiment, due to the etching protective layer that provides thickness to increase, can make the distance between data wire and public electrode strengthen, further reduce the parasitic capacitance between data wire and public electrode.Simultaneously; because etching protective layer thickness increases; with respect to prior art, the array base palte that the embodiment of the present invention provides can also effectively reduce the parasitic capacitance between gate line and public electrode, and can further reduce the parasitic capacitance between data wire and gate line.
Adopt the array base palte of above structure; data wire on array base palte and gate line are manufactured with layer; be arranged to some independent data line segments taking the gate line that arranges continuously as space segmentation; covering gate insulating barrier and etching protective layer on data wire; the etching protective layer covering on data wire adopts with layer manufacture with the etching protective layer being formed on thin film transistor active layer, does not increase extra processing step.And the thickness of etching protective layer is very thick, thereby the distance between data wire and public electrode is strengthened, reduce the parasitic capacitance between data wire and public electrode.Meanwhile, owing to being coated with etching protective layer on data wire, and etching protective layer can adopt organic film material, has therefore also reduced the dielectric constant between data wire and public electrode, thereby can further reduce the parasitic capacitance between data wire and public electrode.In addition, source electrode penetrates the through hole of described gate insulation layer and described the first etching protective layer by described data wire top, adjacent described independent data line segment is electrically connected, and does not increase other processing step, and processing procedure is simple.
Further, the embodiment of the present invention two provides a kind of preparation method of array base palte.
Embodiment bis-,
The embodiment of the present invention two provides a kind of preparation method of array base palte, and for realizing the preparation of the array base palte that the embodiment of the present invention one provides, this preparation method's steps flow chart can as shown in Figure 5, comprise:
Step 101, formation grid, gate line and data wire.
In this step, can be on transparency carrier, deposition the first metal layer makes grid, gate line and data wire by lithography on this first metal layer, and described data wire is arranged to some independent data line segments taking the described gate line that arranges continuously as space segmentation.
Step 102, formation gate insulation layer.
In this step, can be on described grid, gate line and data wire, deposition forms gate insulation layer, and described gate insulation layer covers described grid, gate line and described data wire.This gate insulation layer can be inorganic material, and such as silica, silicon nitride etc. can be also organic material.
Step 103, formation active layer.
In this step, can be on described gate insulation layer, depositing semiconductor layers makes pattern by lithography on this semiconductor layer, form active layer, and described active layer and described grid region overlapping.
Preferably, described semiconductor layer adopts oxide semiconductor material.As, indium gallium zinc oxide.
Step 104, formation etching protective layer.
In this step; can be on described active layer and described gate insulation layer; apply etching protective layer; by this etching protective layer patterning; form the first etching protective layer and the second etching protective layer; wherein, described the first etching protective layer covers described data wire region, and described the second etching protective layer is formed on described source-drain electrode region.The width of wherein said the first etching protective layer is greater than the width of data wire, and the width of described the second etching protective layer is greater than the width of gate line.
Described etching protective layer is the organic film that organic material forms, and has lower dielectric constant, can be generally 2 or 3, under normal circumstances for example, for to be less than 4 dielectric constant: polyimides (polymide).Meanwhile, the thickness of this etching protective layer can be greater than 2 μ m(and comprise 2 μ m), for example, is the thickness of 2～3 μ m.But about dielectric constant and the thickness of etching protective layer, the present invention is not limited to this, concrete dielectric constant and thickness can be selected according to demand in above-mentioned provided scope.
Step 105, etching through hole.
In this step, can above described data wire, etch through hole.
Step 106, formation source electrode and drain electrode.
In this step; can be on described the second etching protective layer, described active layer and described gate insulation layer; deposit the second metal level; on this second metal level, make pattern by lithography; form separate source electrode and drain electrode; and described source electrode, by the through hole of described data wire top, is electrically connected adjacent described independent data line segment.
Further, the present embodiment can also comprise the following steps:
Step 107, formation pixel electrode.
In this step, can be on described drain electrode and described gate insulation layer, deposit transparent conductive layer makes pattern by lithography on this transparency conducting layer, forms pixel electrode, and wherein, described pixel electrode and described data wire region partly overlap.
Step 108, formation passivation layer.
In this step, can be on described pixel electrode, deposit passivation layer, described passivation layer covers described transparency carrier.Described passivation layer can adopt silica or silicon nitride.
Step 109, formation public electrode.
In this step, can be on described passivation layer, deposit transparent electric conducting material makes pattern by lithography on this transparent conductive material, forms public electrode, and described common electrode layer covers described pixel electrode; And described public electrode and described data wire region part are overlapping, and overlapping with described gate line region part.Described transparent conductive material can be tin indium oxide.
The array base palte that above-mentioned manufacture method forms; data wire and gate line are manufactured with layer; be arranged to some independent data line segments taking the gate line that arranges continuously as space segmentation; covering gate insulating barrier and etching protective layer on data wire; the etching protective layer covering on data wire adopts with layer manufacture with the etching protective layer being formed on thin film transistor active layer, does not increase extra processing step.And the thickness of etching protective layer is very thick, thereby the distance between data wire and public electrode is strengthened, reduce the parasitic capacitance between data wire and public electrode.Meanwhile, owing to being coated with etching protective layer on data wire, and etching protective layer can adopt organic film material, has therefore also reduced the dielectric constant between data wire and public electrode, thereby can further reduce the parasitic capacitance between data wire and public electrode.In addition, source electrode penetrates the through hole of described gate insulation layer and described the first etching protective layer by described data wire top, adjacent described independent data line segment is electrically connected, and does not increase other processing step, and processing procedure is simple.
Above embodiment is for technical solution of the present invention is better described, known to those skilled in the art, the present invention also comprises technical scheme essence equivalence described in above embodiment or the scheme being equal to, should be using concrete situation described in embodiment as limiting to the claimed invention.In addition,, although described the application's preferred embodiment, once those skilled in the art obtain the basic creative concept of cicada, can make other change and amendment to these embodiment.So claims are intended to be interpreted as comprising preferred embodiment and fall into all changes and the amendment of the application's scope.
Obviously, those skilled in the art can carry out various changes and modification and the spirit and scope that do not depart from the application to the application.Like this, if these amendments of the application and within modification belongs to the scope of the application's claim and equivalent technologies thereof, the application is also intended to comprise these changes and modification interior.
Claims (21)
1. an array base palte, described array base palte comprises thin-film transistor and encloses the data wire and the gate line that form multiple pixel cells, it is characterized in that,
Described gate line and described data line bit be in same layer, and described data wire is arranged to some independent data line segments taking the described gate line that arranges continuously as space segmentation;
Gate insulation layer is formed on described data wire and gate line;
Thin-film transistor, comprises source electrode and drain electrode, and described source electrode penetrates the through hole of described gate insulation layer by described data wire top, be electrically connected with adjacent described independent data line segment.
2. array base palte as claimed in claim 1; it is characterized in that; described thin-film transistor also comprises the etching protective layer being formed on described gate insulator, and described etching protective layer comprises the second etching protective layer that covers the first etching protective layer on described data wire and be formed on described source-drain electrode region.
3. array base palte as claimed in claim 1, it is characterized in that, described thin-film transistor also comprises the grid and the active layer that are formed on described transparency carrier, wherein, described grid is electrically connected with described gate line, and overlap mutually described active layer and described grid region.
4. array base palte as claimed in claim 1, is characterized in that, is also provided with pixel electrode above described drain electrode, and described drain electrode is electrically connected with described pixel electrode.
5. array base palte as claimed in claim 4, is characterized in that, described pixel electrode and described data wire region partly overlap.
6. array base palte as claimed in claim 4, is characterized in that, described array base palte also comprises the passivation layer that covers described pixel electrode, described thin-film transistor, described data wire and described gate line.
7. array base palte as claimed in claim 6, is characterized in that, described array base palte also comprises the public electrode being formed on described pixel electrode; Described public electrode and described data wire region part are overlapping, and overlapping with described gate line region part.
8. array base palte as claimed in claim 1, is characterized in that, described the second etching protective layer and described the first etching protective layer are positioned at same layer.
9. array base palte as claimed in claim 1, is characterized in that, described the second etching protective layer also covers described gate line.
10. array base palte as claimed in claim 1, is characterized in that, described active layer is oxide semiconductor material.
11. array base paltes as claimed in claim 1, is characterized in that, described the first etching protective layer and the second etching protective layer material are organic film.
12. array base paltes as described in as arbitrary in claim 1～11, is characterized in that, the thickness of described the first etching protective layer and the second etching protective layer is 0.5 micron～3 microns.
13. 1 kinds of liquid crystal indicators, is characterized in that, comprising: the array base palte as described in as arbitrary in claim 1～12, with the color membrane substrates that described array base palte is oppositely arranged, is arranged on the liquid crystal layer between described array base palte and described color membrane substrates.
The preparation method of 14. 1 kinds of array base paltes, is characterized in that, described method comprises:
On transparency carrier, deposition the first metal layer makes gate line and data wire by lithography on this first metal layer, and described data wire is arranged to some independent data line segments taking the described gate line that arranges continuously as space segmentation;
On described gate line and data wire, deposition forms gate insulation layer, and described gate insulation layer covers described gate line and described data wire;
Above described data wire, etch through hole;
On described gate insulation layer, deposition the second metal level makes pattern by lithography on this second metal level, forms separate source electrode and drain electrode, and described source electrode is by the through hole of described data wire top, is electrically connected with adjacent described independent data line segment.
15. preparation methods as claimed in claim 14; it is characterized in that; after forming described gate insulator; also be included on described gate insulation layer, apply etching protective layer, by this etching protective layer patterning; form the first etching protective layer and the second etching protective layer; wherein, described the first etching protective layer covers described data wire region, and described the second etching protective layer is formed on described source-drain electrode region.
16. preparation methods as claimed in claim 14, is characterized in that, are also included on described the first metal layer and make grid simultaneously by lithography, and described grid is electrically connected with described gate line.
17. preparation methods as claimed in claim 16, is characterized in that, after forming described gate insulator, also be included on described gate insulation layer, depositing semiconductor layers makes pattern by lithography on this semiconductor layer, form active layer, and described active layer and described grid region are overlapped mutually.
18. preparation methods as claimed in claim 14, is characterized in that, after forming separate source electrode and drain electrode, also comprise:
On described drain electrode and described gate insulation layer, deposit transparent conductive layer makes pattern by lithography on this transparency conducting layer, forms pixel electrode, and wherein, described pixel electrode and described data wire region partly overlap.
19. preparation methods as claimed in claim 18, is characterized in that, after forming pixel electrode, also comprise:
Deposit passivation layer, covers described transparency carrier;
On described passivation layer, deposit transparent electric conducting material makes pattern by lithography on this transparent conductive material, forms public electrode, and described common electrode layer covers described pixel electrode; And described public electrode and described data wire region part are overlapping, and overlapping with described gate line region part.
20. preparation methods as claimed in claim 14, is characterized in that, described semiconductor layer adopts oxide semiconductor material.
21. preparation methods as claimed in claim 14, is characterized in that, described the first etching protective layer and the second etching protective layer material are organic film.
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Cited By (7)
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| CN106935597A (en) * | 2017-03-14 | 2017-07-07 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN107765920A (en) * | 2017-10-26 | 2018-03-06 | 惠科股份有限公司 | Signal transmission device and display device |
| CN111863906A (en) * | 2020-07-28 | 2020-10-30 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN114415408A (en) * | 2022-01-21 | 2022-04-29 | 合肥京东方显示技术有限公司 | Display substrate, preparation method thereof and display device |
| CN115032840A (en) * | 2022-06-07 | 2022-09-09 | 广州华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN115951515A (en) * | 2022-12-28 | 2023-04-11 | 长沙惠科光电有限公司 | Display panel, preparation method thereof and display device |
| US11927858B2 (en) | 2020-10-23 | 2024-03-12 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Array substrate and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050242347A1 (en) * | 2004-04-29 | 2005-11-03 | Han-Chung Lai | [thin film transistor array and fabricating method thereof] |
| CN101393364A (en) * | 2007-09-21 | 2009-03-25 | 北京京东方光电科技有限公司 | TFT LCD pixel structure and method for manufacturing same |
| CN101893799A (en) * | 2009-05-22 | 2010-11-24 | 上海天马微电子有限公司 | Liquid crystal display panel and method for manufacturing the same |
| CN102023424A (en) * | 2009-09-09 | 2011-04-20 | 北京京东方光电科技有限公司 | TFT-LCD array substrate and manufacture method thereof |
| CN102629612A (en) * | 2011-12-23 | 2012-08-08 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| US20120218489A1 (en) * | 2007-12-28 | 2012-08-30 | Au Optronics Corp. | Liquid Crystal Display Unit Structure Including a Patterned Etch Stop Layer Above a First Data Line Segment |
-
2013
- 2013-04-02 CN CN201310113604.2A patent/CN103915443B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050242347A1 (en) * | 2004-04-29 | 2005-11-03 | Han-Chung Lai | [thin film transistor array and fabricating method thereof] |
| CN101393364A (en) * | 2007-09-21 | 2009-03-25 | 北京京东方光电科技有限公司 | TFT LCD pixel structure and method for manufacturing same |
| US20120218489A1 (en) * | 2007-12-28 | 2012-08-30 | Au Optronics Corp. | Liquid Crystal Display Unit Structure Including a Patterned Etch Stop Layer Above a First Data Line Segment |
| CN101893799A (en) * | 2009-05-22 | 2010-11-24 | 上海天马微电子有限公司 | Liquid crystal display panel and method for manufacturing the same |
| CN102023424A (en) * | 2009-09-09 | 2011-04-20 | 北京京东方光电科技有限公司 | TFT-LCD array substrate and manufacture method thereof |
| CN102629612A (en) * | 2011-12-23 | 2012-08-08 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
Cited By (12)
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|---|---|---|---|---|
| CN106935597A (en) * | 2017-03-14 | 2017-07-07 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN106935597B (en) * | 2017-03-14 | 2020-02-18 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
| US10656478B2 (en) | 2017-03-14 | 2020-05-19 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, and display panel |
| CN107765920A (en) * | 2017-10-26 | 2018-03-06 | 惠科股份有限公司 | Signal transmission device and display device |
| CN107765920B (en) * | 2017-10-26 | 2020-01-14 | 惠科股份有限公司 | Signal transmission device and display device |
| CN111863906A (en) * | 2020-07-28 | 2020-10-30 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US11737342B2 (en) | 2020-07-28 | 2023-08-22 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and manufacturing method thereof and display apparatus |
| US11927858B2 (en) | 2020-10-23 | 2024-03-12 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Array substrate and display device |
| CN114415408A (en) * | 2022-01-21 | 2022-04-29 | 合肥京东方显示技术有限公司 | Display substrate, preparation method thereof and display device |
| CN115032840A (en) * | 2022-06-07 | 2022-09-09 | 广州华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN115032840B (en) * | 2022-06-07 | 2024-05-24 | 广州华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN115951515A (en) * | 2022-12-28 | 2023-04-11 | 长沙惠科光电有限公司 | Display panel, preparation method thereof and display device |
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