CN103780228A - Clock jitter improving circuit and method - Google Patents
Clock jitter improving circuit and method Download PDFInfo
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Abstract
The invention relates to the field of circuit design, and discloses a clock jitter improving circuit and method. The clock jitter improving circuit comprises a current mirror, a voltage reference generation circuit, a sawtooth wave generation and voltage comparison circuit, a frequency dividing circuit and a control circuit. The first input end of the voltage reference generation circuit is connected with the current mirror, and the second input end of the voltage reference generation circuit is connected with the output end of the control circuit. The output end of the voltage reference generation circuit is connected with the first input end of the sawtooth wave generation and voltage comparison circuit. The second input end of the sawtooth wave generation and voltage comparison circuit is connected with the current mirror, and the third input end of the sawtooth wave generation and voltage comparison circuit is connected with the output end of the control circuit. The output end of the sawtooth wave generation and voltage comparison circuit is connected with the frequency dividing circuit. Compared with phase-lock loops of existing PLL circuits, the clock jitter improving circuit provided in the embodiments of the invention has advantages of less circuit modules and simple circuit, and due to the advantages of less circuit modules, simple circuit and less used elements, advantages of less circuit area and low power consumption can be realized.
Description
Technical Field
The invention relates to the field of circuit design, in particular to a clock jitter improving circuit and a clock jitter improving method.
Background
In many circuit systems, such as Analog-to-Digital converters (ADCs) and Digital-to-Analog converters (DACs), clock jitter (clock jitter) of a clock has a significant effect on circuit performance, and a large clock jitter may seriously affect the performance of the ADC or the DAC, so that strict requirements are imposed on the jitter of a sampling clock in the ADC or the DAC with high speed and high accuracy.
The existing circuit for reducing clock jitter adopts a Phase-Locked Loop (PLL) circuit, and the inherent low-pass filtering characteristic of the PLL circuit can effectively filter high-frequency components in the clock jitter, so that the total clock jitter is reduced.
Because the PLL circuit is a phase-locked loop, the structure is complex, and related circuit modules are more, the power consumption is larger.
Disclosure of Invention
In view of this, the present invention is to solve the problems of the prior art that the circuit for reducing clock jitter has a complicated structure, a large circuit area and a large power consumption, and the technical solution is as follows:
a first aspect of the present application provides a clock jitter improving circuit, which includes a current mirror, a voltage reference generating circuit, a sawtooth wave generating and voltage comparing circuit, a frequency dividing circuit, and a control circuit;
the first input end of the voltage reference generating circuit is connected with the current mirror, the second input end of the voltage reference generating circuit is connected with the output end of the control circuit, and the output end of the voltage reference generating circuit is connected with the first input end of the sawtooth wave generating and voltage comparing circuit;
the second input end of the sawtooth wave generating and voltage comparing circuit is connected with the current mirror, the third input end of the sawtooth wave generating and voltage comparing circuit is connected with the output end of the control circuit, and the output end of the sawtooth wave generating and voltage comparing circuit is connected with the frequency dividing circuit;
wherein:
the input end of the control circuit inputs a clock signal, and the output end of the control circuit outputs a control signal;
the voltage reference generating circuit receives a first current of the current mirror according to the control signal and provides a comparison reference level for the sawtooth wave generating and voltage comparing circuit according to the first current;
the third input end of the sawtooth wave generation and voltage comparison circuit receives the control signal, the first input end of the sawtooth wave generation and voltage comparison circuit receives the comparison reference level according to the control signal, the second input end of the sawtooth wave generation and voltage comparison circuit receives the second current of the current mirror, the second current charges a capacitor to generate a sawtooth wave signal, and a square wave is output according to the comparison reference level and the comparison result of the sawtooth wave signal;
the frequency dividing circuit divides the frequency of the square wave and outputs an improved clock signal.
With reference to the first aspect, in a first possible implementation manner of the first aspect,
the circuit further comprises a reference current source;
the current mirror, the voltage reference generating circuit, the sawtooth wave generating and voltage comparing circuit are respectively connected with the reference current source;
the current mirror outputs a current proportional to the reference current source to the voltage reference generation circuit, the sawtooth wave generation and voltage comparison circuit.
With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect,
the voltage reference generating circuit comprises a first charging branch circuit and a second charging branch circuit;
wherein,
the first charging branch is connected with the second charging branch in parallel;
the input end of the first charging branch and the input end of the second charging branch are respectively connected with the current mirror;
the second charging branch circuit carries out periodic charging on the first charging branch circuit.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect,
the first charging branch comprises a first capacitor and a first switch, and the first capacitor and the first switch are connected in series through a first common end;
the second charging branch comprises a second capacitor and a second switch, and the second capacitor and the second switch are connected in series through a second common terminal;
the voltage reference generation circuit further comprises a third switch;
a first end of the third switch is connected with the first common end, and a second end of the third switch is connected with the second common end;
the first common terminal is used as the output terminal of the voltage reference generating circuit and is connected with the sawtooth wave generating and voltage comparing circuit.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect,
the voltage reference generation circuit further comprises a fourth switch and a fifth switch;
the fourth switch is used for resetting the voltage of the second capacitor before charging;
the fifth switch is connected in parallel with the first capacitor, and the fifth switch is used for resetting the voltage of the first capacitor before charging.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect,
the sawtooth wave generation and voltage comparison circuit comprises a comparator, a third capacitor, a sixth switch and a seventh switch;
the first end of the third capacitor is connected with the current mirror, and the second end of the third switch is connected with the grounding end of the reference current source;
an inverting input end of the comparator is connected with the first common end, a positive input end of the comparator is connected with the first end of the third capacitor, and the level output by the output end of the comparator controls the on-off of the seventh switch;
the sixth switch and the seventh switch are respectively connected with the third capacitor in parallel, wherein:
the sixth switch is used for voltage resetting of the third capacitor before charging, and the seventh switch is used for periodic voltage resetting of the third capacitor during normal work.
A second aspect of the present application provides a clock jitter improving method applied to a clock jitter improving circuit, where the circuit includes a current mirror, a voltage reference generating circuit, a sawtooth wave generating and voltage comparing circuit, a frequency dividing circuit, and a control circuit, and the method includes:
the control circuit receives a clock signal and outputs a control signal;
the voltage reference generating circuit receives a first current of the current mirror according to the control signal and provides a comparison reference level for the sawtooth wave generating and voltage comparing circuit according to the first current;
the third input end of the sawtooth wave generation and voltage comparison circuit receives the control signal, the first input end of the sawtooth wave generation and voltage comparison circuit receives the comparison reference level according to the control signal, the second input end of the sawtooth wave generation and voltage comparison circuit receives the second current of the current mirror, the second current charges a capacitor to generate a sawtooth wave signal, and a square wave is output according to the comparison reference level and the comparison result of the sawtooth wave signal;
the frequency dividing circuit divides the frequency of the square wave and outputs an improved clock signal.
In the clock improvement circuit provided by the embodiment of the present invention, the input end of the control circuit 500 inputs a clock signal, the output end outputs a control signal, and the control signal is used to control the voltage reference generation circuit and the sawtooth wave generation and voltage comparison circuit, so that the voltage reference generation circuit 200 can receive the first current of the current mirror 100, provide a comparison reference level for the sawtooth wave generation and voltage comparison circuit 300 according to the first current, and enable the first input end of the sawtooth wave generation and voltage comparison circuit 300 to receive the comparison reference level, the second input end to receive the second current of the current mirror, generate a sawtooth wave signal according to the second current, and output a square wave according to the comparison reference level and the comparison result of the sawtooth wave signal. As can be seen from the above, the clock signal outputs a square wave after passing through the voltage reference generating circuit 200 and the sawtooth wave generating and voltage comparing circuit 300, and the frequency dividing circuit 400 divides the frequency of the received square wave and outputs an improved clock signal, so that the clock improving circuit provided in the embodiment of the present invention improves the jitter of the clock after passing through the control circuit 500, the voltage reference generating circuit 200, the sawtooth wave generating and voltage comparing circuit 300, and the frequency dividing circuit 400 in sequence.
Further, the clock jitter improving circuit provided by the embodiment of the present invention includes a current mirror 100, a voltage reference generating circuit 200, a sawtooth wave generating and voltage comparing circuit 300, a frequency dividing circuit 400, and a control circuit 500, and compared with the phase-locked loop of the conventional PLL circuit, the clock jitter improving circuit has the advantages of fewer circuit modules and simple circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a clock jitter improving circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another structure of a clock jitter improving circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another structure of a clock jitter improving circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a clock jitter improving circuit according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a control circuit in the clock jitter improving circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of control signals provided by the present invention corresponding to the embodiment of FIG. 4;
FIG. 7 is a waveform diagram of a Sawtoth signal according to the embodiment of FIG. 4;
FIG. 8 is a signal waveform diagram of Vout _ comp corresponding to the embodiment of FIG. 4 provided by the present invention;
FIG. 9 is a waveform diagram of the output clock CLK _ OUT according to the embodiment of FIG. 4;
fig. 10 is a flowchart illustrating a clock jitter improving method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 shows a schematic diagram of a clock jitter improvement circuit, which includes a current mirror 100, a voltage reference generation circuit 200, a sawtooth generation and voltage comparison circuit 300, a frequency division circuit 400, and a control circuit 500.
A first input terminal of the voltage reference generating circuit 200 is connected to the current mirror 100, a second input terminal of the voltage reference generating circuit 200 is connected to an output terminal of the control circuit 500, and an output terminal of the voltage reference generating circuit 200 is connected to a first input terminal of the sawtooth wave generating and voltage comparing circuit 300.
A second input terminal of the sawtooth wave generating and voltage comparing circuit 300 is connected to the current mirror 100, a third input terminal of the sawtooth wave generating and voltage comparing circuit 300 is connected to an output terminal of the control circuit 500, and an output terminal of the sawtooth wave generating and voltage comparing circuit 300 is connected to the frequency dividing circuit 400.
Wherein:
the input end of the control circuit 400 inputs a clock signal, and the output end of the control circuit 400 outputs a control signal;
the voltage reference generating circuit 200 receives a first current of the current mirror 100 according to the control signal, and the voltage reference generating circuit 200 provides a comparison reference level for the sawtooth wave generating and voltage comparing circuit 300 according to the first current;
a third input end of the sawtooth wave generating and voltage comparing circuit 300 receives the control signal, a first input end of the sawtooth wave generating and voltage comparing circuit 300 receives a comparison reference level according to the control signal, a second input end of the sawtooth wave generating and voltage comparing circuit 300 receives a second current of the current mirror, a capacitor is charged by the second current to generate a sawtooth wave signal, and a square wave is output according to the comparison reference level and a comparison result of the sawtooth wave signal;
the frequency dividing circuit 400 divides the frequency of the square wave and outputs an improved clock signal.
In the clock improvement circuit provided by the embodiment of the present invention, the input end of the control circuit 500 inputs a clock signal, the output end outputs a control signal, and the control signal is used to control the voltage reference generation circuit and the sawtooth wave generation and voltage comparison circuit, so that the voltage reference generation circuit 200 can receive the first current of the current mirror 100, provide a comparison reference level for the sawtooth wave generation and voltage comparison circuit 300 according to the first current, and enable the first input end of the sawtooth wave generation and voltage comparison circuit 300 to receive the comparison reference level, the second input end to receive the second current of the current mirror, generate a sawtooth wave signal according to the second current, and output a square wave according to the comparison reference level and the comparison result of the sawtooth wave signal. As can be seen from the above, the clock signal outputs a square wave after passing through the voltage reference generating circuit 200 and the sawtooth wave generating and voltage comparing circuit 300, and the frequency dividing circuit 400 divides the frequency of the received square wave and outputs an improved clock signal, so that the clock improving circuit provided in the embodiment of the present invention improves the jitter of the clock after passing through the control circuit 500, the voltage reference generating circuit 200, the sawtooth wave generating and voltage comparing circuit 300, and the frequency dividing circuit 400 in sequence.
Further, the clock jitter improving circuit provided by the embodiment of the present invention includes a current mirror 100, a voltage reference generating circuit 200, a sawtooth wave generating and voltage comparing circuit 300, a frequency dividing circuit 400, and a control circuit 500, and compared with the phase-locked loop of the conventional PLL circuit, the clock jitter improving circuit has the advantages of fewer circuit modules and simple circuit.
Referring to fig. 2, in other embodiments of the present invention, the clock jitter improvement circuit further includes a reference current source 600.
The current mirror 100, the voltage reference generation circuit 200, and the sawtooth wave generation and voltage comparison circuit 300 are respectively connected to the reference current source 600, and the current mirror 100 outputs a current proportional to the reference current source 600 to the voltage reference generation circuit 200 and the sawtooth wave generation and voltage comparison circuit 300. It should be noted that if the current mismatch is generated, the charging voltage will be deviated, and finally the output clock frequency will be deviated from the theoretical value, so the current mirror 100 outputs a current proportional to the reference current source 600 to the voltage reference generating circuit 200 and the sawtooth wave generating and voltage comparing circuit 300.
Referring to fig. 3, in other embodiments of the present invention, the voltage reference generating circuit 200 may include a first charging branch 201 and a second charging branch 202.
The first charging branch 201 provides a comparison reference level for the sawtooth wave generation and voltage comparison circuit 300, and since the circuit may have leakage current, the comparison reference level will slowly decrease after a period of charging, and finally affect the normal operation of the circuit, in order to solve the problem, a second charging branch 202 is arranged in the voltage reference generation circuit 200, wherein the first charging branch 201 is connected in parallel with the second charging branch 202, the input end of the first charging branch 201 and the input end of the second charging branch 202 are respectively connected with the current mirror 100, and the second charging branch 202 charges the first charging branch 201 periodically.
Further, a switch may be disposed between the second charging branch 202 and the current mirror 100, so that the current mirror 100 performs periodic charging and discharging on the second charging branch 202 through closing of the switch, and the closing of the switch may be controlled by a control signal output by the control circuit.
In addition, a switch may be disposed between the first charging branch 201 and the second charging branch 202, and after the second charging branch 202 is charged each time, the switch between the first charging branch 201 and the second charging branch 202 is turned on, so that the second charging branch 202 periodically charges the first charging branch 201, thereby canceling the influence of leakage current on the comparison reference level, and further enabling the comparison reference level to have a stable output value. Wherein, the closing of the switch between the first charging branch 201 and the second charging branch 202 can be controlled by the control signal output by the control circuit.
It should be further added that a switch may also be disposed between the first charging branch 201 and the current mirror 100, so that the current mirror 100 performs periodic charging and discharging on the first charging branch 201 through closing of the switch, and the closing of the switch may be controlled by a control signal output by the control circuit.
Referring to fig. 4, the embodiment of the invention provides a specific implementation circuit of the clock jitter improving circuit, which includes a current mirror 100, a voltage reference generating circuit 200, a sawtooth wave generating and voltage comparing circuit 300, a frequency dividing circuit 400, and a reference current source 600, and a control circuit is not shown in fig. 4.
The voltage reference generating circuit 200 includes a first charging branch and a second charging branch, the first charging branch includes a first capacitor C1 and a first switch S1, and the first capacitor C1 and the first switch S1 are connected in series via a first common terminal.
The second charging branch comprises a second capacitor C2 and a second switch S2, and the second capacitor C2 and the second switch S2 are connected in series through a second common terminal.
The voltage reference generating circuit 200 further includes a third switch S3.
A first terminal of the third switch S3 is connected to the first common terminal, and a second terminal of the third switch S3 is connected to the second common terminal;
the first common terminal is connected to the sawtooth wave generation and voltage comparison circuit 300 as an output terminal of the voltage reference generation circuit 200.
Further, the voltage reference generating circuit 200 may further include a fourth switch S4 and a fifth switch S5.
The fourth switch S4 is used for resetting the voltage of the second capacitor C2 before charging;
the fifth switch S5 is connected in parallel with the first capacitor C1, and the fifth switch S5 is used for voltage reset of the first capacitor C1 before charging.
Referring also to fig. 4, the sawtooth wave generation and voltage comparison circuit 300 includes a comparator 301, a third capacitor C3, a sixth switch S6, and a seventh switch S7.
A first end of the third capacitor C3 is connected to the current mirror 100, and a second end of the third switch S3 is connected to the ground terminal of the reference current source;
the inverting input terminal of the comparator 301 is connected to the first common terminal, the positive input terminal of the comparator 301 is connected to the first terminal of the third capacitor C3, and the level output by the output terminal of the comparator 301 controls the on/off of the seventh switch S7;
a sixth switch S6 and a seventh switch S7 are respectively connected with the third capacitor C3 in parallel,
wherein:
the sixth switch S6 is used for voltage reset of the third capacitor C3 before charging, and the seventh switch S7 is used for periodic voltage reset of the third capacitor C3 during normal operation.
Further, fig. 4, fig. 5, and fig. 6 are used as examples to explain a specific implementation process of the circuit operating principle of the present invention, where fig. 4 is a core circuit, fig. 5 is a control circuit, and fig. 6 is a timing sequence of a control signal generated by the control circuit.
The control circuit receives a clock signal CLK _ IN and outputs 6 control signals S1-S6, which are used for controlling the on-off of corresponding identification switches S1-S6 IN the core circuit, that is, the control signal controls the on-off of the switch S1, the control signal S2 controls the on-off of the switch S2, and IN turn, the control signal S6 controls the on-off of the switch S6.
For convenience of analysis, all switches in the figure are closed when the control signal is at a high level and are opened when the control signal is at a low level.
The circuit working state can be divided into a Reset state and a normal working state through the Reset signal Reset, wherein the Reset signal Reset is at a high level in the Reset state, and the Reset signal Reset is changed from the high level to a low level in the normal working state.
Wherein the Reset signal Reset is input to the frequency dividing circuit 300.
When the operating state is the Reset state, the Reset signal Reset is at a high level, the control signals S1 and S2 are at a low level at this time, and S3, S4, S5 and S6 are at a high level, so that the switches S1 and S2 are opened, the switches S3, S4, S5 and S6 are closed, and the voltages at the two ends of the capacitors C1, C2 and C3 are discharged to zero through the switches, that is, the voltage signals Vref and sawthoth in fig. 5 are zero.
Meanwhile, in the reset state, the frequency divider 300 is in the reset state and outputs a fixed level value.
When the operating state is the normal operating state, the Reset signal Reset changes from the high level to the low level, the control signal S1 starts to change to the high level at the first rising edge or falling edge after the Reset signal is at the low level, and the time for keeping the high level is th = N × T, where T is the period of the input clock CLK _ IN, N is half of the ratio of the clocks of S2, S3, S4 to the period of CLK _ IN, and N is an integer greater than 0. After the time th, S1 goes low and remains unchanged, and the control signals S2, S3, and S4 change periodically with a period of 2 × N × T, and the phase relationship between the control signals is shown in fig. 6.
The capacitor C1 is charged for a time th by the current source I1, and the reference voltage generation circuit obtains a reference voltage Vref = I1 th/C1, where I1 is an input current value of the current source and C1 is a capacitance value of the capacitor C1.
C1 is charged through switch S1 for a length of time th = N × T. Ideally, the reference voltage Vref will remain unchanged, but after S1 is turned off, if there is no leakage charge supplemented by other current sources, the voltage at C1 will drop slowly, and when the voltage drops to a certain threshold, the normal operation of the circuit will be affected, and to solve this problem, a charging circuit composed of several devices, i.e., a capacitor C2, a switch S2, and a switch S3, is introduced into the circuit, and the charging circuit obtains a charging voltage consistent with the reference voltage Vref by periodically charging and discharging C2. After each time the C1 charging is completed, the switch S3 is turned on for a time corresponding to t2 in fig. 6, so that the C2 charges the C1 to counteract the effect of the leakage current on Vref, thereby keeping Vref substantially unchanged.
The values of the currents I1, I2 and the capacitors C1 and C2 have great flexibility, but the currents I1, I2 and C1 and C2 need to satisfy the following relation that I1/C1= I2/C2. Assuming that I1= I2 and C1= C2, the voltage value of the reference voltage Vref is Vref = I1 × th/C1= I1 × N × T/C1 after a sufficiently long settling time.
Further, the circuit may further include a switch S4, and the switch S4 is used for voltage resetting of the capacitor C2 before charging.
It should be noted that, the selection of the 5 time parameters t 1-t 5 in fig. 6 is not strictly limited, and can be adjusted according to the actual circuit.
The sawtooth wave generation and voltage comparison circuit 300 is composed of a switch S6, a switch S7, a capacitor C3 and a comparator 301. When the operation state of the sawtooth wave generation and voltage comparison circuit 300 is the normal operation state, the current I3 charges the capacitor C3, when the charging voltage exceeds Vref, the comparator 301 will flip from low level to high level, the output terminal of the comparator 301 outputs high level, this high causes switch S7 to close, re-discharging the voltage on capacitor C3 to zero, comparator 301 will switch back from high to low, switch S7 will open again, current source I3 will begin a new charge on capacitor C3, and so on, at the Sawtooth node a Sawtooth wave is obtained as shown in fig. 7, the maximum value of which is Vref, at the same time, the square wave signal shown in fig. 8 will be obtained at the node Vout _ comp, and in an actual circuit, the duty ratio of the square wave signal is very small, i.e., tp < < tl, the period Tsaw tl = Vref C3/I3 of the Sawtooth wave Sawtooth and the square wave Vout _ comp.
It should be noted that, in the actual circuit implementation, the values of C3 and I3 can be flexibly selected.
Further, the switch S6 is closed during the initial stage of the circuit, in order to discharge the charge on the capacitor C3. The moment when S3 turns off cannot be earlier than the moment when the capacitor C1 completes the first charging through the switch S1 to ensure that the reference voltage Vref at the negative input of the comparator has stabilized. In addition, switch S5 is closed during the initial stages of circuit operation in order to drain the charge on capacitor C1.
By the frequency dividing circuit 400, the clock signal CLK _ OUT can be recovered from Vout _ comp output from the output terminal of the sawtooth wave generation and voltage comparison circuit 300, CLK _ OUT being shown with reference to fig. 9, while the frequency dividing circuit 400 ensures that the duty ratio of the output clock is 50%.
Assuming that the frequency division coefficient of the frequency division circuit 400 is K, the period of the divided clock signal is Tout=Tsaw*K。
Furthermore, by setting the proper circuit parameters, the clock signal CLK _ OUT with the frequency consistent with that of the input clock CLK _ IN can be recovered at the clock output end by the circuit.
The specific process is as follows:
from the above analysis, it can be seen that as long as the circuit parameters satisfy the formula
The circuit can recover the output clock CLK _ OUT with the same frequency from the input clock CLK _ IN.
Further, in most cases, the clock jitter satisfies the gaussian distribution, and therefore, it is assumed that the clock jitter satisfies the characteristics of the gaussian distribution. Assuming the standard deviation of the input clock jitter is δ (T), the voltage reference Vref indirectly controlled by the input clock will generate voltage noise following gaussian distribution, the noise average power will change with each C2 charging C1, but after a sufficient number of charges, the average noise power of Vref will tend to a stable value, namely:
in the formula,
for the noise average power when Vref is stable,
the noise voltage at the completion of the first charge of Vref. This noise voltage will be converted back to the jitter of Vout _ comp by the sawtooth generation and voltage comparison circuit and then converted to the jitter of the output clock after passing through the frequency division circuit 400. When analyzing the jitter of the noise voltage converted into Vout _ comp by the Sawtooth wave generation and voltage comparison circuit, the noise voltage can be equivalent to the Sawtooth node, and thus the jitter δ of Vout _ comp can be analyzed (T1), specifically derived as:
after the jitter δ (T1) of Vout _ comp passes through the frequency divider circuit, the jitter obtained at the CLK _ OUT port is δ (T2), specifically:
is composed of
It can be seen that the jitter of the output clock decreases with the increase of the N, K product, and when the product is larger, the jitter delta (T2) of the output clock will be significantly smaller than the jitter delta (T) of the input clock, so increasing the N, K value can effectively reduce the jitter of the input clock.
Referring to fig. 10, fig. 10 is a flow chart of a clock jitter improving method applied to a clock jitter improving circuit, the circuit including a current mirror, a voltage reference generating circuit, a sawtooth wave generating and voltage comparing circuit, a frequency dividing circuit, and a control circuit, the method including:
step 110: the control circuit receives the clock signal and outputs a control signal.
Step 120: the voltage reference generating circuit receives a first current of the current mirror according to the control signal and provides a comparison reference level for the sawtooth wave generating and voltage comparing circuit according to the first current.
Step 130: the third input end of the sawtooth wave generation and voltage comparison circuit receives the control signal, the first input end of the sawtooth wave generation and voltage comparison circuit receives the comparison reference level according to the control signal, the second input end of the sawtooth wave generation and voltage comparison circuit receives the second current of the current mirror, the capacitor is charged by the second current to generate a sawtooth wave signal, and a square wave is output according to the comparison reference level and the comparison result of the sawtooth wave signal.
Step 140: the frequency dividing circuit divides the frequency of the square wave and outputs an improved clock signal.
According to the clock improvement method provided by the embodiment of the invention, a clock signal is input at the input end of a control circuit, a control signal is output at the output end of the control circuit, and the control signal is used for controlling a voltage reference generation circuit and a sawtooth wave generation and voltage comparison circuit, so that the voltage reference generation circuit can receive a first current of a current mirror and provide a comparison reference level for the sawtooth wave generation and voltage comparison circuit according to the first current, and the first input end of the sawtooth wave generation and voltage comparison circuit can receive the comparison reference level, a second input end of the sawtooth wave generation and voltage comparison circuit can receive a second current of the current mirror and generate a sawtooth wave signal according to the second current, and a square wave is output according to the comparison reference level and the comparison result of the sawtooth wave signal.
Therefore, the clock improvement circuit provided by the embodiment of the invention improves the clock jitter after sequentially passing through the control circuit, the voltage reference generation circuit, the sawtooth wave generation and voltage comparison circuit and the frequency division circuit.
Furthermore, the clock jitter improving method provided by the embodiment of the invention is applied to a clock jitter improving circuit, and the circuit comprises a current mirror, a voltage reference generating circuit, a sawtooth wave generating and voltage comparing circuit, a frequency dividing circuit and a control circuit, so that the clock jitter improving circuit applied by the clock jitter improving method has the advantages of less circuit modules and simple circuit compared with a phase-locked loop of the conventional PLL circuit.
Those skilled in the art will appreciate that the drawings are merely schematic representations of one preferred embodiment and that the blocks or flow diagrams in the drawings are not necessarily required to practice the present invention.
Those skilled in the art will appreciate that the modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, and may be correspondingly changed in one or more devices different from the embodiments. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A clock jitter improvement circuit is characterized by comprising a current mirror, a voltage reference generation circuit, a sawtooth wave generation and voltage comparison circuit, a frequency division circuit and a control circuit;
the first input end of the voltage reference generating circuit is connected with the current mirror, the second input end of the voltage reference generating circuit is connected with the output end of the control circuit, and the output end of the voltage reference generating circuit is connected with the first input end of the sawtooth wave generating and voltage comparing circuit;
the second input end of the sawtooth wave generating and voltage comparing circuit is connected with the current mirror, the third input end of the sawtooth wave generating and voltage comparing circuit is connected with the output end of the control circuit, and the output end of the sawtooth wave generating and voltage comparing circuit is connected with the frequency dividing circuit;
wherein:
the input end of the control circuit inputs a clock signal, and the output end of the control circuit outputs a control signal;
the voltage reference generating circuit receives a first current of the current mirror according to the control signal and provides a comparison reference level for the sawtooth wave generating and voltage comparing circuit according to the first current;
the third input end of the sawtooth wave generation and voltage comparison circuit receives the control signal, the first input end of the sawtooth wave generation and voltage comparison circuit receives the comparison reference level according to the control signal, the second input end of the sawtooth wave generation and voltage comparison circuit receives the second current of the current mirror, the second current charges a capacitor to generate a sawtooth wave signal, and a square wave is output according to the comparison reference level and the comparison result of the sawtooth wave signal;
the frequency dividing circuit divides the frequency of the square wave and outputs an improved clock signal.
2. The circuit of claim 1, further comprising a reference current source;
the current mirror, the voltage reference generating circuit, the sawtooth wave generating and voltage comparing circuit are respectively connected with the reference current source;
the current mirror outputs a current proportional to the reference current source to the voltage reference generation circuit, the sawtooth wave generation and voltage comparison circuit.
3. The circuit of any of claims 1-2, wherein the voltage reference generating circuit comprises a first charging branch, a second charging branch;
wherein,
the first charging branch is connected with the second charging branch in parallel;
the input end of the first charging branch and the input end of the second charging branch are respectively connected with the current mirror;
the second charging branch circuit carries out periodic charging on the first charging branch circuit.
4. The circuit of claim 3, wherein the first charging branch comprises a first capacitor and a first switch, and wherein the first capacitor and the first switch are connected in series via a first common terminal;
the second charging branch comprises a second capacitor and a second switch, and the second capacitor and the second switch are connected in series through a second common terminal;
the voltage reference generation circuit further comprises a third switch;
a first end of the third switch is connected with the first common end, and a second end of the third switch is connected with the second common end;
the first common terminal is used as the output terminal of the voltage reference generating circuit and is connected with the sawtooth wave generating and voltage comparing circuit.
5. The circuit of claim 4, wherein the voltage reference generation circuit further comprises a fourth switch and a fifth switch;
the fourth switch is used for resetting the voltage of the second capacitor before charging;
the fifth switch is connected in parallel with the first capacitor, and the fifth switch is used for resetting the voltage of the first capacitor before charging.
6. The circuit of claim 5, wherein the sawtooth wave generation and voltage comparison circuit comprises a comparator, a third capacitor, a sixth switch, and a seventh switch;
the first end of the third capacitor is connected with the current mirror, and the second end of the third switch is connected with the grounding end of the reference current source;
an inverting input end of the comparator is connected with the first common end, a positive input end of the comparator is connected with the first end of the third capacitor, and the level output by the output end of the comparator controls the on-off of the seventh switch;
the sixth switch and the seventh switch are respectively connected with the third capacitor in parallel, wherein:
the sixth switch is used for voltage resetting of the third capacitor before charging, and the seventh switch is used for periodic voltage resetting of the third capacitor during normal work.
7. A clock jitter improving method is applied to a clock jitter improving circuit, the circuit comprises a current mirror, a voltage reference generating circuit, a sawtooth wave generating and voltage comparing circuit, a frequency dividing circuit and a control circuit, and the method comprises the following steps:
the control circuit receives a clock signal and outputs a control signal;
the voltage reference generating circuit receives a first current of the current mirror according to the control signal and provides a comparison reference level for the sawtooth wave generating and voltage comparing circuit according to the first current;
the third input end of the sawtooth wave generation and voltage comparison circuit receives the control signal, the first input end of the sawtooth wave generation and voltage comparison circuit receives the comparison reference level according to the control signal, the second input end of the sawtooth wave generation and voltage comparison circuit receives the second current of the current mirror, the second current charges a capacitor to generate a sawtooth wave signal, and a square wave is output according to the comparison reference level and the comparison result of the sawtooth wave signal;
the frequency dividing circuit divides the frequency of the square wave and outputs an improved clock signal.
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| CN110677143A (en) * | 2019-10-30 | 2020-01-10 | 深圳英集芯科技有限公司 | Sawtooth wave generating circuit and buck-boost converter |
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