CN103327587B - A kind of terminal sleep cycle control methods and device - Google Patents
A kind of terminal sleep cycle control methods and device Download PDFInfo
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- CN103327587B CN103327587B CN201310206822.0A CN201310206822A CN103327587B CN 103327587 B CN103327587 B CN 103327587B CN 201310206822 A CN201310206822 A CN 201310206822A CN 103327587 B CN103327587 B CN 103327587B
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Abstract
The invention provides a kind of terminal sleep cycle control methods and device.Described method includes: after receiving the instruction entering sleep pattern, carry out timing by high frequency clock；When determine arrive the first timing point by described high frequency clock timing time, carry out timing by low-frequency clock, and triggering terminal enter sleep pattern；When determine arrive the second timing point by described low-frequency clock timing time, carry out timing by described high frequency clock；When determining by described high frequency clock timing arrival three timing point, triggering terminal enters mode of operation, starts to carry out data interaction with base station.The present invention can extend the sleep cycle of terminal, reduces the power consumption of terminal.
Description
Technical field
The present invention relates to mobile communication technology field, particularly relate to a kind of terminal sleep cycle control methods, and a kind of terminal sleep period control device.
Background technology
LTE (Long Term Evolution, Long Term Evolution project) it is widely used as a kind of forth generation wireless telecommunications (3G) standard, the electronic equipment using LTE communication standard can provide the user the network service of fast and stable, there is the features such as receiving velocity height, availability of frequency spectrum height and receiver are simple.
In LTE system, must carry out correct time with base station eNB synchronization during user terminal UE work, i.e. the moment keeps the state transmitting the subframe alignment of data.In the operational mode, there is single time block in UE receiver, use high frequency clock to produce sequential and the timing of various needs, the operation that high frequency clock is system provides precise time reference, it can be ensured that the normal transceiving data of UE.
UE, when need not monitor channel information, can close receiver and enter sleep pattern, and in a sleep mode, DRX (Discontinuous Reception, the discontinuous acceptance) cycle that UE configures according to network side carries out sleep awakening process.In order to reduce system power dissipation as far as possible, the high frequency clock source of closed system can be closed, including high-frequency oscillating circuits and PLL, use low-frequency clock timing.After DRX sleep cycle terminates, need from sleep, to wake up UE up, and start receiver immediately to start working.
Low-frequency clock (32.768KHZ) is used to replace the high frequency clock that precision is higher under sleep pattern, when starting to transmit data when UE wakes up up, due to the inaccuracy of time, the loss of the synchronizing informations such as the sub-frame boundary transmitting data and frame number can be caused, thus need re-synchronization.
And the process of re-synchronization needs high frequency clock, and require that UE is in mode of operation, therefore, needing to terminate in advance sleep pattern, thus, the process of re-synchronization really shortens the length of one's sleep of terminal, owing to the time of re-synchronization can reach Millisecond, for shorter DRX sleep cycle, system even cannot be introduced into sleep, is unfavorable for the low-power consumption of terminal.
Summary of the invention
The technical problem to be solved is to provide a kind of terminal sleep cycle control methods, to extend the sleep cycle of terminal, reduces the power consumption of terminal.
Present invention also offers a kind of terminal sleep period control device, in order to ensure said method application in practice and realization.
In order to solve the problems referred to above, the invention discloses a kind of terminal sleep cycle control methods, including:
After receiving the instruction of entrance sleep pattern, carry out timing by high frequency clock；
When determine arrive the first timing point by described high frequency clock timing time, carry out timing by low-frequency clock, and triggering terminal enter sleep pattern, wherein, described first timing point is concordant with the first edge of described low-frequency clock；
When determine arrive the second timing point by described low-frequency clock timing time, timing is carried out by described high frequency clock, wherein, described second timing point is concordant with the second edge of described low-frequency clock, the duration of described second timing point configures according to the sleep cycle T0 of described terminal with difference T1 of the duration of described first timing point, and the difference of T0 Yu T1 is less than the first pre-set threshold value；
When determining by described high frequency clock timing arrival three timing point, triggering terminal enters mode of operation, starts to carry out data interaction, wherein, time a length of described sleep cycle T0 of described 3rd timing point with base station.
Preferably, configured difference T1 of the duration of the first timing point and the second timing point according to the sleep cycle T0 of described terminal by following steps, including:
By sleep cycle T0 divided by the time-count cycle of low-frequency clock, obtain first number of low-frequency clock time-count cycle；
Second number of the time-count cycle of low-frequency clock is determined with the difference of the second pre-set threshold value, using the product of described second number and low-frequency clock as the first timing point and difference T1 of the duration of the second timing point according to first number of low-frequency clock time-count cycle.
Preferably, after described first edge is time zero, first edge of described low-frequency clock.
Preferably, after described first edge is time zero, the n-th edge of described low-frequency clock, N is positive integer；
Described method also includes, is determined the first edge of described low-frequency clock by following steps:
Calculate described sleep cycle T0 and deduct the difference of the duration of the second timing point and difference T1 of the duration of described first timing point；
Time zero described in selected distance is less than first edge as described low-frequency clock, the edge of T0 Yu T1 difference.
Preferably, the first edge or second edge of described low-frequency clock carries out sampling by described high frequency clock to described low-frequency clock and determines.
Present invention also offers a kind of terminal sleep period control device, including:
First high frequency timing module, after receiving the instruction entering sleep pattern, timing is carried out by high frequency clock, when determining by described high frequency clock timing to the first timing point, stop carrying out timing by described high frequency clock, wherein, described first timing point is concordant with the first edge of described low-frequency clock；
Low frequency timing module, for carrying out timing by low-frequency clock, and triggering terminal enters sleep pattern, when determining by described low-frequency clock timing to the second timing point, stopping carrying out timing by described low-frequency clock, wherein, described second timing point is concordant with the second edge of described low-frequency clock, the duration of described second timing point configures according to described sleep cycle T0 with difference T1 of the duration of described first timing point, and the difference of T0 Yu T1 is less than the first pre-set threshold value；
Second high frequency timing module, for by using described high frequency clock to carry out timing, when determine by described high frequency clock timing arrive three timing points time, stop carry out timing by described high frequency clock, described 3rd timing point time a length of described terminal sleep cycle T0；
Work trigger module, is used for triggering described terminal and enters mode of operation, starts to carry out data interaction with base station.
Preferably, described device also includes:
Time distribution module, for configuring difference T1 of the duration of the first timing point and the second timing point according to the sleep cycle T0 of described terminal；
Distribution of described time module includes:
First number determines submodule, is used for sleep cycle T0 divided by the time-count cycle of low-frequency clock, obtains first number of low-frequency clock time-count cycle；
Second number determines submodule, for determining second number of the time-count cycle of low-frequency clock with the difference of the second pre-set threshold value according to first number of low-frequency clock time-count cycle, using the product of described second number and low-frequency clock as the first timing point and difference T1 of the duration of the second timing point.
Preferably, described first high frequency timing module, specifically for when timing to time zero after, when first edge of described low-frequency clock is concordant, determine when arriving the first timing point by described high frequency clock timing.
Preferably, described first high frequency timing module, specifically for when timing to time zero after, when the n-th edge of described low-frequency clock is concordant, determine that when arriving the first timing point by described high frequency clock timing, wherein, N is positive integer；
Described device also includes, edge determines module, for determining difference T1 of the duration according to described sleep cycle T0 and the second timing point and the duration of described first timing point, determine the first edge of described low-frequency clock, after described first edge is time zero, the n-th edge of described low-frequency clock；
Described edge determines that module includes:
Mathematic interpolation submodule, deducts the difference of the duration of the second timing point and difference T1 of the duration of described first timing point for calculating described sleep cycle T0；
Submodule is chosen at edge, is less than first edge as described low-frequency clock, the edge of T0 Yu T1 difference for time zero described in selected distance.
Preferably, described first high frequency timing module by described high frequency clock described low-frequency clock sampled determine timing to the first timing point with the first edge flush of described low-frequency clock, described low frequency timing module by described high frequency clock described low-frequency clock sampled determine timing extremely with the second timing point of the second edge flush of described low-frequency clock.
Compared with prior art, the invention have the advantages that
According to the embodiment of the present invention, after receiving the instruction entering sleep pattern, by high frequency clock timing to the first timing point, then begin through low-frequency clock and carry out timing, and enter sleep pattern, when low-frequency clock timing arrives the second timing point, timing is carried out by high frequency clock, until arriving the 3rd timing point, triggering terminal enters sleep pattern, starts to recover the data interaction with base station.The second timing point that the first timing point started due to the timing of low-frequency clock and timing terminate is the edge of low-frequency clock, therefore, low-frequency clock timing in sleep pattern is accurately, not arriving the part at low-frequency clock edge and reach the time after T1 by high frequency clock timing, thereby may be ensured that the timing accuracy under whole sleep pattern；In the case of accurate timing, enter sleep pattern from certain sub-frame boundary receiving data, and sleep cycle is the integral multiple of subframe, then, after can ensure that end sleep cycle, receiving data is still sub-frame boundary.
In sum, use the method for the embodiment of the present invention without carrying out re-synchronization between end sleep pattern, and the difference of sleep cycle T0 and the timing duration T1 of low-frequency clock is less than the first pre-set threshold value, time compared to the re-synchronization of Millisecond, the embodiment of the present invention can extend the sleep cycle of terminal, reduces the power consumption of terminal.
Further, the method using the embodiment of the present invention, can the most self-defined DRX sleep bout length, the actual length of one's sleep can be set in a register according to time of sleep cycle, apply for reality and provide bigger motility.
Accompanying drawing explanation
Fig. 1 is the flow chart of the present invention a kind of terminal sleep cycle control methods embodiment 1；
Fig. 2 is the flow chart of the present invention a kind of terminal sleep cycle control methods embodiment 2；
Fig. 3 is the structured flowchart of the present invention a kind of terminal sleep period control device embodiment 1；
Fig. 4 is the structured flowchart of the present invention a kind of terminal sleep period control device embodiment 2；
Fig. 5 is the timing schematic diagram of terminal sleep mode in the embodiment of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, the present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings.
With reference to Fig. 1, it is shown that the flow chart of a kind of terminal sleep cycle control methods embodiment 1 of the present invention, specifically may comprise steps of:
Step 101, receive enter sleep pattern instruction after, carry out timing by high frequency clock.
Terminal can enter sleep pattern when need not monitor channel information, and is generated into the instruction of sleep pattern, it is also possible to submitted to the instruction of entrance sleep pattern by the interface of terminal preset by user.Terminal includes two elapsed time clocks, and one is low frequency elapsed time clock, and one is high frequency elapsed time clock, in the embodiment of the present invention, after receiving the instruction entering sleep pattern, carries out timing by high frequency clock.Owing to terminal is when being introduced into sleep pattern and being in running order, carries out timing by high frequency clock, therefore, after receiving the instruction entering sleep pattern, continue through high frequency clock and carry out timing.
Step 102, when determine arrive the first timing point by high frequency clock timing time, carry out timing by low-frequency clock, and triggering terminal enter sleep pattern, wherein, the first timing point is concordant with the first edge of low-frequency clock.
The timing time of high frequency clock is as the criterion with the first timing point, can use low-frequency clock instead and start timing, and triggering terminal enters sleep pattern after arriving the first timing point.Wherein, first timing point is the first edge of low-frequency clock, first edge can be rising edge or the trailing edge of low-frequency clock, during owing to receiving the instruction entering sleep pattern, the edge of low-frequency clock can't be in most cases, sleep pattern is entered in the case of non-edge, using low-frequency clock timing, the timing uncertainty under sleep pattern can be caused true, the embodiment of the present invention enters sleep pattern from the edge of low-frequency clock, thereby may be ensured that the timing of low-frequency clock is accurately when entering sleep pattern.
In embodiments of the present invention, the first timing point i.e. edge of low-frequency clock can carry out sampling by high frequency clock to low-frequency clock and determines.
Step 103, when determine arrive the second timing point by low-frequency clock timing time, timing is carried out by high frequency clock, wherein, second timing point is concordant with the second edge of low-frequency clock, difference T1 of the duration of the second timing point and the duration of the first timing point configures according to the sleep cycle T0 of terminal, and the difference of T0 Yu T1 is less than the first pre-set threshold value.
In a sleep mode, terminal carries out timing by low-frequency clock, and the timing end point of low-frequency clock is as the criterion with the second timing point, and wherein, the second timing point is the second edge of low-frequency clock, and the second edge can be rising edge or the trailing edge of low-frequency clock.In embodiments of the present invention, the second timing point i.e. edge of low-frequency clock can carry out sampling by high frequency clock to low-frequency clock and determines.
Wherein, the timing duration of the first timing point refers to, from the beginning of the instruction receiving entrance sleep pattern the time zero beginning to use high frequency clock timing, and the time between the first timing point；Equally, the timing duration of the second timing point refers to, from the beginning of the instruction receiving entrance sleep pattern the time zero beginning to use high frequency clock timing, and the time between the second timing point.
In the embodiment of the present invention, first edge and the second edge can be rising edge, or it is trailing edge, in this case, the duration of the first timing point and the integral multiple that difference is low-frequency clock time-count cycle of the duration of the second timing point, first edge and the second edge can also one be rising edge one be trailing edge, in this case, the difference of the duration of the first timing point and the duration of the second timing point is that the integral multiple of low-frequency clock time-count cycle adds half period.Use another edge of low-frequency clock timing tremendously low frequency clock, it is ensured that the low-frequency clock timing in sleep pattern is accurately.
As it is shown in figure 5, give the timing schematic diagram of terminal sleep mode in the embodiment of the present invention.The sub-frame boundary that upwards arrow logo is data in SUBFRAME_BOUNDARY above Fig. 5, mid portion corresponds to high frequency clock (SYS_CLK, system clock) timing schematic diagram, lower section low-frequency clock (Real-Time Clock, RTC) timing schematic diagram, the problem lost in order to avoid synchronizing information, sleep cycle (DRX SLEEP INTERVAL), from the beginning of sub-frame boundary, terminates at sub-frame boundary.
B is the sleep cycle T0 arranged, what the starting point of sleep cycle was corresponding is certain subframe a receiving data, correspond to the time point b of low-frequency clock, point b is not the edge of low-frequency clock, mode according to background technology, it may appear that the problem that low-frequency clock timing uncertainty really causes needing re-synchronization data.If beginning with low-frequency clock timing from certain edge c, and stopping low-frequency clock timing at another edge d, thereby may be ensured that the accuracy of the timing duration (i.e. time B shown in Fig. 5) of low-frequency clock.
In the embodiment of the present invention, can be according to concrete business or environmental demand, sleep cycle T0 is preset for terminal, the integral multiple of subframe all can be set to, if entering sleep pattern, in the case of accurate timing from current certain sub-frame boundary receiving data due to sleep cycle T0, after ensuring that end sleep cycle, receiving data is still sub-frame boundary, it is not necessary to terminates sleep pattern in advance and carries out re-synchronization, it is ensured that the accuracy of data receiver.
Wherein, time zero first timing point of low-frequency clock and the timing time that difference T1 is low-frequency clock of timing end point the second timing point, it is terminal actual length of one's sleep, T1 configures according to the sleep cycle T0 of terminal, and when distributing the timing time of low-frequency clock, the difference of sleep cycle T0 and the timing time T1 of low-frequency clock need to be met less than the first pre-set threshold value, thereby may be ensured that be longer than in background technology the actual length of one's sleep of terminal carry out re-synchronization after the remaining length of one's sleep, such that it is able to reduction power consumption of terminal, extend the stand-by time of terminal.
In the embodiment of the present invention, difference T1 of the duration of the first timing point and the second timing point can be the integral multiple of low-frequency clock time-count cycle, can be distributed difference T1 of the duration of the first timing point and the second timing point by following steps:
Sub-step S11, by sleep cycle T0 divided by the time-count cycle of low-frequency clock, obtain first number of low-frequency clock time-count cycle；
Sub-step S12, determine second number of the time-count cycle of low-frequency clock with the difference of the second pre-set threshold value according to first number of low-frequency clock time-count cycle, using the product of the second number and low-frequency clock as the first timing point and difference T1 of the duration of the second timing point.
It is possible, firstly, to by sleep cycle T0 divided by the time-count cycle of low-frequency clock, the business obtained of being divided by is that low-frequency clock at most can be with the periodicity of timing, i.e. first number of low-frequency clock time-count cycle.Such as, sleep cycle T0 is 10ms, and can obtain result divided by cycle of low-frequency clock is 327.68, i.e. business is 327, illustrate in sleep cycle low-frequency clock at most can with 327 complete cycles of timing, remainder be 0.68 explanation in addition to complete cycle, low-frequency clock can be with 0.68 cycle of timing.
Owing to the embodiment of the present invention starting timing from certain edge of low-frequency clock, edge herein can be rising edge or trailing edge, and when entering sleep pattern, certain edge of distance low-frequency clock may also have a segment distance, if the length of this segment distance is more than remainder, then low-frequency clock cannot carry out timing according to most periodicities, needs to distribute to the periodicity of low-frequency clock timing.
Such as, the rising edge of current distance low-frequency clock also has 0.1 cycle, the most first uses 0.1 cycle of the complete low-frequency clock of high frequency clock timing, it is also possible to continue to use 327 cycles of low-frequency clock timing；If but the rising edge of current distance low-frequency clock also has 0.8 cycle, then use 0.8 cycle of the complete low-frequency clock of high frequency clock timing, and low-frequency clock cannot 327 complete cycles of timing.
Therefore, in embodiments of the present invention, second number of the time-count cycle of low-frequency clock can be determined according to the difference of first number of low-frequency clock time-count cycle with the second pre-set threshold value, i.e., most periodicities are deducted a preset value, thus ensures that the timing time of low-frequency clock is complete cycle.In concrete implementation, the second pre-set threshold value could be arranged to 2, on the one hand may insure that the timing time of low-frequency clock is complete cycle, and the opposing party can make the timing time of low-frequency clock long, and the actual length of one's sleep of terminal also can be long.
After the number of the time-count cycle determining low-frequency clock, difference T1 of the duration that i.e. can get the first timing point and the second timing point that the second number is multiplied with low-frequency clock, i.e. the timing time T1 of low-frequency clock.
In the embodiment of the present invention, Clocked operation can be completed by the intervalometer of terminal, after distributing T1, can be stored in difference T1 of the duration of the first timing point and the second timing point in the depositor of intervalometer, the difference of T0 Yu T1, the timing time that i.e. high frequency clock is total can also be stored in further.
In concrete implementation, when the difference of the timing time T1 of sleep cycle T0 and low-frequency clock is no less than a cycle, high frequency clock timing can have multiple choices to the edge of low-frequency clock accordingly, i.e., after first edge can be time zero, first edge of low-frequency clock, after the first edge can also be time zero, the n-th edge of low-frequency clock, N is positive integer.
As shown in Figure 5, draw the number of cycles in time B according to the second pre-set threshold value after, as a example by rising edge, first rising edge after b point can be selected as low-frequency clock to start the first edge of timing, it is also possible to select c point to start the first edge of timing as low-frequency clock.
In order to extend the actual length of one's sleep of terminal as far as possible, i.e. extend the timing time of low-frequency clock, first edge of high frequency clock timing tremendously low frequency clock can be used, after i.e. first edge is time zero, first edge of low-frequency clock, so that the actual length of one's sleep of terminal reaches the longest, the energy consumption of terminal is minimum.In concrete implementation, the time at first edge that terminal enters the starting point distance low-frequency clock of sleep pattern every time is not fixed, i.e. the size of the A1 in Fig. 5 is unfixed.
Step 104, when determine by high frequency clock timing arrive three timing points time, triggering terminal enter mode of operation, start with base station carry out data interaction, wherein, time a length of sleep cycle T0 of the 3rd timing point.
After low-frequency clock timing terminates, high frequency clock can be continued through and carry out timing, although now terminal is not the most in sleep, remain in sleep cycle, therefore, after step 103 medium-high frequency clock starts timing, triggering terminal mode of operation can't be entered, but when high frequency clock arrives three timing points, triggering terminal enters mode of operation.
Wherein, the timing duration of the 3rd timing point refers to, from the beginning of the instruction receiving entrance sleep pattern the time zero beginning to use high frequency clock timing, and the time between the 3rd timing point.3rd timing point time a length of sleep cycle T0, i.e. high frequency clock and low-frequency clock total timing time be sleep cycle T0.
As it is shown in figure 5, sleep cycle is divided into three phases, A1 and A2 is the timing time of high frequency clock, and A1 is high frequency clock first stage timing time, and A2 is high frequency clock second stage timing time, and B is the timing time of low-frequency clock.That is to say in sleep cycle when high frequency clock timing arrives the 3rd timing point, total timing time of high frequency clock reaches A, or the timing time of high frequency clock second stage reaches A2, now triggering terminal wakes up up from sleep pattern, enter mode of operation, and channel information can be begun listening for, recover the reception to base station data or transmission.
In concrete implementation, a kind of preferably mode can be, in a step 101 during high frequency clock timing tremendously low frequency clock edge, record the high frequency clock timing time A1 in this stage, then according to difference A of sleep cycle T0 and low-frequency clock timing time T1, subtract each other with the time A1 of high frequency clock first stage, obtain high frequency clock second stage timing time A2, the time point that A2 terminates is the 3rd timing point, and high frequency clock i.e. triggers at second stage timing arrival A2 and wakes up terminal up.
Another kind of preferably mode can be, in a step 101 during high frequency clock timing tremendously low frequency clock edge, record the high frequency clock timing time A1 in this stage, when low-frequency clock timing, record the low-frequency clock timing time B in this stage, then according to the difference of the length of one's sleep with A1 and B, obtaining high frequency clock second stage timing time A2, high frequency clock i.e. triggers at second stage timing arrival A2 and wakes up terminal up.
Terminal receives data by receiver system, receiver ready before therefore if A2 terminates, and high frequency clock source needs ensured ready before the A2 stage starts timing, as shown in Figure 5, high frequency clock terminates the previous cycle in B-stage, i.e. the A2 stage starts the previous cycle and is ready for.
According to the embodiment of the present invention, the time after the part not arriving low-frequency clock edge and another edge reached during low frequency is, by high frequency clock timing, thereby may be ensured that the timing accuracy under whole sleep pattern；In the case of accurate timing, sleep pattern is entered from certain sub-frame boundary receiving data, and sleep cycle is the integral multiple of subframe, after then can ensure that end sleep cycle, receiving data is still sub-frame boundary, avoid the re-synchronization after UE wakes up up, extend system sleep cycle, beneficially system power dissipation optimization.
Further, the method using the embodiment of the present invention, can the most self-defined DRX sleep bout length, the actual length of one's sleep can be set in a register according to time of sleep cycle, apply for reality and provide bigger motility.
With reference to Fig. 2, it is shown that the flow chart of a kind of terminal sleep cycle control methods embodiment 2 of the present invention, specifically may comprise steps of:
Step 201, configuring difference T1 of the duration of the first timing point and the second timing point according to the sleep cycle T0 of terminal, wherein, the difference of T0 Yu T1 is less than the first pre-set threshold value.
Step 202, according to sleep cycle T0 and difference T1 of the duration of the duration of the second timing point and the first timing point, determine the first edge of low-frequency clock, after the first edge is time zero, the n-th edge of low-frequency clock, N is positive integer.
In embodiment 1 preferably, first timing point is concordant with the first edge of low-frequency clock, after first edge is time zero, first edge of low-frequency clock, first edge of high frequency clock timing tremendously low frequency clock, then begin through low-frequency clock and carry out timing, when being no less than a cycle due to the difference of the timing time T1 of sleep cycle T0 and low-frequency clock, high frequency clock timing can have multiple choices to the edge of low-frequency clock accordingly, therefore, the present embodiment gives the determination method of the first timing point, i.e. low-frequency clock starts the determination method at edge of timing, the edge of n-th edge low-frequency clock can be rising edge or the trailing edge of low-frequency clock, step 202 may include that
Sub-step S21, calculating sleep cycle T0 deduct the difference of difference T1 of the duration of the second timing point and the duration of the first timing point；
Sub-step S22, selected distance time zero are less than first edge as low-frequency clock, the edge of T0 Yu T1 difference.
The difference of the duration of the second timing point and the duration of the first timing point is the timing time T1 of low-frequency clock, the difference of sleep cycle T0 and the timing time T1 of low-frequency clock is the timing time summation of high frequency clock in sleep cycle, when the timing time of high frequency clock is more than a cycle, can can there is various ways with the selection at edge, only need to meet the edge distance current time chosen less than above-mentioned difference.
As shown in Figure 5, the length that difference is A1 and the A2 time of sleep cycle T0 and the timing time T1 of low-frequency clock, it is about 2.8 cycles, A1 is 1.3 cycles, A2 is 1.5 cycles, as a example by rising edge, first rising edge distance current time is 0.3 cycle, second rising edge that is to say that c point distance current time is 1.3 cycles, 3rd rising edge that is to say that c point distance current time is 2.3 cycles, 4th rising edge that is to say that c point distance current time is 3.3 cycles, therefore, first less than 2.8 cycles of difference can be selected, second or the 3rd rising edge are as the time beginning through low-frequency clock timing, Fig. 5 have selected second rising edge c point as the time beginning through low-frequency clock timing.
Step 203, receive enter sleep pattern instruction after, carry out timing by high frequency clock；
Step 204, when determine arrive the first timing point by high frequency clock timing time, carry out timing by low-frequency clock, and triggering terminal enter sleep pattern, wherein, the first timing point is concordant with the first edge of low-frequency clock.
In the embodiment of the present invention, the edge of low-frequency clock can carry out sampling by high frequency clock to low-frequency clock and determine.
Step 205, when determine reach the second timing point by low-frequency clock timing time, carry out timing by high frequency clock, wherein, the second timing point is concordant with the second edge of low-frequency clock.
Step 206, when determine by high frequency clock timing arrive three timing points time, triggering terminal enter mode of operation, start with base station carry out data interaction, wherein, time a length of sleep cycle T0 of the 3rd timing point.
According to the embodiment of the present invention, after receiving the instruction entering sleep pattern, by high frequency clock timing to the first timing point, then begin through low-frequency clock and carry out timing, and enter sleep pattern, when low-frequency clock timing arrives the second timing point, timing is carried out by high frequency clock, until arriving the 3rd timing point, triggering terminal enters sleep pattern, starts to recover the data interaction with base station.Owing to the timing of low-frequency clock starts to terminate to be the edge of low-frequency clock with timing, therefore, low-frequency clock timing in sleep pattern is accurately, not arriving the part at low-frequency clock edge and reach the time after T1 by high frequency clock timing, thereby may be ensured that the timing accuracy under whole sleep pattern；In the case of accurate timing, enter sleep pattern from certain sub-frame boundary receiving data, and sleep cycle is the integral multiple of subframe, then, after can ensure that end sleep cycle, receiving data is still sub-frame boundary.
In sum, use the method for the embodiment of the present invention without carrying out re-synchronization between end sleep pattern, and the difference of sleep cycle T0 and the timing duration T1 of low-frequency clock is less than the first pre-set threshold value, time compared to the re-synchronization of Millisecond, the embodiment of the present invention can extend the sleep cycle of terminal, reduces the power consumption of terminal.
Further, the method using the embodiment of the present invention, can the most self-defined DRX sleep bout length, the actual length of one's sleep can be set in a register according to time of sleep cycle, apply for reality and provide bigger motility.
For embodiment of the method, in order to be briefly described, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not limited by described sequence of movement, because according to the present invention, some step can use other orders or carry out simultaneously.Secondly, those skilled in the art also should know, embodiment described in this description belongs to preferred embodiment, necessary to involved action and the module not necessarily present invention.
With reference to Fig. 3, it is shown that the structured flowchart of a kind of terminal sleep period control device embodiment 1 of the present invention, specifically can include with lower module:
First high frequency timing module 301, after receiving the instruction entering sleep pattern, carries out timing by high frequency clock, when determining by high frequency clock timing to the first timing point, stopping carrying out timing by high frequency clock, wherein, the first timing point is concordant with the first edge of low-frequency clock；
Low frequency timing module 302 is connected with the first high frequency timing module 301, low frequency timing module 302 is when the first high frequency timing module 301 timing arrives the first timing point, timing is carried out by low-frequency clock, and triggering terminal enters sleep pattern, when determining by low-frequency clock timing to the second timing point, stop carrying out timing by low-frequency clock, wherein, first timing point is concordant with the first edge of low-frequency clock, difference T1 of the duration of the second timing point and the duration of the first timing point configures according to sleep cycle T0, and the difference of T0 Yu T1 is less than the first pre-set threshold value；
Second high frequency timing module 303 is connected with low frequency timing module 302, second high frequency timing module 303 is for when low frequency timing module 302 timing arrives the second timing point, by high frequency clock timing, when determining by high frequency clock timing arrival three timing point, stop carry out timing by high frequency clock, the 3rd timing point time a length of terminal sleep cycle T0；
Work trigger module 304 is connected with the second high frequency timing module 303, and work trigger module 304 enters mode of operation for triggering terminal, starts to carry out data interaction with base station.
In the embodiment of the present invention, the first high frequency timing module, specifically for when timing to time zero after, when first edge of low-frequency clock is concordant, determine when arriving the first timing point by high frequency clock timing.
In the embodiment of the present invention, the first high frequency timing module can be with timing to first timing point concordant with low-frequency clock rising edge or trailing edge, and low frequency timing module can be with timing to second timing point concordant with low-frequency clock rising edge or trailing edge.
In the embodiment of the present invention, first high frequency timing module by high frequency clock low-frequency clock can be sampled determine timing to the first timing point with the first edge flush of low-frequency clock, low frequency timing module by high frequency clock low-frequency clock can be sampled determine timing extremely with the second timing point of the second edge flush of low-frequency clock.
With reference to Fig. 4, it is shown that the structured flowchart of a kind of terminal sleep period control device embodiment 2 of the present invention, specifically can include with lower module:
Time distribution module 401, for configuring difference T1 of the duration of the first timing point and the second timing point according to the sleep cycle T0 of terminal, wherein, the difference of T0 Yu T1 is less than the first pre-set threshold value；
Edge determines that module 402 is connected with time distribution module 401, edge determines that module 402 is for the sleep cycle T0 according to time distribution module 401 distribution and difference T1 of the duration of the duration of the second timing point and the first timing point, determine the first edge of low-frequency clock, after first edge is time zero, the n-th edge of low-frequency clock, N is positive integer；
First high frequency timing module 403 determines that with edge module 402 is connected, first high frequency timing module 403 is after receiving the instruction entering sleep pattern, timing is carried out by high frequency clock, when determining by high frequency clock timing to the first timing point, stop carrying out timing by high frequency clock, wherein, the first timing point determines that with edge the first edge of low-frequency clock that module 402 determines is concordant；
Low frequency timing module 404 is connected with time distribution module 401 and the first high frequency timing module 403, low frequency timing module 404 is when the first high frequency timing module 403 timing arrives the first timing point, timing is carried out by low-frequency clock, and triggering terminal enters sleep pattern, when determining by low-frequency clock timing to the second timing point, stop carrying out timing by low-frequency clock, wherein, second timing point is concordant with the second edge of low-frequency clock, and difference T1 of the duration of the second timing point and the duration of the first timing point is determined by time distribution module 401；
Second high frequency timing module 405 is connected with low frequency timing module 404, high frequency timing module 405 is for when low frequency timing module 404 timing arrives the second timing point, timing is carried out by high frequency clock, when determining by high frequency clock timing arrival three timing point, stop carry out timing by high frequency clock, the 3rd timing point time a length of terminal sleep cycle T0；
Work trigger module 406 is connected with the second high frequency timing module 405, and work trigger module 406 is when the second high frequency timing module 405 timing arrives three timing points, and triggering terminal enters mode of operation, starts to carry out data interaction with base station.
In the embodiment of the present invention, the first high frequency timing module, specifically for when timing to time zero after, when the n-th edge of low-frequency clock is concordant, determine that when arriving the first timing point by high frequency clock timing, wherein, N is positive integer.
In the embodiment of the present invention, time distribution module 401 may include that
First number determines submodule, is used for sleep cycle T0 divided by the time-count cycle of low-frequency clock, obtains first number of low-frequency clock time-count cycle；
Second number determines that submodule and the first number determine that submodule is connected, second number determines that submodule determines second number of the time-count cycle of low-frequency clock for first number of low-frequency clock time-count cycle determining that submodule determines according to the first number with the difference of the second pre-set threshold value, using the product of the second number and low-frequency clock as the first timing point and difference T1 of the duration of the second timing point.
In the embodiment of the present invention, edge determines that module may include that
Mathematic interpolation submodule and the second number determine that submodule is connected, and mathematic interpolation submodule is for calculating the difference that sleep cycle T0 deducts difference T1 of the duration of the second timing point and the duration of the first timing point；
Edge is chosen submodule and is connected with mathematic interpolation submodule, and edge is chosen submodule and is less than first edge as low-frequency clock, the edge of T0 Yu the T1 difference that mathematic interpolation submodule determines for selected distance time zero.
In the embodiment of the present invention, the first high frequency timing module timing to first timing point concordant with low-frequency clock rising edge or trailing edge, low frequency timing module timing is to second timing point concordant with low-frequency clock rising edge or trailing edge.
In the embodiment of the present invention, first high frequency timing module by high frequency clock low-frequency clock sampled determine timing to the first timing point with the first edge flush of low-frequency clock, low frequency timing module by high frequency clock low-frequency clock sampled determine timing extremely with the second timing point of the second edge flush of low-frequency clock.
Owing to described device embodiment essentially corresponds to the embodiment of the method shown in earlier figures 1 and Fig. 2, therefore the most detailed part in the description of the present embodiment, may refer to the related description in previous embodiment, do not repeat at this.
The present invention can be used in numerous general or special purpose computing system environment or configuration.Such as: personal computer, server computer, handheld device or portable set, laptop device, multicomputer system, system based on microprocessor, set top box, programmable consumer-elcetronics devices, network PC, minicomputer, mainframe computer, the distributed computing environment including any of the above system or equipment etc..
The present invention can be described in the general context of computer executable instructions, such as program module.Usually, program module includes performing particular task or realizing the routine of particular abstract data type, program, object, assembly, data structure etc..The present invention can also be put into practice in a distributed computing environment, in these distributed computing environment, the remote processing devices connected by communication network perform task.In a distributed computing environment, during program module may be located at the local and remote computer-readable storage medium including storage device.
In this article, term " includes ", " comprising " or its any other variant are intended to comprising of nonexcludability, so that include that the process of a series of key element, method, article or equipment not only include those key elements, but also include other key elements being not expressly set out, or also include the key element intrinsic for this process, method, article or equipment.In the case of there is no more restriction, statement " including ... " key element limited, it is not excluded that there is also other identical element in including the process of described key element, method, article or equipment.
Above to a kind of terminal sleep cycle control methods provided by the present invention, and, a kind of terminal sleep period control device is described in detail, principle and the embodiment of the present invention are set forth by specific case used herein, and the explanation of above example is only intended to help to understand method and the core concept thereof of the present invention；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, the most all will change, in sum, this specification content should not be construed as limitation of the present invention.
Claims (8)
1. a terminal sleep cycle control methods, it is characterised in that including:
After receiving the instruction of entrance sleep pattern, carry out timing by high frequency clock；
When determine arrive the first timing point by described high frequency clock timing time, entered by low-frequency clock
Row timing, and triggering terminal entrance sleep pattern, wherein, described first timing point and described low frequency
First edge of clock is concordant；
When determine arrive the second timing point by described low-frequency clock timing time, during by described high frequency
Clock carries out timing, and wherein, described second timing point is concordant with the second edge of described low-frequency clock,
Difference T1 of the duration of the duration of described second timing point and described first timing point is according to described terminal
Sleep cycle T0 configures, and the difference of T0 Yu T1 is less than the first pre-set threshold value；Farther include: will
Sleep cycle T0 divided by the time-count cycle of low-frequency clock, obtains first of low-frequency clock time-count cycle
Number；Low frequency is determined with the difference of the second pre-set threshold value according to first number of low-frequency clock time-count cycle
Second number of the time-count cycle of clock, by the time-count cycle of described second number and low-frequency clock
Product is as the first timing point and difference T1 of the duration of the second timing point；
When determining by described high frequency clock timing arrival three timing point, triggering terminal enters work
Operation mode, starts to carry out data interaction, wherein, time a length of institute of described 3rd timing point with base station
State sleep cycle T0；Wherein, corresponding timing point time a length of from receive enter sleep pattern finger
Make and begin to use the timing point of high frequency clock timing to start, the time between corresponding timing point.
Method the most according to claim 1, it is characterised in that described first edge is timing
After starting point, first edge of described low-frequency clock.
Method the most according to claim 1, it is characterised in that described first edge is timing
After starting point, the n-th edge of described low-frequency clock, N is positive integer；
Described method also includes, is determined the first edge of described low-frequency clock by following steps:
Calculate described sleep cycle T0 deduct the duration of the second timing point and described first timing point time
The difference of long difference T1；
When time zero described in selected distance is less than the edge of T0 Yu T1 difference as described low frequency
First edge of clock.
Method the most according to claim 1, it is characterised in that the first of described low-frequency clock
Edge or the second edge carry out sampling by described high frequency clock to described low-frequency clock and determine.
5. a terminal sleep period control device, it is characterised in that including:
First high frequency timing module, after receiving the instruction entering sleep pattern, passes through high frequency
Clock carries out timing, when determining by described high frequency clock timing to the first timing point, stops logical
Cross described high frequency clock and carry out timing, wherein, described first timing point and the first limit of low-frequency clock
Along concordant；
Low frequency timing module, for carrying out timing by described low-frequency clock, and triggering terminal enters
Sleep pattern, when determining by described low-frequency clock timing to the second timing point, stops by institute
State low-frequency clock and carry out timing, wherein, described second timing point and the second limit of described low-frequency clock
Along concordant, the duration of described second timing point is basis with difference T1 of the duration of described first timing point
Described sleep cycle T0 configuration, the difference of T0 Yu T1 is less than the first pre-set threshold value；
Second high frequency timing module, for by using described high frequency clock to carry out timing, when determining
When arriving three timing points by described high frequency clock timing, stop being carried out by described high frequency clock
Timing, described 3rd timing point time a length of described terminal sleep cycle T0；
Work trigger module, is used for triggering described terminal and enters mode of operation, start to carry out with base station
Data interaction；
Wherein, corresponding timing point time a length of enter the instruction of sleep pattern and start to make from receiving
Start with the timing point of high frequency clock timing, the time between corresponding timing point；
Wherein, also include:
Time distribution module, for according to the sleep cycle T0 of described terminal configure the first timing point and
Difference T1 of the duration of the second timing point；
Distribution of described time module includes:
First number determines submodule, for by sleep cycle T0 divided by the time-count cycle of low-frequency clock,
Obtain first number of low-frequency clock time-count cycle；
Second number determines submodule, for the first number and the according to low-frequency clock time-count cycle
The difference of two pre-set threshold value determines second number of the time-count cycle of low-frequency clock, by described second
The product of number and the time-count cycles of low-frequency clock as the first timing point and the second timing point duration it
Difference T1.
Device the most according to claim 5, it is characterised in that described first high frequency timing mould
Block, specifically for when timing to time zero after, first edge of described low-frequency clock put down
Qi Shi, determines when arriving the first timing point by described high frequency clock timing.
Device the most according to claim 5, it is characterised in that described first high frequency timing mould
Block, specifically for when timing to time zero after, the n-th edge of described low-frequency clock put down
Qi Shi, determines that when arriving the first timing point by described high frequency clock timing, wherein, N is the most whole
Number；
Described device also includes, edge determines module, be used for determining according to described sleep cycle T0 with
And second difference T1 of duration of duration and described first timing point of timing point, when determining described low frequency
First edge of clock, after described first edge is time zero, the n-th of described low-frequency clock
Edge；
Described edge determines that module includes:
Mathematic interpolation submodule, deducts the duration of the second timing point for calculating described sleep cycle T0
Difference with difference T1 of the duration of described first timing point；
Submodule is chosen at edge, for time zero described in selected distance less than T0 Yu T1 difference
Edge as the first edge of described low-frequency clock.
Device the most according to claim 5, it is characterised in that described first high frequency timing mould
Block carries out sampling by described high frequency clock to described low-frequency clock and determines that timing is to during with described low frequency
First timing point of the first edge flush of clock, when described low frequency timing module is by described high frequency
Described low-frequency clock is sampled and is determined that timing is to equal with the second edge of described low-frequency clock by clock
The second neat timing point.
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| CN105703749B (en) * | 2014-11-24 | 2018-07-20 | 中国科学院沈阳自动化研究所 | A kind of accurate doze output circuit of low-power consumption and method |
| CN106411444A (en) * | 2015-07-30 | 2017-02-15 | 联芯科技有限公司 | Timing compensation method and mobile terminal |
| KR102618563B1 (en) * | 2016-07-01 | 2023-12-27 | 삼성전자주식회사 | Integrated circuit device and electronic device including the same |
| CN106376065B (en) * | 2016-08-30 | 2019-08-20 | 重庆邮电大学 | A kind of mechanism based on POMDP dynamic adjustment base station shutdown length of window |
| EP3689039A1 (en) | 2017-12-19 | 2020-08-05 | Huawei Technologies Co. Ltd. | A user node, a network node and methods for wireless communication |
| CN114860323A (en) * | 2022-05-20 | 2022-08-05 | 重庆御芯微信息技术有限公司 | Low-power-consumption accurate timing awakening method and device |
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| CA2340446A1 (en) * | 1998-08-14 | 2000-02-24 | Qualcomm Incorporated | Synchronisation of a low power clock in a wireless communication device |
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| CN102821446A (en) * | 2012-06-04 | 2012-12-12 | 江苏大学 | Synchronous awaking mechanism of long-term and deep dormant wireless sensor network |
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| US7463910B2 (en) * | 2005-03-10 | 2008-12-09 | Qualcomm Incorporated | Apparatus and method for determining sleep clock timing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CA2340446A1 (en) * | 1998-08-14 | 2000-02-24 | Qualcomm Incorporated | Synchronisation of a low power clock in a wireless communication device |
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| CN102821446A (en) * | 2012-06-04 | 2012-12-12 | 江苏大学 | Synchronous awaking mechanism of long-term and deep dormant wireless sensor network |
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