CN103295642B - Shift register and panel display apparatus - Google Patents
Shift register and panel display apparatus Download PDFInfo
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- CN103295642B CN103295642B CN201210352901.8A CN201210352901A CN103295642B CN 103295642 B CN103295642 B CN 103295642B CN 201210352901 A CN201210352901 A CN 201210352901A CN 103295642 B CN103295642 B CN 103295642B
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Abstract
Technical solution of the present invention provides a kind of shift register and panel display apparatus, the control end of the first transistor of shift register receives the first clock signal, first end receives output signal or the start signal of upper level shift register, and the second end connects the first end of electric capacity and the control end of transistor seconds; The first end of transistor seconds receives second clock signal, second end connects the control end of the second end of electric capacity, the first end of third transistor, the first end of the 4th transistor and the 5th transistor, and the second end of transistor seconds exports the output signal of shift register at the corresponding levels; The control end of third transistor receives the first clock signal, and the second end connects the second end of the 4th transistor and the second end of the 5th transistor, and the second termination of third transistor receives low level signal; The control end of the 4th transistor connects the first end of the 5th transistor and the negative pole end of unit; The positive terminal of transistor unit receives second clock signal.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly a kind of shift register and panel display apparatus.
Background technology
In liquid crystal display (LCD), or in structure other flat-panel monitors such as e-book, Organic Light Emitting Diode flexible display similarly, grid driving circuit and data drive circuit are all the later stage attach on display panel when assembling, and the cost of driving circuit is high, assembling attachment process also will spend a large amount of operations, manpower and time.
In order to reduce costs, amorphous silicon gate could drives (AmorphousSiliconGate, ASG) technology to be suggested.ASG technology is non-display area gate driver circuit being integrated in display panel synchronous in flat-panel monitor manufacture process, the frame region of such as display panels.Owing to adopting ASG technology can save original gate driver circuit, improve integrated level, reduce outer member, reduce manufacturing cost, therefore ASG technology is applied more and more.
By every a line pixel cell, the circuit structure producing separately gate drive signal is called ASG unit.ASG unit has the structure of a shift register usually, and overall ASG driving circuit is the repetition of ASG unit at all row, or the interlacing of parity rows ASG unit repeats.Gate drive signal is connected with the on-off element (such as thin film transistor (TFT) TFT) of the pixel cell in pel array, controls conducting and the disconnection of described on-off element.
As shown in Figure 1, ASG driving circuit is made up of a series of ASG unit (shift register) 121.ASG unit 121 comprises input node IN, output node OUT, voltage source node V1 and clock signal node C1 and C2.Input node IN inputs start signal or upper level output signal STV, output node OUT export output signal GoutN, voltage source node V1 input low level signal VGL at the corresponding levels, the clock signal clk of clock signal node C1 and the complementation of C2 input phase and CLKB.
As shown in Figures 2 and 3, low level signal VGL is always low level, and the course of work of ASG unit is roughly as follows:
When upper level output signal STV is high level, clock signal clk B is low level, clock signal clk is high level: the clock signal clk of high level makes MOS transistor T1 and MOS transistor T3 conducting; After MOS transistor T1 conducting, P point voltage becomes and outputs signal the identical high level of STV with upper level; The high level of P point makes MOS transistor T2 conducting; Low level low level signal VGL and clock signal clk B makes output signal GoutN be low level by the MOS transistor T2 of conducting and MOS transistor T3.
Upper level output signal is when STV becomes low level from high level, clock signal clk B becomes high level, clock signal clk becomes low level: low level clock signal clk makes MOS transistor T1 and MOS transistor T3 cut-off; The high level of P point maintains MOS transistor T2 conducting, and the clock signal clk B of high level makes output signal GoutN become high level from low level, and increases the magnitude of voltage of P point high level by electric capacity Ct.
MOS transistor T3 is generally the lower trombone slide of ASG unit, as can be seen from the above-mentioned course of work, clock signal clk be low level at present trombone slide be cut-off state.Clock signal clk is the low level time probably account for 50% of the whole cycle, that is, lower trombone slide the whole cycle 50% time be all cut-off state, the lower trombone slide of cut-off causes output node OUT to be in floating state.
The output node OUT of floating state is serious by outer signals crosstalk, and output signal is unstable, and after certain progression, output waveform distortion is serious.
Summary of the invention
The output node of what technical solution of the present invention solved is existing shift register is serious by outer signals crosstalk, and output signal is unstable.
Technical solution of the present invention provides a kind of shift register, comprising: the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, transistor unit and electric capacity;
The control end of described the first transistor receives the first clock signal, and first end receives output signal or the start signal of upper level shift register, and the second end connects the first end of described electric capacity and the control end of transistor seconds;
The first end of described transistor seconds receives second clock signal, second end connects the control end of the second end of described electric capacity, the first end of third transistor, the first end of the 4th transistor and the 5th transistor, and the second end of described transistor seconds exports the output signal of shift register at the corresponding levels;
The control end of described third transistor receives described first clock signal, and the second end connects the second end of described 4th transistor and the second end of described 5th transistor, and the second termination of described third transistor receives low level signal;
The control end of described 4th transistor connects the described first end of the 5th transistor and the negative pole end of described unit;
The positive terminal of described transistor unit receives described second clock signal;
The conducting resistance of described transistor unit is greater than the conducting resistance of described 5th transistor.
Optionally, described first clock signal is the complementary signal of described second clock signal, and described low level signal is less than or equal to the low level magnitude of voltage of described first clock signal.
Optionally, described shift register also comprises: the 7th transistor, and the control end of described 7th transistor receives the output signal of next stage shift register, and first end connects the first end of described electric capacity, and the second termination receives described low level signal.
Optionally, described shift register also comprises: the 8th transistor, and the control end of described 8th transistor receives described first clock signal, and first end connects the control end of described 4th transistor, and the second termination receives described low level signal.
Optionally, described transistor unit comprises the 6th transistor, the control end of described 6th transistor connects the positive terminal of first end as described transistor unit of described 6th transistor, second end of described 6th transistor is as the negative pole end of described transistor unit, and the conducting resistance of described 6th transistor is greater than the conducting resistance of described 5th transistor.
Optionally, described transistor unit comprises diode, described diode cathode is as the positive terminal of described transistor unit, and described diode cathode is as the negative pole end of described transistor unit, and the conducting resistance of described diode is greater than the conducting resistance of described 5th transistor.
Optionally, described transistor is MOS transistor, and the control end of described transistor is the grid of described MOS transistor;
The drain electrode that the source electrode that the first end of described transistor is described MOS transistor, the second end are described MOS transistor, or the first end of described transistor be the drain electrode of described MOS transistor, the second end is the source electrode of described MOS transistor.
Optionally, the breadth length ratio of described 5th transistor is greater than the breadth length ratio of described 6th transistor.
Optionally, the breadth length ratio of described 5th transistor is greater than five times of the breadth length ratio of described 6th transistor.
Technical solution of the present invention also provides a kind of panel display apparatus, comprising: pixel cell and above-mentioned shift register, and described shift register is suitable for producing the signal needed for described pixel cell.
Compared with prior art, technical solution of the present invention can continue the low level maintaining output signal after the output signal of shift register produces a pulse, prevent shift register output node from occurring floating state, avoid output signal by outer signals crosstalk, stable output signal.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing shift register;
Fig. 2 is a kind of structural representation of existing shift register cell;
The input/output signal waveform schematic diagram that Fig. 3 is shift register cell shown in Fig. 2;
Fig. 4 is enforcement one structural representation of shift register of the present invention;
The input/output signal waveform schematic diagram that Fig. 5 is shift register shown in Fig. 4;
Fig. 6 is enforcement two structural representation of shift register of the present invention;
Fig. 7 is enforcement three structural representation of shift register of the present invention;
The input/output signal waveform schematic diagram that Fig. 8 is shift register cell shown in Fig. 7.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to following explanation, advantages and features of the invention will be clearer.
As shown in Figure 4, the embodiment of the present invention one provides a kind of shift register, comprising: the first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, transistor unit 11 and electric capacity C1.
The control end of described the first transistor M1 receives the first clock signal clk, and first end receives output signal or the start signal STV of upper level shift register, and the second end connects the first end of described electric capacity C1 and the control end of transistor seconds M2;
The first end of described transistor seconds M2 receives second clock signal CLKB, second end connects the control end of second end of described electric capacity C1, the first end of third transistor M3, the first end of the 4th transistor M4 and the 5th transistor M5, and second end of described transistor seconds M2 exports the output signal GoutN of shift register at the corresponding levels;
The control end of described third transistor M3 receives described first clock signal clk, and the second end connects second end of described 4th transistor M4 and second end of described 5th transistor M5, and second termination of described third transistor M3 receives low level signal VGL;
The control end of described 4th transistor M4 connects the described first end of the 5th transistor M5 and the negative pole end of described transistor unit 11;
The positive terminal of described transistor unit 11 receives described second clock signal CLKB;
The conducting resistance of described transistor unit 11 is greater than the conducting resistance of described 5th transistor M5.
Described electric capacity C1 can stored charge play the on-off action of transistor seconds M2.
Described transistor unit 11 can comprise the 6th transistor M6, the control end of described 6th transistor M6 connects the positive terminal of first end as described transistor unit 11 of described 6th transistor M6, second end of described 6th transistor M6 is as the negative pole end of described transistor unit 11, and the conducting resistance of described 6th transistor M6 is greater than the conducting resistance of described 5th transistor M5.
The conducting resistance of described 6th transistor M6 can be greater than the conducting resistance of described 5th transistor M5.Concrete, described 5th transistor M5 and the 6th transistor M6 is MOS transistor, and the breadth length ratio of described 5th transistor M5 is greater than the breadth length ratio of described 6th transistor M6.Optionally, the breadth length ratio of described 5th transistor M5 is greater than five times of the breadth length ratio of described 6th transistor M6.
Described transistor unit 11 also can comprise diode, described diode cathode is as the positive terminal of described transistor unit, described diode cathode is as the negative pole end of described transistor unit, and the conducting resistance of described diode is greater than the conducting resistance of described 5th transistor.
Composition graphs 4 and Fig. 5, first clock signal clk of the present embodiment one is the complementary signal of described second clock signal CLKB, and low level signal VGL is less than or equal to the low level magnitude of voltage of described first clock signal clk.The shift register course of work is roughly as follows:
When the output signal of upper level shift register or start signal STV are high level, the first clock signal clk is high level, second clock signal CLKB is low level:
First clock signal clk of high level makes the first transistor M1 and third transistor M3 conducting, and low level clock signal clk B makes the 6th transistor M6 end; After the first transistor M1 conducting, P point voltage becomes the high level identical with the output signal of upper level shift register or start signal STV; The high level of P point makes transistor seconds M2 conducting; Low level low level signal VGL and second clock signal CLKB makes output signal GoutN become low level by the third transistor M3 of conducting and transistor seconds M2; Low level output signal GoutN makes the 5th transistor M5 end; The cut-off of the 5th transistor M5 and the 6th transistor M6 causes Q point to present floating state, and the Q point voltage value of floating state is between high level and low level, and cannot make the 4th transistor M4 conducting, the 4th transistor M4 ends.
The output signal of upper level shift register or start signal STV becomes low level from high level, the first clock signal clk is low level, second clock signal CLKB is high level time:
Low level first clock signal clk makes the first transistor M1 and third transistor M3 cut-off, and the clock signal clk B of high level makes the 6th transistor M6 conducting; The high level of P point maintains transistor seconds M2 conducting; The second clock signal CLKB of high level makes output signal GoutN become high level from low level, and increases the magnitude of voltage of P point high level by electric capacity C1; The output signal GoutN of high level makes the 5th transistor M5 conducting, and the conducting resistance due to the 6th transistor M6 is greater than the conducting resistance of the 5th transistor M5, so Q point voltage keeps floating state, the 4th transistor M4 ends.
When the output signal of upper level shift register or start signal STV keep low level, the first clock signal clk is high level, second clock signal CLKB is low level:
First clock signal clk of high level makes the first transistor M1 and third transistor M3 conducting, and low level clock signal clk B makes the 6th transistor M6 end; After the first transistor M1 conducting, P point voltage becomes the low level identical with the output signal of upper level shift register or start signal STV; The low level of P point makes transistor seconds M2 end; Low level low level signal VGL makes output signal GoutN be low level by the third transistor M3 of conducting; Low level output signal GoutN makes the 5th transistor M5 end; It is floating state that the cut-off of the 5th transistor M5 and the 6th transistor M6 causes Q point voltage still, and the 4th transistor M4 ends;
When the output signal of upper level shift register or start signal STV keep low level, the first clock signal clk is low level, second clock signal CLKB is high level:
Low level first clock signal clk makes the first transistor M1 and third transistor M3 cut-off, and the clock signal clk B of high level makes the 6th transistor M6 conducting; The low level of P point maintains transistor seconds M2 cut-off, and output signal GoutN is still low level; Low level output signal GoutN makes the 5th transistor M5 remain off; 6th transistor M6 of conducting makes Q point voltage become the high level identical with second clock signal CLKB; The Q point voltage of high level makes the 4th transistor M4 conducting; It is low level that low level signal VGL maintains output signal GoutN by the 4th transistor M4 of conducting.
After this, the 6th transistor M6 along with second clock signal CLKB periodically conducting and cut-off, the cyclical variation between high level and floating state of Q point.
As can be seen from the above-mentioned course of work, keep low level after output signal GoutN produces a pulse always, when first clock signal clk is high level, low level signal VGL maintains the low level of output signal GoutN by the third transistor M3 of conducting, when second clock signal CLKB is high level, low level signal VGL maintains the low level of output signal GoutN by the 4th transistor M4 of conducting.Therefore, the technical scheme of application the present embodiment one can prevent shift register output node from occurring floating state, avoids output signal by outer signals crosstalk, stable output signal.
As shown in Figure 6, the embodiment of the present invention two is also to comprise the 7th transistor M7 with the difference of embodiment one, the control end of described 7th transistor M7 receives the output signal GoutN+1 of next stage shift register, first end connects the first end of described electric capacity C1, and the second termination receives described low level signal VGL.
Continue with reference to figure 5,7th transistor M7 conducting when the output signal GoutN+1 of next stage shift register is high level, low level signal VGL makes the low level of P point more stable, the burr impact on the output signal of less upper level shift register or start signal STV.
As shown in Figure 7, the embodiment of the present invention three is also to comprise the 8th transistor M8 with the difference of embodiment one, the control end of described 8th transistor M8 receives described first clock signal clk, and first end connects the control end of described 4th transistor M4, and the second termination receives described low level signal VGL.
As shown in Figure 8, the 6th transistor M6 conducting when second clock signal CLKB is high level, the second clock signal CLKB of high level makes Q point voltage become high level by the 6th transistor M6 of conducting; 8th transistor M8 conducting when first clock signal clk is high level, low level signal VGL makes Q point voltage become low level by the 8th transistor M8 of conducting.Q point can be avoided like this to occur floating state, ensure that periodicity conducting and the cut-off of the 4th transistor M4, stabilize output signal GoutN further.
The transistor of above-described embodiment can be MOS transistor, and the control end of described transistor is the grid of described MOS transistor; The drain electrode that the source electrode that the first end of described transistor is described MOS transistor, the second end are described MOS transistor, or the first end of described transistor be the drain electrode of described MOS transistor, the second end is the source electrode of described MOS transistor.
The embodiment of the present invention also provides a kind of panel display apparatus, comprising: pixel cell and the shift register described in above-described embodiment, and the shift register described in above-described embodiment is suitable for producing the signal needed for described pixel cell.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should with claim institute limited range.
Claims (10)
1. a shift register, is characterized in that, comprising: the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, transistor unit and electric capacity;
The control end of described the first transistor receives the first clock signal, and first end receives output signal or the start signal of upper level shift register, and the second end connects the first end of described electric capacity and the control end of transistor seconds;
The first end of described transistor seconds receives second clock signal, second end connects the control end of the second end of described electric capacity, the first end of third transistor, the first end of the 4th transistor and the 5th transistor, and the second end of described transistor seconds exports the output signal of shift register at the corresponding levels;
The control end of described third transistor receives described first clock signal, and the second end connects the second end of described 4th transistor and the second end of described 5th transistor, and the second termination of described third transistor receives low level signal;
The control end of described 4th transistor connects the described first end of the 5th transistor and the negative pole end of described transistor unit;
The positive terminal of described transistor unit receives described second clock signal;
The conducting resistance of described transistor unit is greater than the conducting resistance of described 5th transistor.
2. shift register as claimed in claim 1, it is characterized in that, described first clock signal is the complementary signal of described second clock signal, and described low level signal is less than or equal to the low level magnitude of voltage of described first clock signal.
3. shift register as claimed in claim 1, it is characterized in that, also comprise: the 7th transistor, the control end of described 7th transistor receives the output signal of next stage shift register, first end connects the first end of described electric capacity, and the second termination receives described low level signal.
4. shift register as claimed in claim 1, it is characterized in that, also comprise: the 8th transistor, the control end of described 8th transistor receives described first clock signal, first end connects the control end of described 4th transistor, and the second termination receives described low level signal.
5. shift register as claimed in claim 1, it is characterized in that, described transistor unit comprises the 6th transistor, the control end of described 6th transistor connects the positive terminal of first end as described transistor unit of described 6th transistor, second end of described 6th transistor is as the negative pole end of described transistor unit, and the conducting resistance of described 6th transistor is greater than the conducting resistance of described 5th transistor.
6. shift register as claimed in claim 1, it is characterized in that, described transistor unit comprises diode, described diode cathode is as the positive terminal of described transistor unit, described diode cathode is as the negative pole end of described transistor unit, and the conducting resistance of described diode is greater than the conducting resistance of described 5th transistor.
7. the shift register as described in claim as arbitrary in claim 1-6, is characterized in that, described transistor is MOS transistor, and the control end of described transistor is the grid of described MOS transistor;
The drain electrode that the source electrode that the first end of described transistor is described MOS transistor, the second end are described MOS transistor, or the first end of described transistor be the drain electrode of described MOS transistor, the second end is the source electrode of described MOS transistor.
8. shift register as claimed in claim 7, it is characterized in that, the breadth length ratio of described 5th transistor is greater than the breadth length ratio of described 6th transistor.
9. shift register as claimed in claim 8, it is characterized in that, the breadth length ratio of described 5th transistor is greater than five times of the breadth length ratio of described 6th transistor.
10. a panel display apparatus, is characterized in that, comprising: pixel cell and the shift register described in any one of claim 1-9, and the shift register described in any one of claim 1-9 is suitable for producing the signal needed for described pixel cell.
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| CN201210352901.8A CN103295642B (en) | 2012-09-19 | 2012-09-19 | Shift register and panel display apparatus |
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| CN104751769A (en) * | 2013-12-25 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driver and organic light emitting display employing same |
| CN104900179B (en) * | 2015-06-29 | 2017-08-18 | 重庆市中光电显示技术有限公司 | A kind of array scanning control circuit of flat-panel monitor |
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