CN103280196A - Shifting register and thin film transistor liquid crystal display - Google Patents
Shifting register and thin film transistor liquid crystal display Download PDFInfo
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- CN103280196A CN103280196A CN2012103503501A CN201210350350A CN103280196A CN 103280196 A CN103280196 A CN 103280196A CN 2012103503501 A CN2012103503501 A CN 2012103503501A CN 201210350350 A CN201210350350 A CN 201210350350A CN 103280196 A CN103280196 A CN 103280196A
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Abstract
The invention provides a shifting register and a thin film transistor liquid crystal display. The shifting register comprises multiple cascaded shifting registering circuits, and each circuit is composed of nine transistors and one capacitor, wherein each shifting registering circuit comprises a pulling-up transistor, a first pulling-down transistor and a second pulling-down transistor of a signal output module, a third pulling-down transistor, a switching transistor, a first capacitor, a resetting transistor, a first auxiliary pulling-down transistor and a second auxiliary pulling-down transistor of an auxiliary pulling-down module, a third auxiliary pulling-down transistor and a second capacitor; and the third auxiliary pulling-down transistor and the second capacitor are connected in parallel. The second capacitor is used as a buffering device and can filter surplus burr signals in output signals to reduce signal crosstalk; and meanwhile, the first pulling-down transistor and the second pulling-down transistor can respectively work in a half pulling-down period so that the drifting of threshold voltage, caused by too big width-length ratio of the transistor is inhibited and the stability of a circuit is further guaranteed. The auxiliary pulling-down module is arranged so that an output waveform of a second node is more stable.
Description
Technical field
The present invention relates to the liquid crystal flat-panel display technique, relate in particular to a kind of shift register and Thin Film Transistor-LCD.
Background technology
Begin to develop rapidly and progressively move to maturity from the nineties in 20th century for the FPD of representative (flat-panel display device) technology with TFT-LCD (Thin film transistor-Liquid crystal display, Thin Film Transistor-LCD).Because TFT-LCD has high-resolution, low-power consumption, frivolous, advantage such as be easy to carry, and has been widely used in above-mentioned information to show in the product, make LCD enter the new stage that high image quality, high color show, have vast market prospect.All used tft active matrix among the LCD of present nearly all top grade without any exception.TFT (Thin film transistor) active matrix mainly comprises two kinds of A-Si (amorphous silicon) tft active matrix and P-Si (poly-silicon) tft active matrixs.Compare with P-Si TFT technology, A-Si TFT technical development comparative maturity, good uniformity and cost are lower, but its mobility is lower, generally at 0.1～1.0cm
2/ Vs, the mobility of P-Si TFT then can reach 50～200cm
2/ Vs.Because A-Si TFT mobility ratio is lower, causes its driving circuit speed slower.
Small-medium size LCD is mainly used in portable product, and is therefore different with large-scale LCD on technical feature requires.The small-medium size product is emphasized the integration capability of light, thin, the device of display, better reliability and low cost more.At present, market has also proposed requirements at the higher level to the resolution of LCD, has high resolving power in order to make miniaturization LCD, and the number that reduces the TFT-LCD drive IC is very important.Usually, when the resolution of LCD was higher than QVGA (240 * RGB * 320), the TFT panel need surpass 1000 outside leads.When product resolution further increases, in limited space, make more outer lead and just become very difficult.
Above technical matters can be by being integrated in driving circuit (gate driver circuits or source driver circuits) on the thin film transistor substrate and solving.This technology can make, and the display cost is lower, more compact structure, thereby Mechanical Reliability is higher makes it have the bigger market competitiveness.
And the development along with technology, sweep circuit trends towards circuit integration, increasing company adopts shift register to replace turntable driving IC, thereby reduced the display bezel size of LCD, be integrated on the display panel owing to circuit simultaneously, also reduce the usage quantity of IC, thereby greatly reduced the cost of manufacture of display panel.
Along with high-end product is more and more pursued narrow frame and lightness, therefore the dimensional requirement of shift register circuit constantly reduces, shift register circuit is the demonstration as driving circuit control thin film transistor substrate simultaneously, so require shift register circuit that stable electric current can be provided.
Therefore, provide a kind of number of transistors that the shift register that overall dimensions is little and the signal waveform that provides of work is stable is provided less and become the problem of industry extensive concern by the Thin Film Transistor-LCD that the cascade of this kind shift register forms.
Summary of the invention
Technical matters to be solved by this invention provides the shift register that a kind of number of transistors is few, work wave is stable and the Thin Film Transistor-LCD that is formed by the cascade of this kind shift register.
For addressing the above problem, the invention provides a kind of shift register, comprise the shift register circuit of multi-stage cascade, each shift register circuit comprises:
Primary input end and main output terminal;
Signal output module, comprise and be respectively coupled to the pulling up transistor of described main output terminal, first pull-down transistor, second pull-down transistor, the described input termination first node that pulls up transistor, described pulling up transistor in order to when opening, to produce the described main output terminal that outputs signal to of high level, described first pull-down transistor and second pull-down transistor are in order to alternately to produce the low level described main output terminal that outputs signal to, the input termination Section Point of described second pull-down transistor when opening;
Switching transistor is coupled between described primary input end and the described first node, in order to the described unlatching that pulls up transistor of input signal control according to master clock signal and primary input end;
First electric capacity is coupled between described first node and the described main output terminal, provides burning voltage in order to utilize the electric capacity bootstrap effect for described pulling up transistor;
Reset transistor is coupled to described first node, in order to control the described replacement of closing the output signal of exporting with described main output terminal that pulls up transistor; And
Drop-down supplementary module, be coupled to described main output terminal and described Section Point, in order to realize that described first pull-down transistor and second pull-down transistor alternately produce low level output signal, described drop-down supplementary module comprises: the first auxiliary pull-down transistor, in order to discharge the high level of described Section Point fast according to master clock signal; The second auxiliary pull-down transistor is the level of the described Section Point of FEEDBACK CONTROL in order to the output signal according to described main output terminal, and then stablizes the level of described main output terminal; And the 3rd auxiliary pull-down transistor, in order to draw high the level of described Section Point according to described from clock signal, described anti-phase from clock signal and described master clock signal; Described signal output module also comprises the 3rd pull-down transistor, and the input termination first node of described the 3rd pull-down transistor is used for the level according to the drop-down first node of Section Point of the last shift register circuit of place shift register circuit.
Further, in described shift register, the switching transistor of first order shift register circuit receives initialize signal, and the switching transistor of every grade of shift register circuit is coupled to the main output terminal of its prime shift register circuit thereafter; The switching transistor of afterbody shift register circuit receives final reset signal, and the reset transistor of other every grade shift register circuit is coupled to the main output terminal of level shift register circuit thereafter.
Further, describedly pull up transistor, first pull-down transistor, second pull-down transistor, the 3rd pull-down transistor, switching transistor, reset transistor, the first auxiliary pull-down transistor, the second auxiliary pull-down transistor and the 3rd auxiliary pull-down transistor be Thin Film Transistor (TFT).
Further, in each shift register circuit: in described signal output module: the described grid that pulls up transistor connects first node, source electrode and connects and describedly connect described main output terminal from clock signal, drain electrode; The grid of described first pull-down transistor connects described master clock signal, source electrode and connects described main output terminal, misses and connect low level end; The grid of described second pull-down transistor connects that Section Point, source electrode connect described main output terminal, drain electrode connects low level end; The source electrode of described the 3rd pull-down transistor connects the drop-down Section Point of Section Point, the drain electrode that first node, grid connect the last shift register circuit of its place shift register circuit and connects low level end; The grid of described switching transistor connects that described master clock signal, source electrode connect described primary input end, drain electrode connects described first node; Main output terminal, the source electrode that the grid of described reset transistor connects back one shift register circuit connects described first node, drain electrode connects low level end; And in described drop-down supplementary module: the grid of the described first auxiliary pull-down transistor connects that described master clock signal, source electrode connect described Section Point, drain electrode connects described low level end; The grid of the described second auxiliary pull-down transistor connects that described main output terminal, source electrode connect described Section Point, drain electrode connects described low level end; The grid of the described the 3rd auxiliary pull-down transistor and drain electrode connect and describedly connect described Section Point from clock signal, source electrode.
Further, the breadth length ratio of the described the 3rd auxiliary pull-down transistor is greater than the breadth length ratio of the described second auxiliary pull-down transistor.
Further, the breadth length ratio of the described the 3rd auxiliary pull-down transistor is greater than ten times of the breadth length ratio of the described second auxiliary pull-down transistor.
Further, described first electric capacity connects between described first node and the main output terminal.
Further, the working time of described first pull-down transistor and second pull-down transistor is respectively half of drop-down cycle.
Further, shift register circuit is divided into odd level shift register circuit and even level shift register circuit in the described shift register, and the master clock signal that the master clock signal that described odd level shift register circuit receives and described even level shift register circuit receive is anti-phase.
The present invention also provides a kind of Thin Film Transistor-LCD, comprises array of display and gate driver circuit, describedly controls described array of display in order to produce a plurality of signals, and described gate driver circuit comprises aforesaid shift register.
In sum, the shift register circuit of shift register of the present invention utilizes output signal as the stable output of the further control signal of feedback, thereby reach the purpose of current stabilization control actuation voltage, adopt two pull-down transistors to carry out drop-down to output terminal simultaneously, and can utilize drop-down cycle of 100% to carry out fully drop-down, avoided floating dummy status, so the time circuit stable.
Further, shift register increase of the present invention arranges described the 3rd pull-down transistor, described the 3rd pull-down transistor can be according to the level of the first node of the current shift register circuit of Control of Voltage of the Section Point of the last shift register circuit of place shift register circuit drop-down, thereby the drop-down current potential that keeps first node, and then the whole driving force of optimization shift register.
The present invention also provides a kind of Thin Film Transistor-LCD of being made up of aforesaid shift register, described Thin Film Transistor-LCD comprises array of display and gate driver circuit, described shift register is controlled described array of display in order to produce a plurality of signals, and described gate driver circuit comprises the aforesaid shift register of employing.Adopt the demonstration of the Thin Film Transistor-LCD that shift register of the present invention forms more stable, reaction velocity is faster, and has reduced panel size, realizes the smooth volume production of high-end frivolous product, further reduces production costs.
Description of drawings
Fig. 1 is the structural representation of shift register in one embodiment of the invention.
Fig. 2 is the structural representation of shift register circuit in one embodiment of the invention.
Fig. 3 is the signal timing diagram in the shift register course of work in one embodiment of the invention.
Fig. 4 is the signal timing diagram of the course of work of shift register and prior art one shift register circuit in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes synoptic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, synoptic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 1 is the structural representation of shift register in one embodiment of the invention, and as shown in Figure 1, the shift register circuit of described shift register produces signal control array of display successively and carries out the image demonstration.Wherein, in the present embodiment, shift register circuit is divided into odd level shift register circuit and even level shift register circuit in the described shift register, the master clock signal that the master clock signal that described odd level shift register circuit receives and described even level shift register circuit receive is anti-phase, it is corresponding first clock signal clk that receives of master clock signal CK1 that the odd level shift register circuit receives, the corresponding second clock signal CLKB that receives of the master clock signal CK2 that corresponding described even level shift register circuit receives, first clock signal clk and second clock signal CLKB are anti-phase.And the switching transistor M1 of first order shift register circuit receives initialize signal STP, thereafter the switching transistor M1 of every grade of shift register circuit is coupled to the main output terminal OUT of its prime shift register circuit, namely the switching transistor M1 of N+1 level shift register circuit is coupled to the main output terminal OUT of N level shift register circuit, and wherein N is the positive integer less than the shift register circuit sum; The reset transistor M2 of afterbody shift register circuit receives final reset signal, the reset transistor M2 of other every grade shift register circuit is coupled to the main output terminal OUT of level shift register circuit thereafter, thereby realize the output signal control unlatching of a shift register circuit thereafter of each shift register circuit, the output signal of each shift register circuit is controlled resetting of its last shift register circuit, makes the shift register circuit output signal output successively in the shift register.
Fig. 2 is the structural representation of shift register circuit in one embodiment of the invention.In conjunction with Fig. 1 and Fig. 2, the invention provides a kind of shift register, the shift register circuit that comprises multi-stage cascade, each shift register circuit comprises: primary input end IN and main output terminal OUT, signal output module 100, switching transistor M1, first capacitor C 1, reset transistor M2 and auxiliary drop-down module 200.
Described signal output module 100 comprises the M3 that pulls up transistor, the first pull-down transistor M6 and the second pull-down transistor M8 that is respectively coupled to described main output terminal OUT, the input termination first node of the described M3 that pulls up transistor, the described M3 of pulling up transistor is in order to produce the described main output terminal Out that outputs signal to of high level when opening, the described first pull-down transistor M6 and the second pull-down transistor M8 are in order to alternately to produce the low level described main output terminal Out that outputs signal to, the input termination Section Point Q of the described second pull-down transistor M8 when opening;
Described switching transistor M1 is coupled between described primary input end and the described first node P, in order to control the unlatching of the described M3 that pulls up transistor according to the input signal of master clock signal CK1 and primary input end IN;
Described first capacitor C 1 is coupled between described first node P and the described main output terminal OUT, provides burning voltage in order to utilize the electric capacity bootstrap effect for the described M3 of pulling up transistor;
Described reset transistor M2 is coupled to described first node P, in order to control the replacement of closing the output signal of exporting with described main output terminal IN of the described M3 of pulling up transistor; And
Described auxiliary drop-down module 200 is coupled to described main output terminal IN and described Section Point Q, in order to realize that the described first pull-down transistor M6 and the second pull-down transistor M8 alternately produce low level output signal, described auxiliary drop-down module comprises: the first auxiliary pull-down transistor M5, in order to discharge the high level of described Section Point Q fast according to master clock signal; The second auxiliary pull-down transistor M7 is the level of the described Section Point Q of FEEDBACK CONTROL in order to the output signal according to described main output terminal OUT, and then stablizes the level of described main output terminal OUT; And the 3rd auxiliary pull-down transistor M4, in order to draw high the level of described Section Point according to described from clock signal, wherein said anti-phase from clock signal and described master clock signal.In addition, described signal output module also comprises the 3rd pull-down transistor M9, and the input termination first node P of described the 3rd pull-down transistor M9 is used for the level according to the drop-down first node P of Section Point of the last shift register circuit of place shift register circuit.The level of the first node P of the drop-down shift register circuit at the corresponding levels of signal of the Section Point Q by the previous stage shift register circuit, thus make shift register circuit more stable.
Simultaneously, auxiliary drop-down module 200 is the structure of parallel resistance in the described shift register circuit, so the output waveform of Section Point Q can reach high level sooner, and then makes signal reaction speed faster, makes final output waveform more stable.
Shift register of the present invention has the shift register circuit of a plurality of cascades, and each grade shift register circuit comprises nine transistors and an electric capacity, the i.e. circuit structure of 9T1C.Wherein, M1 is switching transistor, and M2 is reset transistor, and M3 pulls up transistor, and M6 is first pull-down transistor, and M8 is second pull-down transistor, and M5, M7 and M4 are respectively first to the 3rd auxiliary pull-down transistor, and M9 is the 3rd pull-down transistor.Transistor size that shift register circuit of the present invention uses is few, can effectively reduce the frame size, reduces the size of panel, and effectively reduces the cost of panel; Simultaneously, guaranteed the shift register circuit operate as normal, circuit is stable, and improves reaction velocity.In the present embodiment, the described M3 of pulling up transistor, the first pull-down transistor M6, the second pull-down transistor M8, the 3rd pull-down transistor M9, switching transistor M1, reset transistor M2, the first auxiliary pull-down transistor M5, the second auxiliary pull-down transistor M6 and the 3rd auxiliary pull-down transistor M4 are Thin Film Transistor (TFT).
In each shift register circuit: in described signal output module: the grid of the described M3 of pulling up transistor connects that first node P, source electrode meet described clock signal C K2, drain electrode meets described main output terminal OUT; The grid of the described first pull-down transistor M6 meets described master clock signal CK1, source electrode and connects described main output terminal, misses and connect low level end; The grid of the described second pull-down transistor M8 connects that Section Point Q, source electrode meet described main output terminal OUT, drain electrode meets low level end VGL; The grid of described switching transistor M1 connects that described master clock signal CK1, source electrode meet described primary input end IN, drain electrode meets described first node P; Main output terminal OUT, the source electrode that the grid of described reset transistor M2 connects back one shift register circuit meets described first node P, drain electrode meets low level end VGL; And in described auxiliary drop-down module: the grid of the described first auxiliary pull-down transistor M5 connects that described master clock signal CK1, source electrode meet described Section Point Q, drain electrode meets described low level end VGL; The grid of the described second auxiliary pull-down transistor M7 connects that described main output terminal OUT, source electrode meet described Section Point Q, drain electrode meets described low level end VGL; The grid of the described the 3rd auxiliary pull-down transistor M4 and drain electrode connect and describedly meet described Section Point Q from clock signal C K2, source electrode.Auxiliary drop-down module is the structure of parallel resistance in the described shift register circuit, so the output waveform that Q order can reach high level sooner, and then makes signal reaction speed faster, and the raising reaction velocity also makes final output waveform more stable.
Fig. 3 is the signal timing diagram in the shift register course of work in one embodiment of the invention.In conjunction with Fig. 2 and Fig. 3, the effect of the first auxiliary pull-down transistor M5 mainly is the high voltage that discharges Section Point Q, make the second pull-down transistor M8 can be operated in cycle of 50%, the level that adds first pull-down transistor M6 master's output terminal OUT when main clock pulse signal CK1 output high impulse is drop-down, thereby make described shift register circuit reach for 100% drop-down cycle, thereby avoided floating dummy status not floating null cycle, and then make circuit stable.
In preferred embodiment, the breadth length ratio of the described the 3rd auxiliary pull-down transistor M4 is greater than the breadth length ratio of the described second auxiliary pull-down transistor M7.In preferred embodiment, the breadth length ratio of the described the 3rd auxiliary pull-down transistor M4 is greater than ten times of the breadth length ratio of the described second auxiliary pull-down transistor M7.Described shift register circuit provides output signal by main output terminal OUT, this output signal feedback second auxiliary pull-down transistor M7, because the breadth length ratio of the second auxiliary pull-down transistor M7 is much larger than the 3rd auxiliary breadth length ratio of trombone slide M4 down, so the electric current of current ratio the 3rd auxiliary trombone slide M4 down of the second auxiliary pull-down transistor M7 is bigger, make the electric current of Section Point Q more near the voltage of the low level VGL of the second auxiliary pull-down transistor M7 conducting, form waveform as shown in Figure 3, thus a feasible high pulse signal that has filtered out from clock signal C K2.
Further, described first capacitor C 1 connects between described first node P and the main output terminal OUT.
Further, the working time of the described first pull-down transistor M6 and the second pull-down transistor M8 is respectively half of drop-down cycle.Because each comfortable half drop-down cycling of the first pull-down transistor M6 and the second pull-down transistor M8 has also suppressed the drift because of the excessive threshold voltage of transistor breadth length ratio, and then has guaranteed the stability of circuit.By auxiliary drop-down module 200 is set, can make the output waveform of Section Point more stable.
Fig. 4 is P point signal timing diagram in the course of work of shift register and prior art one shift register circuit in one embodiment of the invention.The signal timing diagram of first node P in the course of work of shift register circuit shown in Figure 2 is adopted in meander line 200 expression among Fig. 4, and the signal timing diagram of the first node in the course of the work of the shift register circuit that the 3rd pull-down transistor is not set of a kind of prior art of meander line 100 expressions, as shown in Figure 4, before first node P charging enters noble potential, can be seen by the A point, the first node P of shift register circuit of the present invention maintains-low-voltage of 10V, can be seen by the B point, and the voltage of the first node P of the shift register circuit of prior art is-8.264V, can be seen by the C point, after increasing by the 3rd pull-down transistor, the further drop-down 2.1107V of the electrical potential energy of first node P point before entering noble potential, thus optimization actuation voltage and hold facility are greatly improved.Hence one can see that, increases the pull-down capability that the 3rd pull-down transistor can keep first node P, thereby optimize the driving force of shift register circuit, and then optimize the whole driving force of shift register.
In sum, the shift register circuit of shift register of the present invention utilizes output signal as the stable output of the further control signal of feedback, thereby reach the purpose of current stabilization control actuation voltage, adopt two pull-down transistors to carry out drop-down to output terminal simultaneously, and can utilize drop-down cycle of 100% to carry out fully drop-down, avoided floating dummy status, so the time circuit stable.
Further, shift register increase of the present invention arranges described the 3rd pull-down transistor, described the 3rd pull-down transistor can be according to the level of the first node of the current shift register circuit of Control of Voltage of the Section Point of the last shift register circuit of place shift register circuit drop-down, thereby the drop-down current potential that keeps first node, and then the whole driving force of optimization shift register.
The present invention also provides a kind of Thin Film Transistor-LCD of being made up of aforesaid shift register, described Thin Film Transistor-LCD comprises array of display and gate driver circuit, described shift register is controlled described array of display in order to produce a plurality of signals, and described gate driver circuit comprises the aforesaid shift register of employing.Adopt the demonstration of the Thin Film Transistor-LCD that shift register of the present invention forms more stable, reaction velocity is faster, and has reduced panel size, realizes the smooth volume production of high-end frivolous product, further reduces production costs.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. shift register comprises the shift register circuit of multi-stage cascade, and each shift register circuit comprises:
Primary input end and main output terminal;
Signal output module, comprise and be respectively coupled to the pulling up transistor of described main output terminal, first pull-down transistor, second pull-down transistor, the described input termination first node that pulls up transistor, described pulling up transistor in order to when opening, to produce the described main output terminal that outputs signal to of high level, described first pull-down transistor and second pull-down transistor are in order to alternately to produce the low level described main output terminal that outputs signal to, the input termination Section Point of described second pull-down transistor when opening;
Switching transistor is coupled between described primary input end and the described first node, in order to the described unlatching that pulls up transistor of input signal control according to master clock signal and primary input end;
First electric capacity is coupled between described first node and the described main output terminal, provides burning voltage in order to utilize the electric capacity bootstrap effect for described pulling up transistor;
Reset transistor is coupled to described first node, in order to control the described replacement of closing the output signal of exporting with described main output terminal that pulls up transistor; And
Drop-down supplementary module is coupled to described main output terminal and described Section Point, alternately produces low level output signal in order to realize described first pull-down transistor and second pull-down transistor, and described drop-down supplementary module comprises:
The first auxiliary pull-down transistor is in order to discharge the high level of described Section Point fast according to master clock signal;
The second auxiliary pull-down transistor is the level of the described Section Point of FEEDBACK CONTROL in order to the output signal according to described main output terminal, and then stablizes the level of described main output terminal; And
The 3rd auxiliary pull-down transistor, in order to according to the level of drawing high described Section Point from clock signal, described anti-phase from clock signal and described master clock signal;
Described signal output module also comprises the 3rd pull-down transistor, and the input termination first node of described the 3rd pull-down transistor is used for the level according to the drop-down first node of Section Point of the last shift register circuit of place shift register circuit.
2. shift register as claimed in claim 1, it is characterized in that, in described shift register, the switching transistor of first order shift register circuit receives initialize signal, and the switching transistor of every grade of shift register circuit is coupled to the main output terminal of its prime shift register circuit thereafter; The switching transistor of afterbody shift register circuit receives final reset signal, and the reset transistor of other every grade shift register circuit is coupled to the main output terminal of level shift register circuit thereafter.
3. shift register as claimed in claim 2, it is characterized in that, describedly pull up transistor, first pull-down transistor, second pull-down transistor, the 3rd pull-down transistor, switching transistor, reset transistor, the first auxiliary pull-down transistor, the second auxiliary pull-down transistor and the 3rd auxiliary pull-down transistor be Thin Film Transistor (TFT).
4. shift register as claimed in claim 3 is characterized in that, in each shift register circuit:
In described signal output module: the described grid that pulls up transistor connects first node, source electrode and connects and describedly connect described main output terminal from clock signal, drain electrode; The grid of described first pull-down transistor connects described master clock signal, source electrode and connects described main output terminal, misses and connect low level end; The grid of described second pull-down transistor connects that Section Point, source electrode connect described main output terminal, drain electrode connects low level end; The source electrode of described the 3rd pull-down transistor connects the drop-down Section Point of Section Point, the drain electrode that first node, grid connect the last shift register circuit of its place shift register circuit and connects low level end;
The grid of described switching transistor connects that described master clock signal, source electrode connect described primary input end, drain electrode connects described first node;
Main output terminal, the source electrode that the grid of described reset transistor connects back one shift register circuit connects described first node, drain electrode connects low level end; And in described drop-down supplementary module:
The grid of the described first auxiliary pull-down transistor connects that described master clock signal, source electrode connect described Section Point, drain electrode connects described low level end;
The grid of the described second auxiliary pull-down transistor connects that described main output terminal, source electrode connect described Section Point, drain electrode connects described low level end;
The grid of the described the 3rd auxiliary pull-down transistor and drain electrode connect and describedly connect described Section Point from clock signal, source electrode.
5. shift register as claimed in claim 4 is characterized in that, the breadth length ratio of the described the 3rd auxiliary pull-down transistor is greater than the breadth length ratio of the described second auxiliary pull-down transistor.
6. shift register as claimed in claim 5 is characterized in that, the breadth length ratio of the described the 3rd auxiliary pull-down transistor is greater than ten times of the breadth length ratio of the described second auxiliary pull-down transistor.
7. shift register as claimed in claim 3 is characterized in that, described first electric capacity connects between described first node and the main output terminal.
8. as any described shift register in the claim 1 to 7, it is characterized in that the working time of described first pull-down transistor and second pull-down transistor is respectively half of drop-down cycle.
9. as any described shift register in the claim 1 to 7, it is characterized in that, shift register circuit is divided into odd level shift register circuit and even level shift register circuit in the described shift register, and the master clock signal that the master clock signal that described odd level shift register circuit receives and described even level shift register circuit receive is anti-phase.
10. Thin Film Transistor-LCD, it is characterized in that, comprise array of display and gate driver circuit, described gate driver circuit is controlled described array of display in order to produce a plurality of signals, and described gate driver circuit comprises as any described shift register in the claim 1 to 9.
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| CN103295642A (en) * | 2012-09-19 | 2013-09-11 | 上海中航光电子有限公司 | Shifting register and panel display |
| CN103928007A (en) * | 2014-04-21 | 2014-07-16 | 深圳市华星光电技术有限公司 | GOA circuit and LCD device for LCD |
| CN104021764A (en) * | 2014-06-18 | 2014-09-03 | 上海和辉光电有限公司 | Light-emitting signal control circuit |
| CN104091572A (en) * | 2014-06-17 | 2014-10-08 | 京东方科技集团股份有限公司 | Double pull-down control module, shift register unit, grid driver and display panel |
| CN104952417A (en) * | 2015-07-23 | 2015-09-30 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, grid drive circuit and display device |
| WO2015161536A1 (en) * | 2014-04-22 | 2015-10-29 | 深圳市华星光电技术有限公司 | Drive circuit for display panel and drive method therefor |
| CN105469759A (en) * | 2015-12-15 | 2016-04-06 | 深圳市华星光电技术有限公司 | Shift register |
| US9396682B2 (en) | 2014-01-27 | 2016-07-19 | Shanghai Avic Opto Electronics Co., Ltd. | Gate driving circuit, TFT array substrate, and display device |
| WO2016188033A1 (en) * | 2015-05-28 | 2016-12-01 | 京东方科技集团股份有限公司 | Shift register unit, drive method, gate drive circuit and display device |
| CN107068032A (en) * | 2017-01-22 | 2017-08-18 | 上海中航光电子有限公司 | A kind of scanning element and gate driving circuit |
| CN111145678A (en) * | 2020-02-19 | 2020-05-12 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, driving circuit and display device |
| WO2020108344A1 (en) * | 2018-11-26 | 2020-06-04 | Boe Technology Group Co., Ltd. | Shift register unit, shift register and driving method, and display apparatus |
| WO2022022096A1 (en) * | 2020-07-31 | 2022-02-03 | 京东方科技集团股份有限公司 | Gate driving circuit and display panel |
| WO2023201656A1 (en) * | 2022-04-21 | 2023-10-26 | 京东方科技集团股份有限公司 | Display panel and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093647A (en) * | 2006-06-21 | 2007-12-26 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN101533623A (en) * | 2009-02-26 | 2009-09-16 | 深圳华映显示科技有限公司 | Gate drive for inhibiting drift of a critical voltage |
| CN101625841A (en) * | 2009-07-29 | 2010-01-13 | 友达光电股份有限公司 | Liquid crystal display and shift registering device |
| US20100231497A1 (en) * | 2009-03-13 | 2010-09-16 | Yi-Suei Liao | Display device providing bi-directional voltage stabilization |
-
2012
- 2012-09-19 CN CN201210350350.1A patent/CN103280196B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093647A (en) * | 2006-06-21 | 2007-12-26 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN101533623A (en) * | 2009-02-26 | 2009-09-16 | 深圳华映显示科技有限公司 | Gate drive for inhibiting drift of a critical voltage |
| US20100231497A1 (en) * | 2009-03-13 | 2010-09-16 | Yi-Suei Liao | Display device providing bi-directional voltage stabilization |
| CN101625841A (en) * | 2009-07-29 | 2010-01-13 | 友达光电股份有限公司 | Liquid crystal display and shift registering device |
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|---|---|---|---|---|
| CN103295642A (en) * | 2012-09-19 | 2013-09-11 | 上海中航光电子有限公司 | Shifting register and panel display |
| CN103295642B (en) * | 2012-09-19 | 2016-02-17 | 上海中航光电子有限公司 | Shift register and panel display apparatus |
| US9396682B2 (en) | 2014-01-27 | 2016-07-19 | Shanghai Avic Opto Electronics Co., Ltd. | Gate driving circuit, TFT array substrate, and display device |
| CN103928007A (en) * | 2014-04-21 | 2014-07-16 | 深圳市华星光电技术有限公司 | GOA circuit and LCD device for LCD |
| CN103928007B (en) * | 2014-04-21 | 2016-01-20 | 深圳市华星光电技术有限公司 | A kind of GOA circuit for liquid crystal display and liquid crystal indicator |
| WO2015161536A1 (en) * | 2014-04-22 | 2015-10-29 | 深圳市华星光电技术有限公司 | Drive circuit for display panel and drive method therefor |
| CN104091572A (en) * | 2014-06-17 | 2014-10-08 | 京东方科技集团股份有限公司 | Double pull-down control module, shift register unit, grid driver and display panel |
| CN104021764B (en) * | 2014-06-18 | 2016-06-29 | 上海和辉光电有限公司 | A kind of luminous signal control circuit |
| CN104021764A (en) * | 2014-06-18 | 2014-09-03 | 上海和辉光电有限公司 | Light-emitting signal control circuit |
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| CN104952417A (en) * | 2015-07-23 | 2015-09-30 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, grid drive circuit and display device |
| CN105469759A (en) * | 2015-12-15 | 2016-04-06 | 深圳市华星光电技术有限公司 | Shift register |
| US10115355B2 (en) | 2015-12-15 | 2018-10-30 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Shift register |
| CN107068032A (en) * | 2017-01-22 | 2017-08-18 | 上海中航光电子有限公司 | A kind of scanning element and gate driving circuit |
| CN107068032B (en) * | 2017-01-22 | 2020-06-12 | 上海中航光电子有限公司 | Scanning unit and gate drive circuit |
| US11295652B2 (en) | 2018-11-26 | 2022-04-05 | Beijing Boe Technology Development Co., Ltd. | Shift register unit, shift register and driving method, and display apparatus |
| WO2020108344A1 (en) * | 2018-11-26 | 2020-06-04 | Boe Technology Group Co., Ltd. | Shift register unit, shift register and driving method, and display apparatus |
| CN111145678A (en) * | 2020-02-19 | 2020-05-12 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, driving circuit and display device |
| CN111145678B (en) * | 2020-02-19 | 2022-02-25 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, driving circuit and display device |
| US11783743B2 (en) | 2020-02-19 | 2023-10-10 | Beijing Boe Technology Development Co., Ltd. | Shifting register, driving method thereof, driving circuit and display device |
| WO2022022096A1 (en) * | 2020-07-31 | 2022-02-03 | 京东方科技集团股份有限公司 | Gate driving circuit and display panel |
| WO2023201656A1 (en) * | 2022-04-21 | 2023-10-26 | 京东方科技集团股份有限公司 | Display panel and display device |
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