CN103107791B - Gain linear variable gain amplifier with constant bandwidth - Google Patents

Abstract

The invention discloses a gain linear variable gain amplifier with constant bandwidth. The variable gain amplifier includes a common-source stage amplifier and a gain adjustment network; the common-source stage amplifier includes a first N-type metal oxide transistor, a fifth N-type metal An oxide transistor, a first P-type metal oxide transistor, a second P-type metal oxide transistor, and a first current source; the gain adjustment network includes second to eighth N-type metal oxide transistors, second to tenth current sources and the first to fifteenth switches. The amplifier with this structure has the characteristic of constant bandwidth, and at the same time, through different control words, the gain can achieve a precise linear effect.

Description

Constant Bandwidth Gain Linear Variable Gain Amplifier

technical field

The invention relates to an amplifier, in particular to a gain linear variable gain amplifier with constant bandwidth.

Background technique

In the radio frequency signal receiving chain, the role of the variable gain amplifier is to ensure the constant output signal within the range of input signal variation. Considering the entire receiving chain, the amplifier should have high linearity. In addition, as one of the main parts of the intermediate frequency module, the variable gain amplifier should have a good bandwidth to ensure stable transmission of signals and more effective suppression of non-band signals.

Variable gain amplifiers can be divided into analog signal control variable gain amplifiers and digital signal control variable gain amplifiers according to different control signals. The analog control variable gain amplifier requires a separate construction of an exponential voltage generation circuit, which is difficult to implement in CMOS. The digital control variable gain amplifier realizes the dB linearity of the gain by controlling the digital encoding method. Compared with the analog signal control variable gain amplifier, the digital signal control variable gain amplifier does not need to construct an exponential voltage generation circuit separately, and can optimize the gain value at discrete points, improve the gain accuracy, and is also conducive to low power consumption. Therefore, the digital variable gain amplifier has increasingly become the mainstream method in the radio frequency receiving chain.

Digital variable gain amplifiers are mainly divided into open-loop and closed-loop structures. Both of them realize the dB linear relationship between the gain and the digital signal through the digital signal control switch. The closed-loop structure achieves variable gain by changing the feedback network to change the feedback factor. Its gain accuracy is high, but it has disadvantages such as small bandwidth and high power consumption; the open-loop structure mainly achieves gain by changing the equivalent transconductance or output impedance. Variable, generally the gain control range is larger, the bandwidth is wider, the power consumption is lower, but the gain accuracy is poor. There are many common open-loop structures. A variable-gain amplifier based on a programmable load can realize a linear change in gain in dB, but the bandwidth of the amplifier will decrease as the gain increases. The variable gain amplifier based on the diode load differential pair changes the gain of the amplifier by changing the transconductance of the input tube and the load tube, and also faces the problem of bandwidth change.

At the same time, the general variable gain amplifier based on programmable transconductance changes the transconductance of the input tube by simply changing the size of the input tube or changing the bias current. When a single change in size or current occurs, the overdrive voltage of the input tube Changes will cause the drain-source voltage of the transistor as the bias current source to change, so that the error of the current source generated by the current mirror will change greatly.

Contents of the invention

Purpose of the invention: For the problems and deficiencies in the above-mentioned prior art, the purpose of the invention is to provide a gain linear variable gain amplifier with constant bandwidth. The amplifier of this structure has the characteristics of constant bandwidth. On and off can make the gain achieve a precise linear relationship.

Technical solution: In order to achieve the purpose of the above invention, the technical solution adopted in the present invention is a gain linear variable gain amplifier with constant bandwidth, and the variable gain amplifier includes a common source stage amplifier and a gain adjustment network; wherein:

The common source stage amplifier includes a first N-type metal oxide transistor, a fifth N-type metal oxide transistor, a first P-type metal oxide transistor, a second P-type metal oxide transistor and a first current source;

The gain adjustment network includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a Eight N-type metal oxide transistors, second current source, third current source, fourth current source, fifth current source, sixth current source, seventh current source, eighth current source, ninth current source, tenth current source Current source, first switch, second switch, third switch, fourth switch, fifth switch, sixth switch, seventh switch, eighth switch, ninth switch, tenth switch, eleventh switch, tenth switch The second switch, the thirteenth switch, the fourteenth switch and the fifteenth switch;

The positive end of the input signal is connected to the gates of the first N-type metal oxide transistor, the second N-type metal oxide transistor, the third N-type metal oxide transistor and the fourth N-type metal oxide transistor; the first N-type metal oxide transistor The drain of the oxide transistor is connected to the drain of the first P-type metal oxide transistor, the drain of the first P-type metal oxide transistor is connected to the gate, and the source of the first P-type metal oxide transistor is connected to the power supply voltage ; The source of the first N-type metal oxide transistor and the source of the second N-type metal oxide transistor, the source of the third N-type metal oxide transistor, the source of the fourth N-type metal oxide transistor, the first The source of the five N-type metal oxide transistors, the source of the sixth N-type metal oxide transistor, the source of the seventh N-type metal oxide transistor, and the source of the eighth N-type metal oxide transistor are connected to each other simultaneously. One end of the first current source, the first switch, the second switch and the third switch are connected; the other end of the first switch is connected with one end of the second current source, and the other end of the second switch is connected with one end of the third current source, The other end of the third switch is connected to one end of the fourth current source; the other end of the first current source, the second current source, the third current source and the fourth current source are grounded; one end of the fourth switch is connected to the second N-type metal The drain of the oxide transistor is connected, one end of the fifth switch is connected to the drain of the third N-type metal oxide transistor, one end of the sixth switch is connected to the drain of the fourth N-type metal oxide transistor; the fourth switch, The other ends of the fifth switch and the sixth switch are connected to the drain of the first N-type metal oxide transistor, and at the same time connected to one end of the tenth switch, the eleventh switch and the twelfth switch, as the positive end of the output signal of the amplifier The other end of the tenth switch is connected with one end of the seventh current source, the other end of the eleventh switch is connected with one end of the sixth current source, and the other end of the twelfth switch is connected with one end of the fifth current source; the fifth The other terminals of the current source, the sixth current source and the seventh current source are connected to the power supply voltage; the negative terminal of the input signal is connected to the fifth N-type metal oxide transistor, the sixth N-type metal oxide transistor, and the seventh N-type metal oxide transistor It is connected to the gate of the eighth N-type metal oxide transistor; the drain of the fifth N-type metal oxide transistor is connected to the drain of the second P-type metal oxide transistor, and the drain of the second P-type metal oxide transistor Connected to the gate, the source of the second P-type metal oxide transistor is connected to the power supply voltage; one end of the seventh switch is connected to the drain of the sixth N-type metal oxide transistor, and one end of the eighth switch is connected to the seventh N-type metal oxide transistor. The drain of the oxide transistor is connected, one end of the ninth switch is connected to the drain of the eighth N-type metal oxide transistor; the other end of the seventh switch, the eighth switch, and the ninth switch is connected to the fifth N-type metal oxide transistor connected to the drain of the thirteenth switch, the fourteenth switch and one end of the fifteenth switch at the same time as the negative end of the output signal of the amplifier; the other end of the thirteenth switch is connected to one end of the eighth current source, and the The other end of the fourteenth switch is connected to one end of the ninth current source, and the other end of the fifteenth switch is connected to one end of the tenth current source; the eighth current source, the ninth current source and The other end of the tenth current source is connected to the power supply voltage.

Beneficial effects: compared with the prior art, the present invention has the following beneficial effects:

1. Constant bandwidth. The variable gain amplifier of the present invention is in the last stage of the analog signal chain of the receiver system, and the input signal of the amplifier works in a low frequency state. In the variable gain amplifier of the present invention, the bandwidth is slightly affected by the change of the gain and basically remains unchanged, so that signals outside the bandwidth can be better filtered out. The variable gain amplifier with constant bandwidth of the present invention connects the first P-type metal oxide transistor and the second P-type metal oxide transistor in a diode manner and acts as a differential two-way load, and controls the parallel current source through the switch control word so that The current flowing through the first PMOS transistor and the second PMOS transistor does not ensure that the impedance thereof remains unchanged. The impedance of the first PMOS transistor and the second PMOS transistor is small, and the output impedance of the amplifier is mainly determined by the impedance of these two transistors, and the output gate-source capacitance of these two transistors is relatively large, while The gate-to-drain capacitance of other transistors on the output node is very small, and the output capacitance is mainly determined by these two transistors, so as to ensure that the bandwidth changes little and remains basically constant.

2. Accurate linear relationship of gain. In the whole receiver system, the variable gain amplifier is in the back stage, so the linearity of the amplifier directly affects the performance of the whole receiver. The variable gain amplifier of the invention realizes the precise linear relationship between the digital control word and the gain. The variable gain amplifier of the present invention changes the corresponding bias current while controlling the width-to-length ratio of the first N-type metal oxide transistor and the fifth N-type metal oxide transistor in the common source amplifier through the switch control word, so that The transconductance of the amplifier input tube has a linear relationship with the control word. At the same time, it is ensured that the overdrive voltage of the input transistor remains unchanged, so that the drain-source voltage of the current source transistor generated by the current mirror remains unchanged, so that the error of the current source is small. Since the output impedance remains basically unchanged, by setting different control word sizes, the size of the gain is linearly related to the control word, and the gain step size is fixed, which improves the gain accuracy and linearity.

Description of drawings

Fig. 1 is a circuit diagram of the present invention;

Fig. 2 is the waveform diagram of the amplitude-frequency characteristic of the present invention;

Fig. 3 is a gain comparison graph between the present invention and the traditional structure.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention Modifications in equivalent forms all fall within the scope defined by the appended claims of this application.

As shown in Figure 1, a gain linear variable gain amplifier with constant bandwidth of the present invention includes a common-source stage amplifier and a gain adjustment network; wherein, the common-source stage amplifier includes a first N-type metal oxide transistor N1, a fifth The N-type metal oxide transistor N5, the first P-type metal oxide transistor P1, the second P-type metal oxide transistor P2 and the first current source I1; the gain adjustment network includes the second N-type metal oxide transistor N2, the third NMOS transistor N3, fourth NMOS transistor N4, sixth NMOS transistor N6, seventh NMOS transistor N7, eighth NMOS transistor N8, second Current source I2, third current source I3, fourth current source I4, fifth current source I5, sixth current source I6, seventh current source I7, eighth current source I8, ninth current source I9, tenth current source I10, first switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, sixth switch S6, seventh switch S7, eighth switch S8, ninth switch S9, tenth switch S10, the eleventh switch S11, the twelfth switch S12, the thirteenth switch S13, the fourteenth switch S14, and the fifteenth switch S15.

The input signal positive terminal VIN+ is connected to the gates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4; The drain of the first N-type metal oxide transistor N1 is connected to the drain of the first P-type metal oxide transistor P1, the drain of the first P-type metal oxide transistor P1 is connected to the gate, and the first P-type metal oxide transistor P1 is connected to the gate. The source of the transistor P1 is connected to the power supply voltage; the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2, the source of the third NMOS transistor N3, and the source of the NMOS transistor N3. The source of the fourth NMOS transistor N4, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7 It is connected to the source of the eighth N-type metal oxide transistor N8, and at the same time connected to one end of the first current source I1, the first switch S1, the second switch S2 and the third switch S3; the other end of the first switch S1 is connected to the first One end of the second current source I2 is connected, the other end of the second switch S2 is connected with one end of the third current source I3, and the other end of the third switch S3 is connected with one end of the fourth current source I4; the first current source I1, the second The other ends of the current source I2, the third current source I3 and the fourth current source I4 are grounded; one end of the fourth switch S4 is connected to the drain of the second N-type metal oxide transistor N2, and one end of the fifth switch S5 is connected to the third The drain of the N-type metal oxide transistor N3 is connected, and one end of the sixth switch S6 is connected to the drain of the fourth N-type metal oxide transistor N4; the other ends of the fourth switch S4, the fifth switch S5 and the sixth switch S6 Connected to the drain of the first N-type metal oxide transistor N1, and connected to one end of the tenth switch S10, the eleventh switch S11, and the twelfth switch S12, as the positive terminal VOUT+ of the amplifier output signal; the tenth switch S10 The other end of the switch S11 is connected to one end of the seventh current source I7, the other end of the eleventh switch S11 is connected to one end of the sixth current source I6, and the other end of the twelfth switch S12 is connected to one end of the fifth current source I5; The other terminals of the fifth current source I5, the sixth current source I6 and the seventh current source I7 are connected to the power supply voltage; the input signal negative terminal VIN- is connected to the fifth N-type metal oxide transistor N5, the sixth N-type metal oxide transistor N6, The gate of the seventh NMOS transistor N7 is connected to the gate of the eighth NMOS transistor N8; the drain of the fifth NMOS transistor N5 is connected to the drain of the second PMOS transistor P2 , the drain of the second P-type metal oxide transistor P2 is connected to the gate, the source of the second P-type metal oxide transistor P2 is connected to the power supply voltage; one end of the seventh switch S7 is connected to the sixth N-type metal oxide transistor N6 The drain of the eighth switch S8 is connected to the drain of the seventh N-type metal oxide transistor N7, and one end of the ninth switch S9 is connected to the drain of the eighth N-type metal oxide transistor N8; The other ends of the seventh switch S7, the eighth switch S8 and the ninth switch S9 are connected to the drain of the fifth N-type metal oxide transistor N5, and are simultaneously connected to the thirteenth switch S13, the fourteenth switch S14 and the fifteenth switch One end of S15 is connected as the negative terminal VOUT- of the amplifier output signal; the other end of the thirteenth switch S13 is connected to one end of the eighth current source I8, and the other end of the fourteenth switch S14 is connected to one end of the ninth current source I9 , the other end of the fifteenth switch S15 is connected to one end of the tenth current source I10; the other ends of the eighth current source I8, the ninth current source I9 and the tenth current source I10 are connected to the power supply voltage.

The gain linear variable gain amplifier with a constant bandwidth is controlled by a switch to control the parallel current source so that the current flowing through the first PMOS transistor P1 and the second PMOS transistor P2 is constant to ensure that its impedance remains constant . The impedance of the first PMOS transistor P1 and the second PMOS transistor P2 is small, the output impedance of the amplifier is mainly determined by the impedance of these two transistors, and the output gate-source capacitance of these two transistors is relatively large, while The gate-to-drain capacitance of other transistors on the output node is very small, and the output capacitance is mainly determined by these two transistors, so as to ensure that the bandwidth changes little and remains basically constant. The gain control network of the present invention changes the corresponding bias current while controlling the width-to-length ratio of the first N-type metal oxide transistor and the fifth N-type metal oxide transistor in the common source amplifier through the switch control word, so that the amplifier The transconductance of the input tube has a linear relationship with the control word. Since the output impedance remains basically unchanged, by setting different control word sizes, the size of the gain is linearly related to the control word, and the step size of the gain is fixed.

The first switch S1, the fourth switch S4, the seventh switch S7, the tenth switch S10 and the thirteenth switch S13 are all controlled by a one-bit control word A1, the second switch S2, the fifth switch S5, the eighth switch S8, the The eleventh switch S11 and the fourteenth switch S14 are controlled by a one-bit control word A2, the third switch S3, the sixth switch S6, the ninth switch S9, the twelfth switch S12 and the fifteenth switch S15 are controlled by a one-bit control word A3 Control, the control word signal A3A2A1 is provided by the digital module in the whole automatic gain control loop. The currents of the first current source I1, the second current source I2, the sixth current source I6 and the ninth current source I9 are equal, the currents of the seventh current source I7 and the eighth current source I8 are equal and equal to half of the current of the first current source I1 , the currents of the third current source I3, the fifth current source I5 and the tenth current source I10 are equal and equal to twice the current of the first current source I1, and the current of the fourth current source I4 is equal to four times of the current of the first current source I1 . The width-to-length ratios of the first N-type metal oxide transistor N1 and the fifth N-type metal-oxide transistor N5 are equal, and the width-to-length ratios of the second N-type metal-oxide transistor N2 and the sixth N-type metal-oxide transistor N6 are equal and Equal to the aspect ratio of the first NMOS transistor N1, the aspect ratios of the third NMOS transistor N3 and the seventh NMOS transistor N7 are equal and equal to the first NMOS transistor N1 Twice the width-to-length ratio, the width-to-length ratio of the fourth NMOS transistor N4 and the eighth NMOS transistor N8 are equal and equal to four times the width-to-length ratio of the first NMOS transistor N1. The low-frequency differential signals are respectively applied to the positive terminal VIN+ and the negative terminal VIN-. When the first to fifteenth switches S1-S15 are all turned off, the small voltage signals pass through the first N-type metal oxide transistor N1 and the fifth N-type transistor N1 respectively. The metal oxide transistor N5 converts the current into a small signal, the first current source I1 provides current bias for the common source amplifier, and the first P-type metal oxide transistor P1 and the second P-type metal oxide transistor P2 are respectively implemented in a diode mode connected, as a load for the differential branch. The drains of the first NMOS transistor N1 and the fifth NMOS transistor N5 serve as the positive output terminal VOUT+ and the negative output terminal VOUT− of the amplifier respectively. When the control word A3A2A1 is 01, that is, the first switch S1, the fourth switch S4, the seventh switch S7, the tenth switch S10 and the thirteenth switch S13 are closed, the current of the second current source I2 is controlled by the seventh current source I7 and The eighth current source I8 divides the current, and the current flowing through the first PMOS transistor P1 and the second PMOS transistor P2 remains unchanged. The impedance of the two transistors is equivalent to the reciprocal of the transconductance, so the impedance does not change. variable and smaller. At the same time, all the current of the seventh current source I7 flows through the second NMOS transistor N2, and all the current of the eighth current source I8 flows through the sixth NMOS transistor N6. The impedance seen from the output end is mainly determined by the equivalent impedance of the first PMOS transistor P1 and the second PMOS transistor P2, that is, the output impedance remains basically unchanged. At the output node, the parasitic capacitance of the first P-type metal oxide transistor P1 and the second P-type metal oxide transistor P2 is mainly the gate-source capacitance and is relatively large, while the other transistors introduced are the gate-drain capacitance and work at The gate-to-drain capacitance of the transistor in the saturation region is very small and almost non-existent, so the equivalent capacitance at the output node is determined by the first PMOS transistor P1 and the second PMOS transistor P2 and remains unchanged, so the bandwidth does not change ,keep constant. The current of the second current source I2 only flows through the second NMOS transistor N2 and the sixth NMOS transistor N6 to provide current bias for them, the first switch S1, the fourth switch S4 and the seventh switch S7 At the same time, it is closed, so that the width-to-length ratio and bias current of the second NMOS transistor N2 change by the same multiples relative to the first NMOS transistor N1, then the transconductance of the second NMOS transistor N2 is the same multiple of the transconductance of the first NMOS transistor N1. At the same time, the aspect ratio and bias current of the sixth NMOS transistor N6 are respectively changed by the same multiples relative to the fifth NMOS transistor N5, so the transconductance of the sixth NMOS transistor N6 is the first Five NMOS transistors of the same multiple of the transconductance of N5. When ensuring that the transconductances of the first NMOS transistor N1 and the fifth NMOS transistor N5 are the same and unchanged, the equivalent input transconductance of the entire common source amplifier depends on the size of the multiple, because the output impedance is different , the amplifier gain depends on the size of the multiple.

When the control word A3A2A1 is 011, that is, the first switch S1, the fourth switch S4, the seventh switch S7, the tenth switch S10 and the thirteenth switch S13 are closed, the second switch S2, the fifth switch S5, the eighth switch The switch S8, the eleventh switch S11 and the fourteenth switch S14 are also closed at the same time, and the transistor gate-drain capacitance introduced at this time has a negative impact on the original first P-type metal oxide transistor P1 and the second P-type metal oxide transistor P2. The influence of the gate-source capacitance is small, and the output capacitance remains unchanged; the current of the third current source I3 is shunted by the sixth current source I6 and the ninth current source I9, ensuring that the first P-type metal oxide transistor P1 and the second P-type metal oxide transistor P1 The current of the oxide transistor P2 does not change, and its corresponding equivalent impedance also does not change. Since the drain-source resistance of other transistors introduced is very large, the output load is mainly determined by the first PMOS transistor P1 and the second PMOS transistor P2, so the output impedance and bandwidth remain unchanged. Under this control word, all the current of the sixth current source I6 flows through the third NMOS transistor N3, and all the current of the ninth current source I9 flows through the seventh NMOS transistor N7. The current of the third current source I3 only flows through the third NMOS transistor N3 and the seventh NMOS transistor N7 to provide current bias for them, the second switch S2, the fifth switch S5 and the eighth switch S8 At the same time, it is closed, so that the width-to-length ratio and bias current of the third NMOS transistor N3 change by the same multiples relative to the first NMOS transistor N1, then the transconductance of the third NMOS transistor N3 is the same multiple of the transconductance of the first NMOS transistor N1. At the same time, the width-to-length ratio and bias current of the seventh NMOS transistor N7 are respectively changed by the same multiples relative to the fifth NMOS transistor N5, and the transconductance of the seventh NMOS transistor N7 is the first Five NMOS transistors of the same multiple of the transconductance of N5. When ensuring that the transconductances of the first NMOS transistor N1 and the fifth NMOS transistor N5 are the same and unchanged, the equivalent input transconductance of the entire common source amplifier depends on the total multiple and magnitude.

When the control word A3A2A1 is 111, that is, all switches are closed at the same time, at this time the gate-source capacitance of the first PMOS transistor P1 and the second PMOS transistor P2 dominates, and the output capacitance basically remains unchanged ; The current of the fourth current source I4 is shunted by the fifth current source I5 and the tenth current source I10 to ensure that the currents of the first P-type metal oxide transistor P1 and the second P-type metal oxide transistor P2 remain unchanged, and their corresponding equivalents The effective impedance is also unchanged. Since the drain-source resistance of other transistors introduced is very large, the output load is mainly determined by the first PMOS transistor P1 and the second PMOS transistor P2, so the output impedance and bandwidth remain unchanged. Under this control word, all the current of the fifth current source I5 flows through the fourth NMOS transistor N4, and all the current of the tenth current source I10 flows through the eighth NMOS transistor N8. The current of the fourth current source I4 only flows through the fourth NMOS transistor N4 and the eighth NMOS transistor N8 to provide current bias for them, the third switch S3, the sixth switch S6 and the ninth switch S9 At the same time, it is closed, so that the width-to-length ratio and bias current of the fourth N-type metal-oxide transistor N4 change by the same multiples relative to the first N-type metal-oxide transistor N1, and the transconductance of the fourth N-type metal-oxide transistor N4 is the same multiple of the transconductance of the first NMOS transistor N1. At the same time, the width-to-length ratio and bias current of the eighth NMOS transistor N8 are respectively changed by the same multiples relative to the fifth NMOS transistor N5, and the transconductance of the eighth NMOS transistor N8 is the first Five NMOS transistors of the same multiple of the transconductance of N5. When ensuring that the transconductances of the first NMOS transistor N1 and the fifth NMOS transistor N5 are the same and unchanged, the input transconductance of the entire common source amplifier depends on the total multiple and magnitude. The change of the control word directly makes the equivalent transconductance of the input tube of the entire amplifier change exponentially. By setting fixed current multiples and input tube size multiples, the gain of the amplifier can be precisely linearly related to the control word, and the gain step size is fixed.

The following illustrates that the present invention has the advantages of constant bandwidth and linear gain through simulation comparison.

Using Virtuoso simulation software to simulate the amplitude-frequency characteristics of the variable gain amplifier. At the same time, this technology is used to compare with the traditional technology of changing the transconductance to achieve variable gain.

The results of amplitude-frequency characteristics are shown in Figure 2. The abscissa indicates the frequency of the input signal in Hz, and the ordinate indicates the gain in dB. It can be seen from Fig. 2 that the bandwidth of the present invention is basically constant around 170MHz. The result of comparing this technology with the traditional technology of changing the transconductance to achieve variable gain is shown in Figure 3. The variable gain amplifier proposed by the present invention has a precise linear gain relationship, and the gain step size is 6dB.

To sum up, in the present invention, the diode-connected transistor is used as the load, so that the switching of the switch has little change in the equivalent impedance and capacitive reactance of the output node, thereby ensuring that the bandwidth remains unchanged. In the present invention, the size of the input tube and the bias current are changed at the same time, so that the overdrive voltage of the input tube remains unchanged, and the source-drain-source voltage of the current mirror generated by the current mirror remains unchanged. Therefore, the linear relationship in dB of the gain is realized in an ordinary digital signal control switch On the basis of further improving the gain accuracy.

Claims (1)

1. the gain linear variable gain amplifier that bandwidth is constant, is characterized in that: this variable gain amplifier comprises common-source stage amplifier and gain-adjusted network; Wherein:

Common-source stage amplifier comprises the first N-type MOS transistor (N1), the 5th N-type MOS transistor (N5), a P type MOS transistor (P1), the 2nd P type MOS transistor (P2) and the first current source (I1);

Gain-adjusted network comprises the second N-type MOS transistor (N2), 3rd N-type MOS transistor (N3), 4th N-type MOS transistor (N4), 6th N-type MOS transistor (N6), 7th N-type MOS transistor (N7), 8th N-type MOS transistor (N8), second current source (I2), 3rd current source (I3), 4th current source (I4), 5th current source (I5), 6th current source (I6), 7th current source (I7), 8th current source (I8), 9th current source (I9), tenth current source (I10), first switch (S1), second switch (S2), 3rd switch (S3), 4th switch (S4), 5th switch (S5), 6th switch (S6), 7th switch (S7), 8th switch (S8), 9th switch (S9), tenth switch (S10), 11 switch (S11), twelvemo closes (S12), 13 switch (S13), 14 switch (S14) and the 15 switch (S15),

Input signal anode (VIN+) is connected with the grid of the first N-type MOS transistor (N1), the second N-type MOS transistor (N2), the 3rd N-type MOS transistor (N3) and the 4th N-type MOS transistor (N4), the drain electrode of the one P type MOS transistor (P1) is connected with grid, and the source electrode of a P type MOS transistor (P1) connects supply voltage, the source electrode of the first N-type MOS transistor (N1) and the source electrode of the second N-type MOS transistor (N2), the source electrode of the 3rd N-type MOS transistor (N3), the source electrode of the 4th N-type MOS transistor (N4), the source electrode of the 5th N-type MOS transistor (N5), the source electrode of the 6th N-type MOS transistor (N6), the source electrode of the 7th N-type MOS transistor (N7) is connected with the source electrode of the 8th N-type MOS transistor (N8) and forms one article of main line, be divided into four branch roads afterwards, respectively with the first current source (I1), first switch (S1), second switch (S2) is connected with one end of the 3rd switch (S3), the other end of the first switch (S1) is connected with one end of the second current source (I2), the other end of second switch (S2) is connected with one end of the 3rd current source (I3), and the other end of the 3rd switch (S3) is connected with one end of the 4th current source (I4), the other end ground connection of the first current source (I1), the second current source (I2), the 3rd current source (I3) and the 4th current source (I4), one end of 4th switch (S4) is connected with the drain electrode of the second N-type MOS transistor (N2), one end of 5th switch (S5) is connected with the drain electrode of the 3rd N-type MOS transistor (N3), and one end of the 6th switch (S6) is connected with the drain electrode of the 4th N-type MOS transistor (N4), the other end of the 4th switch (S4), the 5th switch (S5) and the 6th switch (S6) is connected with the drain electrode of the first N-type MOS transistor (N1) and forms one article of main line, as the anode (VOUT+) of amplifier output signal, and this main line is divided into four branch roads, the one end of closing (S12) respectively with the drain electrode of a P type MOS transistor (P1), the tenth switch (S10), the 11 switch (S11) and twelvemo is connected, the other end of the tenth switch (S10) is connected with one end of the 7th current source (I7), the other end of the 11 switch (S11) is connected with one end of the 6th current source (I6), and the other end that twelvemo closes (S12) is connected with one end of the 5th current source (I5), another termination supply voltage of 5th current source (I5), the 6th current source (I6) and the 7th current source (I7), input signal negative terminal (VIN-) is connected with the grid of the 5th N-type MOS transistor (N5), the 6th N-type MOS transistor (N6), the 7th N-type MOS transistor (N7) and the 8th N-type MOS transistor (N8), the drain electrode of the 2nd P type MOS transistor (P2) is connected with grid, and the source electrode of the 2nd P type MOS transistor (P2) connects supply voltage, one end of 7th switch (S7) is connected with the drain electrode of the 6th N-type MOS transistor (N6), one end of 8th switch (S8) is connected with the drain electrode of the 7th N-type MOS transistor (N7), and one end of the 9th switch (S9) is connected with the drain electrode of the 8th N-type MOS transistor (N8), the other end of the 7th switch (S7), the 8th switch (S8) and the 9th switch (S9) is connected with the drain electrode of the 5th N-type MOS transistor (N5) and forms one article of main line, as the negative terminal (VOUT-) of amplifier output signal, and this main line is divided into four branch roads, be connected with one end of the drain electrode of the 2nd P type MOS transistor (P2), the 13 switch (S13), the 14 switch (S14) and the 15 switch (S15) respectively, the other end of the 13 switch (S13) is connected with one end of the 8th current source (I8), the other end of the 14 switch (S14) is connected with one end of the 9th current source (I9), and the other end of the 15 switch (S15) is connected with one end of the tenth current source (I10), another termination supply voltage of 8th current source (I8), the 9th current source (I9) and the tenth current source (I10).