CN101951236A

CN101951236A - Digital variable gain amplifier

Info

Publication number: CN101951236A
Application number: CN201010289321XA
Authority: CN
Inventors: 吴建辉; 胡超; 陈超; 吉新村; 徐震; 竺磊; 徐毅; 杨世铎; 孙杰
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2010-09-20
Filing date: 2010-09-20
Publication date: 2011-01-19
Anticipated expiration: 2030-09-20
Also published as: CN101951236B

Abstract

The invention discloses a digital variable gain amplifier, which utilizes a differential input end switch of an MOS (Metal Oxide Semiconductor) transistor and an MOS transistor diode positive/negative feedback switch to control the network and change equivalent input transconductance and the scale amplification factor of a current mirror so as to realize the function of digital variable gain amplification. The digital variable gain amplifier mainly comprises three parts of a differential input stage transconductance control network, a diode positive/negative feedback control network of the MOS transistor and an output load stage. The invention has the characteristics of stable direct current working point, less chip area, high gain control precision, large and relatively stable broadband, flexible gain control mode, novel thinking, simple circuit structure and the like corresponding to the traditional digital variable gain amplifier.

Description

A kind of digital variable gain amplifier

Technical field

The present invention relates to a kind of digital variable gain amplifier.

Background technology

Variable gain amplifier is as the key modules of radio-frequency transmitter, and the research of its designing technique is the research focus of radio frequency and analog integrated circuit always.Variable gain amplifier need be traded off between performances such as gain control range, gain controlling precision, bandwidth, the linearity, area, power consumption.For under unlike signal power, the settling time that automatic gain control loop (AGC) has identical transient response and accurately defines, the variation that variable gain amplifier all must satisfy the relative control signal of gain is the dB linear change.Variable gain amplifier mainly is divided into analogue variable gain amplifier (VGA) and digital variable gain amplifier (PGA).And the digital control approach of digital variable gain amplifier is easy to realize, gain controlling precision height, and structure is comparatively simple, so become main flow gradually.

Digital control gain amplifier mainly is divided into two big class, i.e. closed-loop structure and open loop structures: closed-loop structure mainly is by digital switch Control and Feedback network, changes feedback factor and realizes gain digital control; The main active degeneration structure of open loop structure, diode load structure, several forms of cascade difference equity.

General closed-loop structure is formed by operational amplifier and feedback network, and operational amplifier can be that the voltage-type operational amplifier also can be the current mode operational amplifier, and feedback network can be that resistance-feedback network also can be the switching capacity feedback network.Change the electric resistance array or the capacitor array of feedback network by digital switch, thereby realize that gain linearity dB changes.The gain of closed-loop structure is by the ratio decision of resistance or electric capacity, and the precision of proportion resistor, electric capacity is higher on the technology, so closed-loop structure has gain controlling precision height, linearity advantages of higher.But adopt the digital variable gain amplifier of closed-loop structure also to bring a lot of problems: at first area is bigger to adopt voltage operational amplifier; Based on the voltage-type operational amplifier, behind the change feedback network, the variation of feedback factor can cause the variation of bandwidth, i.e. gain is big more, and bandwidth is more little; Adopt the current mode operational amplifier, though can guarantee bandwidth substantially not with change in gain, power consumed is excessive; In addition, adopt resistance-feedback network, the chip interview is very big, and noiseproof feature also can worsen simultaneously; Adopt the switching capacity feedback network, complex structure, chip area is big, and needs to cause certain degree of difficulty by Discrete Time Analysis.

The source degeneration structure that open loop structure adopts, promptly differential input stage adds source degeneration resistance, and mutual conductance is approximate linear with source degeneration resistance, and output load stage also is that resistance is formed; In order to guarantee the stable of output common mode voltage,, realize that gain digital is variable generally by digital switch change source degeneration resistor network.Though this mode is simple in structure, area is less, and the linearity is not high, and during change source degeneration resistor network, the linearity and noise all can be affected.

For the linearity of increase source degeneration open loop structure, effective method is exactly by a LOCAL FEEDBACK, improves the input mutual conductance of equivalence, though at this moment the linearity has improved, and big, power consumption increase that the problem of bringing is that chip area becomes.The diode load structure is made up of differential input stage and diode load level, gains to be the product of difference input mutual conductance and output diode load.The influence that is not subjected to process corner in order to guarantee to gain (influence that not changed by electron mobility and hole mobility), the type of loading-diode metal-oxide-semiconductor need equate with the type of differential input stage metal-oxide-semiconductor, at this moment needs current mirror to realize.By the modes such as ratio amplification factor of digital switch Control current source or current mirror, change the mutual conductance of differential input stage or the mutual conductance of loading-diode, thereby realize the dB linear change of gain.This mode is simple in structure, and area is less, and the gain controlling precision is higher, but the change of ride gain can cause the variation of direct current quiescent point, and brings the excessive problem of power consumption.The cascade structure for amplifying by differential input stage, is total to the grid amplifying stage, form with load resistance, by changing the common grid switching network of common grid amplifying stage, thereby change the ratio of the small signal variation current delivery of input stage, thereby realize the gain linearity variation to output load stage.This structural circuit bandwidth is bigger, and structure is comparatively simple, and noise is less, and chip area is less, and changes the common grid switching network of grid amplifying stage altogether, and the dc point of entire circuit is not had any impact.But because the product that this circuit structure gain is difference input mutual conductance and output resistance, and difference input mutual conductance is subjected to factor such as technology easily and change, resistance also is subjected to technique change easily and changes simultaneously, so the gain controlling precision is not high, the linearity is also lower.

Summary of the invention

Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides a kind ofly have that dc point is stable, chip area is few, gain controlling precision height, high and constant relatively, the circuit structure simple numerical variable gain amplifier in broadband.

Technical scheme: for achieving the above object, the technical solution used in the present invention is:

A kind of digital variable gain amplifier (programmable gain amplifier), utilize MOS transistor differential input end switch Control Network and MOS transistor diode just/negative feedback switch Control Network, change the ratio amplification factor of equivalence input mutual conductance and current mirror, thereby realize digital variable gain enlarging function, this digital variable gain amplifier comprises differential input stage mutual conductance Control Network, the MOS transistor diode just/the negative feedback Control Network, output load stage three parts:

Described differential input stage mutual conductance Control Network comprises bias current sources Iref, the PMOS transistor that diode connects and as the 2nd PMOS transistor of tail current source, and six PMOS transistors of differential input stage, i.e. the 3rd PMOS transistor, the 4th PMOS transistor, the 5th PMOS transistor, the 6th PMOS transistor, the 7th PMOS transistor and the 8th PMOS transistor;

Described MOS transistor diode just/the negative feedback Control Network comprises that diode connects first nmos pass transistor and second nmos pass transistor of load, also comprises the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the 6th nmos pass transistor simultaneously;

Described output load stage comprises the 7th nmos pass transistor and the 8th nmos pass transistor of two common source NMOS, two the 9th nmos pass transistor, the tenth nmos pass transistors that are total to grid NMOS, the 9th PMOS transistor and the tenth PMOS transistor of the PMOS of two diode connections.

Described differential input stage mutual conductance Control Network has become the main body circuit part of digital variable gain amplifier with MOS transistor diode positive-negative feedback Control Network mechanism.Wherein a bias current sources Iref and a PMOS transistor produce bias voltage and give the transistorized grid of the 2nd PMOS; The 2nd PMOS transistor is as tail current source, the bias current of differential input stage is provided, bias current sources Iref connects a PMOS transistor drain and a grid, the one PMOS transistor is connected with the transistorized grid of the 2nd PMOS, and a PMOS transistor and the transistorized source electrode of the 2nd PMOS connect power supply; The 3rd PMOS transistor, the 5th PMOS transistor and the transistorized grid of the 7th PMOS connect the positive level of input signal, the source electrode of these three PMOS pipes is connected together, and link to each other with the 2nd PMOS transistor drain as tail current, their substrate all links to each other with separately source electrode; The 4th PMOS transistor, the 6th PMOS transistor and the transistorized grid of the 8th PMOS connect the negative level of input signal, the source electrode of these three PMOS pipes is connected together, and link to each other with the 2nd PMOS transistor drain as tail current, their substrate all links to each other with separately source electrode; The grid of first nmos pass transistor links to each other with drain electrode, form the diode connected mode, its source ground, drain electrode links to each other with the 3rd PMOS transistor drain, drain electrode simultaneously links to each other with the 5th PMOS transistor drain by MOS switch a2+, links to each other with the 6th PMOS transistor drain by MOS switch a2-; The grid of second nmos pass transistor links to each other with drain electrode, form the diode connected mode, source ground, drain electrode links to each other with the 4th PMOS transistor drain, drain electrode simultaneously links to each other with the 6th PMOS transistor drain by MOS switch a2+, links to each other with the 5th PMOS transistor drain by MOS switch a2-; The grid of the 3rd nmos pass transistor links to each other with the grid of first nmos pass transistor, and its drain electrode links to each other with the grid of first nmos pass transistor by a MOS switch a1+, and its drain electrode links to each other with the grid of second nmos pass transistor by another one switch a1-; The grid of the 4th nmos pass transistor links to each other with the grid of second nmos pass transistor, and its drain electrode links to each other with the grid of second nmos pass transistor by a MOS switch a1+, and its drain electrode links to each other with the grid of first nmos pass transistor by another one switch a1-; The source ground of the 5th nmos pass transistor, grid links to each other with the drain electrode of oneself by a MOS switch a3, and its grid links to each other with the 7th PMOS transistor drain by another one MOS switch a3; The source ground of the 6th nmos pass transistor, grid links to each other with the drain electrode of oneself by a MOS switch a3, and its grid links to each other with the 8th PMOS transistor drain by another one MOS switch a3; The grid of the 7th nmos pass transistor links to each other with the grid of first nmos pass transistor, and its drain electrode links to each other with the source electrode of the 9th nmos pass transistor; The grid of the 8th nmos pass transistor links to each other with the grid of second nmos pass transistor, and its drain electrode links to each other with the source electrode of the tenth nmos pass transistor; The grid of the 9th nmos pass transistor connects fixing bias voltage, and its drain electrode links to each other with the transistorized grid of the 9th PMOS as the output stage anode; The grid of the tenth nmos pass transistor connects fixing bias voltage, and its drain electrode links to each other with the transistorized grid of the tenth PMOS as the output stage negative terminal; The transistorized grid of the 9th PMOS links to each other with its drain electrode, forms diode load and connects; The transistorized grid of the tenth PMOS links to each other with its drain electrode, forms diode load and connects; 12 MOS switches all are made of metal-oxide-semiconductor.

Equivalent transconductance by MOS switch control differential input stage; Control the Push And Release of MOS switch by opposite digital signal, the grid formation negative feedback diode connection of oneself is received in the drain electrode of promptly controlling the 4th nmos pass transistor, and the drain electrode of still drain electrode of the 4th nmos pass transistor being received first nmos pass transistor forms the positive feedback diode and connects; Amplify as fully differential simultaneously, keep symmetry, opposite digital signal is controlled the Push And Release of MOS switch, the grid formation negative feedback diode connection of oneself is received in the drain electrode of promptly controlling the 3rd nmos pass transistor, and the drain electrode of still drain electrode of the 3rd nmos pass transistor being received second nmos pass transistor forms the positive feedback diode and connects.

The grid of the 7th nmos pass transistor links to each other with the grid of first nmos pass transistor, and the grid of the 8th nmos pass transistor links to each other with the grid of second nmos pass transistor; The grid of the 9th nmos pass transistor connects fixing bias voltage, forms cascodes with the 7th nmos pass transistor; The grid of the tenth nmos pass transistor connects fixing bias voltage and the 8th nmos pass transistor is formed cascodes; The transistorized grid of the 9th PMOS links to each other with drain electrode, and source electrode connects power supply, forms the output loading that diode connects, and its grid, drains as the anode of differential output signal; The transistorized grid of the tenth PMOS links to each other with drain electrode, and source electrode connects power supply, forms the output loading that diode connects, and its grid, drains as the negative terminal of differential output signal.Shunt when guaranteeing that gain is switched by digital MOS switch and the 7th PMOS transistor, the 8th PMOS transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, dc point stable promptly stablized output common mode voltage.

Beneficial effect: a kind of numerical value variable gain amplifier provided by the invention, thinking novelty, simple in structure, adopt the selection of digital MOS switch control NMOS diode feedback polarity, change current mirror ratio amplification factor, thereby realize that has a digital variable gain enlarging function.This structure is effectively utilized MOS transistor, and circuit area significantly reduces, gain controlling precision height, and bandwidth is big and comparatively constant.

Description of drawings

Fig. 1 is a digital variable gain amplifier main body electrical block diagram of the present invention;

Fig. 2 is a differential input end switch control transconductance circuit structural representation of the present invention;

Fig. 3 is a MOS positive-negative feedback diode connecting circuit structural representation of the present invention;

Fig. 4 is conventional digital switch control gain-changeable amplifier circuit structural representation;

Fig. 5 is a digital variable gain amplifier frequency characteristic analogous diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing the present invention is done further explanation.

As Fig. 1, Fig. 2 and shown in Figure 3, structural representation for a kind of digital variable gain amplifier, it utilizes MOS transistor differential input end switch Control Network and MOS transistor diode positive-negative feedback switch Control Network, change the ratio amplification factor of equivalence input mutual conductance and current mirror, thereby realize digital variable gain enlarging function, this digital variable gain amplifier mainly comprises differential input stage mutual conductance Control Network, the MOS transistor diode just/the negative feedback Control Network, output load stage three parts:

Described differential input stage mutual conductance Control Network comprises bias current sources Iref, the PMOS transistor MP1 that diode connects and as the 2nd PMOS transistor MP2 of tail current source, and six PMOS transistors of differential input stage, i.e. the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the 5th PMOS transistor MP5, the 6th PMOS transistor MP6, the 7th PMOS transistor MP7 and the 8th PMOS transistor MP8;

Described MOS transistor diode just/the negative feedback Control Network comprises the first nmos pass transistor MN1 and the second nmos pass transistor MN2 that connects load, also comprises the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4, the 5th nmos pass transistor MN5 and the 6th nmos pass transistor MN6 simultaneously;

Described output load stage comprises the 7th nmos pass transistor MN7 and the 8th nmos pass transistor MN8 of two common source NMOS, two the 9th nmos pass transistor MN9, the tenth nmos pass transistor MN10 that are total to grid NMOS, the 9th PMOS transistor MP9 and the tenth PMOS transistor MP10 of the PMOS of two diode connections.

Differential input stage mutual conductance Control Network, MOS transistor diode positive-negative feedback Control Network mechanism has become the main body circuit part of digital variable gain amplifier.Wherein a bias current sources Iref and a PMOS transistor MP1 produce the grid that bias voltage is given the 2nd PMOS transistor MP2; The 2nd PMOS transistor MP2 provides the bias current of differential input stage as tail current source, and its source electrode meets power vd D; The grid of the 3rd PMOS transistor MP3, the 5th PMOS transistor MP5 and the 7th PMOS transistor MP7 meets the positive level Vin+ of input signal, the source electrode of these three PMOS pipes is connected together, and link to each other with drain electrode as the 2nd PMOS transistor PM2 of tail current source, their substrate all links to each other with source electrode; The grid of the 4th PMOS transistor MP4, the 6th PMOS transistor MP6 and the 8th PMOS transistor MP8 meets the negative level Vin-of input signal, the source electrode of these three PMOS pipes is connected together, and link to each other with drain electrode as the 2nd PMOS transistor MP2 of tail current source, their substrate all links to each other with source electrode; The grid of the first nmos pass transistor MN1 links to each other with drain electrode, form the diode connected mode, source ground GND, drain electrode links to each other with the drain electrode of the 3rd PMOS transistor MP3, drain electrode simultaneously links to each other with the drain electrode of the 5th PMOS transistor MP5 by MOS switch a2+, links to each other with the drain electrode of the 6th PMOS transistor MP6 by MOS switch a2-; The grid of the second nmos pass transistor MN2 links to each other with drain electrode, form the diode connected mode, source ground GND, drain electrode links to each other with the drain electrode of the 4th PMOS transistor MP4, drain electrode simultaneously links to each other with the drain electrode of the 6th PMOS transistor MP6 by MOS switch a2+, links to each other with the drain electrode of the 5th PMOS transistor MP5 by MOS switch a2-; The grid of the 3rd nmos pass transistor MN3 links to each other with the grid of the first nmos pass transistor MN1, its drain electrode links to each other with the grid of the first nmos pass transistor MN1 by a MOS switch a1+, and its drain electrode links to each other with the grid of the second nmos pass transistor MN2 by another one switch a1-; The grid of the 4th nmos pass transistor MN4 links to each other with the grid of the second nmos pass transistor MN2, its drain electrode links to each other with the grid of the second nmos pass transistor MN2 by a MOS switch a1+, and its drain electrode links to each other with the grid of the first nmos pass transistor MN1 by another one switch a1-; The source ground of the 5th nmos pass transistor MN5, grid links to each other with the drain electrode of oneself by a MOS switch a3, and its grid links to each other with the drain electrode of the 7th PMOS transistor MP7 by another one MOS switch a3; The source ground of the 6th nmos pass transistor MN6, grid links to each other with the drain electrode of oneself by a MOS switch a3, and its grid links to each other with the drain electrode of the 8th PMOS transistor MP8 by another one MOS switch a3; The grid of the 7th nmos pass transistor MN7 links to each other with the grid of the first nmos pass transistor MN1, and its drain electrode links to each other with the source electrode of the 9th nmos pass transistor MN9; The grid of the 8th nmos pass transistor MN8 links to each other with the grid of the second nmos pass transistor MN2, and its drain electrode links to each other with the source electrode of the tenth nmos pass transistor MN10; The grid of the 9th nmos pass transistor MN9 meets fixing bias voltage Vb, and it drains as output stage anode Vout+, and links to each other with the grid of the 9th PMOS transistor MP9; The grid of the tenth nmos pass transistor MN10 meets fixing bias voltage Vb, and it drains as output stage negative terminal Vout-, and links to each other with the grid of the tenth PMOS transistor MP10; The grid of the 9th PMOS transistor MP9 links to each other with its drain electrode, forms diode load and connects; The grid of the tenth PMOS transistor MP10 links to each other with its drain electrode, forms diode load and connects; 12 MOS switches are made of metal-oxide-semiconductor, control the Push And Release of MOS switch by the selection of MOS switch gate voltage.

Equivalent transconductance by MOS switch control differential input stage; By opposite digital signal a1+, a1-controls the Push And Release of MOS switch, the grid formation negative feedback diode connection of oneself is received in the drain electrode of promptly controlling the 4th nmos pass transistor MN4, and the drain electrode of still drain electrode of the 4th nmos pass transistor MN4 being received the first nmos pass transistor MN1 forms the positive feedback diode and connects; Amplify as fully differential simultaneously, keep symmetry, opposite digital signal a1+, a1-controls the Push And Release of MOS switch, the grid formation negative feedback diode connection of oneself is received in the drain electrode of promptly controlling the 3rd nmos pass transistor MN3, and the drain electrode of still drain electrode of the 3rd nmos pass transistor MN3 being received the second nmos pass transistor MN2 forms the positive feedback diode and connects.

The grid of the 7th nmos pass transistor MN7 links to each other with the grid of the first nmos pass transistor MN1, and the grid of the 8th nmos pass transistor MN8 links to each other with the grid of the second nmos pass transistor MN2; The grid of the 9th nmos pass transistor MN9 meets fixing bias voltage Vb, forms cascodes with the 7th nmos pass transistor MN7; The grid of the tenth nmos pass transistor MN10 meets fixing bias voltage Vb and the 8th nmos pass transistor MN6 forms cascodes; The grid of the 9th PMOS transistor MP9 links to each other with drain electrode, and source electrode meets power vd D, forms the output loading that diode connects, and its grid, drains as the anode of differential output signal; The grid of the tenth PMOS transistor MP10 links to each other with drain electrode, and source electrode meets power vd D, forms the output loading that diode connects, and its grid, drains as the negative terminal of differential output signal.Shunt when guaranteeing that gain is switched by digital MOS switch and the 7th PMOS transistor MP7, the 8th PMOS transistor MP8, the 5th nmos pass transistor MN5, the 6th nmos pass transistor MN6, dc point stable promptly stablized output common mode voltage.

The gain controlling principle of traditional digital variable gain amplifier is very directly perceived, as shown in Figure 4, directly control the voltage of a1, a2 by switch, receive when a1 voltage on the grid voltage Vb of the 9th nmos pass transistor MN9, the tenth nmos pass transistor MN10, and during a2 voltage ground connection, the ratio amplification factor of NMOS current mirror just increases, and difference input small-signal current stream becomes big by the ratio that mirror current source flows to output load stage, and the gain of whole amplifier becomes big like this.When a1 voltage ground connection, and a2 voltage is received on the 9th nmos pass transistor MN9, the tenth nmos pass transistor MN10 grid voltage vb, and at this moment the ratio amplification factor of NMOS current mirror diminishes, and the gain of whole amplifier diminishes.This method is simple in structure, and the gain controlling mode is simple, and output common mode voltage is stable.But also bring a series of problem, at first nmos pass transistor the 9th nmos pass transistor MN9, the tenth nmos pass transistor MN10, the 11 nmos pass transistor MN11, the tenth bi-NMOS transistor MN12, the 13 nmos pass transistor MN13, the 14 nmos pass transistor MN14 directly link to each other with output stage, at this moment there is a large amount of parasitic capacitances, thereby makes the bandwidth of amplifier diminish.The gain control range of this structure is less in addition, if increase gain control range, needs by increasing more current lens array, and at this moment power consumption is too high, and it is big that chip area becomes, and further worsens with Time Bandwidth.

In order to address these problems, can to adopt differential input stage mutual conductance Control Network shown in Figure 2 and adopt MOS transistor diode positive-negative feedback Control Network shown in Figure 3.Among Fig. 2, by MOS switch and opposite digital controlled signal a2+, the drain electrode connected mode that a2-controls differential input stage, it can be the negative feedback connected mode, make equivalence input mutual conductance increase, it also can be the positive feedback connected mode, make equivalence input mutual conductance reduce, by when not needing increase or reduce equivalence input mutual conductance, need shunt by one group of difference input PMOS, thereby guarantee under the various gain control mode, the overdrive voltage of difference input equates, and is stable by the output stage dc point.Among Fig. 3, controlling NMOS diode connected mode by MOS switch and opposite digital controlled signal a1+, a1-is that positive feedback connects or negative feedback connects.The positive feedback connected mode can make current mirror ratio amplification factor become big, and the negative feedback connected mode can make current mirror ratio amplification factor diminish.Overall circuit is seen shown in Figure 1, by the control of digital signal to differential input stage mutual conductance Control Network, MOS transistor diode positive-negative feedback Control Network, can realize gain controlling in a big way, the common gate transistor MN9 of output stage, when MN10 increases the output impedance of current mirror, and the effect of getting up to isolate.When gain was switched, the parasitic capacitance of output stage did not change, so variation is less relatively for three dB bandwidth.The dc point of entire circuit was stable when the 7th PMOS transistor MP7, the 8th PMOS transistor MP8, the 5th nmos pass transistor MN5, the 6th nmos pass transistor MN6 and switch guaranteed the gain switching in addition.The PMOS mutual conductance of the utmost point is only imported in the gain of whole amplifier with difference, the proportional current mirror amplification factor of PMOS mutual conductance that output diode connects and digital switch control is relevant.By in order further to improve gain control range, can increase differential input stage mutual conductance Control Network and MOS transistor diode just/the negative feedback Control Network.As long as guarantee that greater than positive feedback, just can there be the loop stability problem in negative feedback.Fig. 5 is given in the simulation result under the CMOS process conditions, as can be seen gain controlling precision and higher three dB bandwidth preferably.

The above only is a preferred implementation of the present invention; be noted that for those skilled in the art; under the prerequisite that does not break away from the principle of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. A digital variable gain amplifier, characterized in that: said amplifier comprises differential input stage transconductance control network, MOS transistor diode positive/negative feedback control network and output load stage three parts:

The differential input stage transconductance control network includes a bias current source Iref, a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), sixth PMOS transistor (MP6), seventh PMOS transistor (MP7) and eighth PMOS transistor (MP8);

The MOS transistor diode positive/negative feedback control network includes a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), and a fifth NMOS transistor (MN5) and a sixth NMOS transistor (MN6);

The output load stage includes a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), a ninth PMOS transistor (MP9), a tenth PMOS transistor (MP10);

In the differential input stage transconductance control network, the bias current source Iref is connected to the drain and gate of the first PMOS transistor (MP1), and the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are in phase Connection, the source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is connected to the power supply (VDD); the third PMOS transistor (MP3), the fifth PMOS transistor (MP5) and the seventh PMOS transistor (MP7) The gate is connected to the positive stage (Vin+) of the input signal, the sources of these three PMOS transistors are connected together, and connected to the drain of the second PMOS transistor (MP2), and their substrates are connected to their respective sources; The gates of the fourth PMOS transistor (MP4), the sixth PMOS transistor (MP6) and the eighth PMOS transistor (MP8) are connected to the negative stage (Vin-) of the input signal, the sources of these three PMOS transistors are connected together, and It is connected to the drain of the second PMOS transistor (MP2), and their substrates are connected to their respective sources; the gate of the first NMOS transistor (MN1) is connected to the drain to form a diode connection, and its source is grounded ( GND), the drain is connected to the drain of the third PMOS transistor (MP3), while the drain is connected to the drain of the fifth PMOS transistor (MP5) through the MOS switch a2+, and connected to the sixth PMOS transistor (MP6) through the MOS switch a2- ) is connected to the drain; the gate of the second NMOS transistor (MN2) is connected to the drain to form a diode connection, the source is grounded (GND), the drain is connected to the drain of the fourth PMOS transistor (MP4), and the drain The pole is connected to the drain of the sixth PMOS transistor (MP6) through the MOS switch a2+, and connected to the drain of the fifth PMOS transistor (MP5) through the MOS switch a2-; the gate of the third NMOS transistor (MN3) is connected to the drain of the first NMOS transistor (MN3) The gate of the transistor (MN1) is connected, its drain is connected to the gate of the first NMOS transistor (MN1) through a MOS switch a1+, and its drain is connected to the gate of the second NMOS transistor (MN2) through another switch a1- connected; the gate of the fourth NMOS transistor (MN4) is connected to the gate of the second NMOS transistor (MN2), and its drain is connected to the gate of the second NMOS transistor (MN2) through a MOS switch a1+, and its drain is connected to the gate of the second NMOS transistor (MN2) through Another switch a1- is connected to the gate of the first NMOS transistor (MN1); the source of the fifth NMOS transistor (MN5) is grounded, the gate is connected to its own drain through a MOS switch a3, and its gate is connected to another MOS switch a3 is connected to the drain of the seventh PMOS transistor (MP7); the source of the sixth NMOS transistor (MN6) is grounded, the gate is connected to its own drain through a MOS switch a3, and its gate is connected to another MOS switch a3 is connected to the drain of the eighth PMOS transistor (MP8); the seventh NMO The gate of the S transistor (MN7) is connected to the gate of the first NMOS transistor (MN1), and its drain is connected to the source of the ninth NMOS transistor (MN9); the gate of the eighth NMOS transistor (MN8) is connected to the second The gate of the NMOS transistor (MN2) is connected, and its drain is connected to the source of the tenth NMOS transistor (MN10); the gate of the ninth NMOS transistor (MN9) is connected to a fixed bias voltage (Vb), and its drain serves as The positive end of the output stage (Vout+) is connected to the gate of the ninth PMOS transistor (MP9); the gate of the tenth NMOS transistor (MN10) is connected to a fixed bias voltage (Vb), and its drain is used as the negative end of the output stage (Vout -) is connected to the gate of the tenth PMOS transistor (MP10); the gate of the ninth PMOS transistor (MP9) is connected to its drain to form a diode load connection; the gate of the tenth PMOS transistor (MP10) is connected to its drain, A diode load connection is formed; all twelve MOS switches are composed of MOS tubes.

2. A kind of digital variable gain amplifier according to claim 1, characterized in that: the gate of the seventh NMOS transistor (MN7) is connected with the gate of the first NMOS transistor (MN1), and the gate of the eighth NMOS transistor (MN8 ) is connected to the gate of the second NMOS transistor (MN2); the gate of the ninth NMOS transistor (MN9) is connected to a fixed bias voltage (Vb), forming a cascode with the seventh NMOS transistor (MN7) structure; the gate of the tenth NMOS transistor (MN10) is connected to a fixed bias voltage (Vb) to form a cascode structure with the eighth NMOS transistor (MN6); the gate of the ninth PMOS transistor (MP9) is connected to the drain , the source is connected to the power supply (VDD), forming a diode-connected output load, and its gate and drain are used as the positive terminal of the differential output signal; the gate of the tenth PMOS transistor (MP10) is connected to the drain, and the source is connected to the power supply ( VDD), forming a diode-connected output load, whose gate and drain are used as the negative terminals of the differential output signal.