CN102683322B - POP encapsulating structure and manufacture method thereof - Google Patents
POP encapsulating structure and manufacture method thereof Download PDFInfo
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- CN102683322B CN102683322B CN201110059126.2A CN201110059126A CN102683322B CN 102683322 B CN102683322 B CN 102683322B CN 201110059126 A CN201110059126 A CN 201110059126A CN 102683322 B CN102683322 B CN 102683322B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- Pressure Welding/Diffusion-Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The present invention relates to a kind of POP encapsulating structure, including upper strata encapsulating structure and lower floor's encapsulating structure, the soldered ball of wherein said upper strata encapsulating structure is by being welded to connect in the upper surface of described lower floor encapsulating structure, but also include the articulamentum being arranged between described upper strata encapsulating structure and described lower floor encapsulating structure, and this articulamentum includes: form, with the lower surface of described upper strata encapsulating structure, the solder layer being connected；It is arranged at the metal level on the downside of described solder layer；Being arranged at the adhesive linkage on the downside of described metal level, this adhesive linkage is formed with lower floor encapsulating structure and is connected.In accordance with the invention it is possible to the stress distribution improved between upper and lower two encapsulating structures, thus improve in conjunction with reliability.
Description
Technical field
The present invention relates to field of semiconductor package, particularly relate to POP encapsulating structure and manufacture method thereof.
Background technology
In logic circuit and memory area, POP encapsulation (stacked package, package-on-package) is already known to the first-selection of industry, is mainly used in the advanced mobile communication platform manufacturing high-end portable formula equipment and smart mobile phone use.Owing to POP encapsulation can support that portable set is to complexity and functional demand, because of the electromotor referred to herein as this field.Some application processors or base band/application memory combine such core component, tend to POP at present and encapsulate solution.
Fig. 1 is the schematic diagram of existing POP encapsulating structure.As shown in Figure 1, in the structure of existing POP encapsulation, upper strata encapsulating structure 10 is arranged at the upper surface of lower floor's encapsulating structure 20 by its soldered ball 11.Wherein said soldered ball 11 and the pad 21 formation electrical connection of described lower floor encapsulating structure 20 upper surface, thus perform the function of complexity.
But, in existing POP encapsulating structure as above, owing to upper strata encapsulating structure 10 is only formed by spherical soldered ball 11 with the connection of lower floor's encapsulating structure 20, therefore stress concentrates the corner parts acting on soldered ball 11 with the junction of lower floor's encapsulating structure, cause that soldered ball 11 tilts, thus the electrical connection of upper strata encapsulating structure 10 and lower floor's encapsulating structure 20 disconnects, semiconductor element cannot be properly functioning.
Summary of the invention
The present invention proposes to solve the problems referred to above, its object is to provide a kind of POP encapsulating structure and manufacture method thereof, described POP encapsulating structure can effectively disperse upper strata encapsulating structure and lower floor's encapsulating structure in conjunction with stress so that adopting the operation of the semiconductor element of this packaged type more stable.
According to an aspect of the present invention, a kind of POP encapsulating structure is provided, including upper strata encapsulating structure and lower floor's encapsulating structure, the soldered ball of wherein said upper strata encapsulating structure is by being welded to connect in the upper surface of described lower floor encapsulating structure, and, also include the articulamentum being arranged between described upper strata encapsulating structure and described lower floor encapsulating structure, and this articulamentum includes: form, with the lower surface of described upper strata encapsulating structure, the solder layer being connected；It is arranged at the metal level on the downside of described solder layer；Being arranged at the adhesive linkage on the downside of described metal level, this adhesive linkage is formed with lower floor encapsulating structure and is connected.
Wherein, the lower surface of described upper strata encapsulating structure is provided with the copper area of coverage, is connected to be formed with described solder layer.
Wherein, the upper surface of described upper strata encapsulating structure is provided with adhesion zone, is connected to be formed with described adhesive linkage.
Preferably, described metal level is layers of copper, with improve articulamentum stability while improve the heat dispersion of described POP encapsulating structure.
Preferably, described adhesive linkage is formed by heat-conducting glue, to improve the heat dispersion of described POP encapsulating structure.
According to a further aspect in the invention, it is provided that the manufacture method of a kind of POP encapsulating structure, comprise the following steps: make upper strata encapsulating structure and lower floor's encapsulating structure；Articulamentum is arranged at the upper surface of described lower floor encapsulating structure；By the soldered ball of described articulamentum and upper strata encapsulating structure, being arranged at by upper strata encapsulating structure above described lower floor encapsulating structure, wherein, described articulamentum includes: form, with the lower surface of described upper strata encapsulating structure, the solder layer being connected；It is arranged at the metal level on the downside of described solder layer；Being arranged at the adhesive linkage on the downside of described metal level, this adhesive linkage is formed with lower floor encapsulating structure and is connected.
Wherein, in the step of described making upper strata encapsulating structure and lower floor's encapsulating structure, the upper surface being additionally included in described lower floor encapsulating structure arranges the step of adhesion zone.
Wherein, in the step of described making upper strata encapsulating structure and lower floor's encapsulating structure, the bottom surface being additionally included in described upper strata encapsulating structure arranges the step of the copper area of coverage.
Preferably, described metal level is layers of copper, with improve articulamentum stability while improve the heat dispersion of described POP encapsulating structure.
Preferably, described adhesive linkage is formed by heat-conducting glue, to improve the heat dispersion of described POP encapsulating structure.
According to POP encapsulating structure provided by the invention and manufacture method thereof, it is possible to effectively dispersion upper strata encapsulating structure and lower floor's encapsulating structure between in conjunction with stress.Further, by being arranged at the articulamentum between upper strata encapsulating structure and lower floor's encapsulating structure, it is possible to improve the heat dispersion of POP encapsulating structure further.
Accompanying drawing explanation
By the description carried out below in conjunction with the accompanying drawing being exemplarily illustrated an example, the above and other purpose of the present invention and feature will become apparent, wherein:
The schematic diagram of the existing POP encapsulating structure of Fig. 1；
Fig. 2 is the schematic diagram of the POP encapsulating structure according to the present invention；
Fig. 3 is the schematic diagram of the articulamentum in Fig. 2.
Detailed description of the invention
Hereinafter, according to an embodiment of the invention POP encapsulating structure is described in detail with reference to the attached drawings.In the following description, in order to more precisely bright technical scheme, the technology contents being not directly dependent upon with the present invention for this area omits the description.Part building block is in the accompanying drawings by suitably expansion, omission and simplification, and the size of each building block is not equivalent to actual size.
As shown in Figure 2 to Figure 3, POP encapsulating structure according to embodiments of the present invention includes: upper strata encapsulating structure 100, lower floor's encapsulating structure 200 and articulamentum 300.In the present embodiment, described upper strata encapsulating structure 100 and lower floor's encapsulating structure 200 are ball grid array package structure (BGA).Thus, described upper strata encapsulating structure 100 is connected with described lower floor encapsulating structure 200 formation by soldered ball 101 and articulamentum 300.Wherein, described soldered ball 101 and the encapsulating structure 200 formation electrical connection of described lower floor.Specifically, it is provided with in the encapsulating material 202 of described lower floor encapsulating structure 200 and forms, with described soldered ball 101, the conductive pole 201 being electrically connected, the soldered ball 101 arranging position and quantity and described upper strata encapsulating structure 100 of this conductive pole 201 is mutually corresponding, and described conductive pole 201 forms electrical connection through described encapsulating material 202 with the pad (not shown) in PCB substrate 203, so that POP encapsulating structure performs complicated function.Obviously, when lower floor's encapsulating structure 200 only arranges encapsulating material at central part, when causing the soldered ball 101 of upper strata encapsulating structure 100 directly facing the PCB substrate of lower floor's encapsulating structure 200, soldered ball 101 is directly welded on the pad of this PCB substrate.In the present invention, connect outside upper strata encapsulating structure 100 and lower floor's encapsulating structure 200 except with soldered ball 101, articulamentum 300 is set up extraly between two encapsulating structures 100,200, so that stress is distributed to central part, stress is avoided to focus on the corner parts of soldered ball and the junction of lower floor's encapsulating structure, thus preventing the tilting of soldered ball.Wherein, described articulamentum 300 is made up of solder layer 301, metal level 302, adhesive linkage 303 from top to bottom successively.Described solder layer 301 is formed with the bottom surface of described upper strata encapsulating structure 100 and is connected, and for this, the lower surface of described upper strata encapsulating structure 100 can also arrange the copper area of coverage, to improve soldering reliability.Preferably, the area of the described copper area of coverage is more than the area of solder layer 301.Described metal level 302 is arranged at the downside of described solder layer 301, also has heat sinking function while increasing the stability of articulamentum 300.Preferably, described metal level is layers of copper, but is not limited thereto, it is also possible to adopt other metals with good heat sinking function and welding effect.Described adhesive linkage 303 is arranged at below described metal level 302, and is formed with the upper surface of described lower floor encapsulating structure 200 and be connected.Preferably, described adhesive linkage 303 is made up of heat-conducting glue, to improve the heat dispersion of POP encapsulating structure.And, the upper surface of described lower floor encapsulating structure 200 is provided with adhesion zone, and in order to arrange described adhesive linkage 303, and the area of described adhesion zone is more than the area of described adhesive linkage 303.Now, described adhesion zone can include common double faced adhesive tape, it is also possible to is the region carrying out roughening after individually dividing.And, in the present invention, described articulamentum is not limited to said structure, namely can arrange liquid glue in the both sides of metal level, substitutes adhesive linkage and solder layer.
Hereinafter, the manufacture method of the POP encapsulating structure according to the present invention described above is illustrated.
First, upper strata encapsulating structure and lower floor's encapsulating structure are made.In the present embodiment, described upper strata encapsulating structure and lower floor's encapsulating structure are ball grid array package structure, but described upper strata encapsulating structure is not limited to this.When described upper strata encapsulating structure adopts the encapsulating structure of other forms, it is possible to separately set cylindrical conducting body to substitute soldered ball.The manufacture method of described upper strata encapsulating structure and lower floor's encapsulating structure belongs to the category of prior art, is therefore not described in detail in this.
After complete upper strata encapsulating structure and lower floor's encapsulating structure, carrying out every test, the content of test includes electrical characteristics test and visual examination.Thus, using one of them non-defective unit of obtaining as the lower floor's encapsulating structure in POP encapsulating structure.Now, the encapsulating material of described lower floor encapsulating structure is likely to comprise the conductive pole of the upper surface for the circuit of PCB substrate extends to lower floor's encapsulating structure, described conductive pole can be formed in the manufacture process of lower floor's encapsulating structure, it is also possible to is formed by the mode of perforation filled conductive material after producing lower floor's encapsulating structure.
Then, the adhesive linkage of articulamentum is arranged at above described weld zone.At this point it is possible to optionally form adhesion zone at the upper surface of described lower floor encapsulating structure, to be arranged above with articulamentum in this adhesion zone.Described adhesion zone can include common double faced adhesive tape and constitute, it is also possible to be the region carrying out roughening after the upper surface to described lower floor encapsulating structure carries out individually division and increasing adhesive property.In the present embodiment, described articulamentum is made up of solder layer, metal level and adhesive linkage from top to bottom successively.Wherein, described metal level is preferably layers of copper, and described adhesive linkage is made up of heat-conducting glue.Now, the forming process of described articulamentum is as follows.First, adhesive linkage is set at the upper surface of lower floor's encapsulating structure.Then, stickup metal level on described adhesive linkage.Finally, solder layer is set at the upper surface of described metal level.And, in the present invention, described articulamentum is not limited to said structure, namely can arrange liquid glue in the both sides of metal level, substitutes adhesive linkage and solder layer.
Then, upper strata encapsulating structure is arranged on above described lower floor encapsulating structure.At this point it is possible to optionally arrange the copper area of coverage at the lower surface of upper strata encapsulating structure, to increase soldering reliability.And it is possible at the applied atop scaling powder of the described copper area of coverage.The described copper area of coverage can be formed at the bottom surface of described upper strata encapsulating structure by the mode of the coat of metal.So, the soldered ball being distributed in upper strata encapsulating structure bottom surface periphery is made to align with the conductive pole of lower floor encapsulating structure or the pad of PCB substrate, and make the described copper area of coverage be directed at the solder layer of described articulamentum, then, in special equipment, the soldered ball of upper strata encapsulating structure is made to form electrical connection with the conductive pole of lower floor's encapsulating structure.
Then, the POP encapsulating structure formed through above-mentioned steps being carried out every test, wherein test content includes electrical characteristics test and visual examination.
Thus, complete the manufacture process of POP encapsulating structure, and final finished is packed.
Adopt the POP encapsulating structure that above-mentioned manufacturing process produces, due to be provided with in the centre of upper and lower two encapsulating structures can the articulamentum of dispersive stress, therefore, it is possible to improve connection reliability.
The invention is not restricted to above-described embodiment, without departing from the present invention, it is possible to carry out various changes and modifications.
Claims (10)
1. a laminated packaging structure, including upper strata encapsulating structure and lower floor's encapsulating structure, the soldered ball of wherein said upper strata encapsulating structure is by being welded to connect in the upper surface of described lower floor encapsulating structure, characterized by further comprising the articulamentum being arranged between described upper strata encapsulating structure and described lower floor encapsulating structure, and this articulamentum include:
The solder layer being connected is formed with the lower surface of described upper strata encapsulating structure；
It is arranged at the metal level on the downside of described solder layer；
Being arranged at the adhesive linkage on the downside of described metal level, this adhesive linkage is formed with lower floor encapsulating structure and is connected.
2. laminated packaging structure according to claim 1, it is characterised in that the lower surface of described upper strata encapsulating structure is provided with the copper area of coverage, is connected to be formed with described solder layer.
3. laminated packaging structure according to claim 1, it is characterised in that the upper surface of described upper strata encapsulating structure is provided with adhesion zone, is connected to be formed with described adhesive linkage.
4. laminated packaging structure according to claim 1, it is characterised in that described metal level is layers of copper.
5. laminated packaging structure according to claim 1, it is characterised in that described adhesive linkage is formed by heat-conducting glue.
6. the manufacture method of a laminated packaging structure, it is characterised in that comprise the following steps:
Make upper strata encapsulating structure and lower floor's encapsulating structure；
Articulamentum is arranged at the upper surface of described lower floor encapsulating structure；
By the soldered ball of described articulamentum and upper strata encapsulating structure, upper strata encapsulating structure is arranged at above described lower floor encapsulating structure,
Wherein, described articulamentum includes:
The solder layer being connected is formed with the lower surface of described upper strata encapsulating structure；
It is arranged at the metal level on the downside of described solder layer；
Being arranged at the adhesive linkage on the downside of described metal level, this adhesive linkage is formed with lower floor encapsulating structure and is connected.
7. the manufacture method of laminated packaging structure according to claim 6, it is characterised in that in the step of described making upper strata encapsulating structure and lower floor's encapsulating structure, the upper surface being additionally included in described lower floor encapsulating structure arranges the step of adhesion zone.
8. the manufacture method of laminated packaging structure according to claim 6, it is characterised in that in the step of described making upper strata encapsulating structure and lower floor's encapsulating structure, the bottom surface being additionally included in described upper strata encapsulating structure arranges the step of the copper area of coverage.
9. the manufacture method of laminated packaging structure according to claim 6, it is characterised in that described metal level is layers of copper.
10. the manufacture method of laminated packaging structure according to claim 6, it is characterised in that described adhesive linkage is formed by heat-conducting glue.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110059126.2A CN102683322B (en) | 2011-03-09 | 2011-03-09 | POP encapsulating structure and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110059126.2A CN102683322B (en) | 2011-03-09 | 2011-03-09 | POP encapsulating structure and manufacture method thereof |
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| CN102683322A CN102683322A (en) | 2012-09-19 |
| CN102683322B true CN102683322B (en) | 2016-07-06 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411373A (en) * | 2018-09-18 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | A method of realizing that multilager base plate is three-dimensional stacked using carrier supported |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426869B (en) * | 2013-07-30 | 2016-03-30 | 三星半导体(中国)研究开发有限公司 | Package on package and manufacture method thereof |
| TW201640590A (en) * | 2015-05-04 | 2016-11-16 | 矽品精密工業股份有限公司 | Electronic package structure and the manufacture thereof |
| CN106374208B (en) * | 2016-10-09 | 2019-06-18 | 华进半导体封装先导技术研发中心有限公司 | High bandwidth organic substrate antenna structure and production method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1959966A (en) * | 2005-09-27 | 2007-05-09 | 艾格瑞系统有限公司 | Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink |
| CN101217141A (en) * | 2007-01-03 | 2008-07-09 | 三星电子株式会社 | IC package and method of manufacturing the same |
| US7851894B1 (en) * | 2008-12-23 | 2010-12-14 | Amkor Technology, Inc. | System and method for shielding of package on package (PoP) assemblies |
-
2011
- 2011-03-09 CN CN201110059126.2A patent/CN102683322B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1959966A (en) * | 2005-09-27 | 2007-05-09 | 艾格瑞系统有限公司 | Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink |
| CN101217141A (en) * | 2007-01-03 | 2008-07-09 | 三星电子株式会社 | IC package and method of manufacturing the same |
| US7851894B1 (en) * | 2008-12-23 | 2010-12-14 | Amkor Technology, Inc. | System and method for shielding of package on package (PoP) assemblies |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411373A (en) * | 2018-09-18 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | A method of realizing that multilager base plate is three-dimensional stacked using carrier supported |
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| CN102683322A (en) | 2012-09-19 |
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