CN103560117B - Heat dissipation structure for PoP packaging - Google Patents
Heat dissipation structure for PoP packaging Download PDFInfo
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- CN103560117B CN103560117B CN201310530690.7A CN201310530690A CN103560117B CN 103560117 B CN103560117 B CN 103560117B CN 201310530690 A CN201310530690 A CN 201310530690A CN 103560117 B CN103560117 B CN 103560117B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 99
- 230000017525 heat dissipation Effects 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 48
- 238000005538 encapsulation Methods 0.000 claims description 41
- 239000011889 copper foil Substances 0.000 claims description 25
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 230000005611 electricity Effects 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000005855 radiation Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
The invention discloses a heat radiation structure for PoP packaging, which comprises: the upper-layer packaging body comprises an upper-layer packaging substrate and a plurality of upper-layer packaging heat-conducting chips or devices which are attached to or welded on a plurality of thermal vias in the upper-layer packaging substrate of the upper-layer packaging body; the lower-layer packaging body comprises a lower-layer packaging substrate and a plurality of lower-layer packaging heat-conducting chips or devices attached to or welded on the surface of the lower-layer packaging substrate; the BGA supporting balls are formed between the upper-layer packaging body and the lower-layer packaging body and electrically connected with the upper-layer packaging body and the lower-layer packaging body; BGA balls formed on the back of the lower package substrate of the lower package body to support the upper and lower package bodies; the heat dissipation cover is covered on the upper layer packaging body so as to realize heat dissipation and shielding of the upper layer packaging heat conduction chip or the device of the upper layer packaging body; and the thermal interface material is formed between the upper-layer packaging heat-conducting chip or device of the upper-layer packaging body and the heat dissipation cover so as to reduce the contact thermal resistance between the upper-layer packaging body and the heat dissipation cover.
Description
Technical field
The present invention relates to internal memory and processor is integrated and radio frequency (Radio Frequency, RF) transmitting-receiving
Stacked package (Pacakge on Package, the PoP) technical field that assembly is integrated, especially a kind of
Radiator structure for PoP encapsulation.
Background technology
Fig. 1 is the schematic diagram of PoP encapsulating structure in prior art, and wherein 10 is upper strata encapsulating structure；
11 is BGA (Ball Grid Array, BGA) soldered ball；20 is lower floor's encapsulating structure；21 are
Conductive pole；22 is packaging EMC material；23 is PCB substrate；30 is articulamentum；Articulamentum 30 by
Solder layer 31, metal level 32 and tack coat 33 form.This PoP encapsulating structure is by upper strata encapsulation knot
Structure 10 and lower floor's encapsulating structure 20 are interconnected and form by BGA soldered ball 11 and articulamentum 30.BGA
Soldered ball 11 plays the effect of electric interconnection, have in the packaging EMC material 22 of lower floor's encapsulating structure 20 with
The conductive pole 21 of BGA soldered ball 11 electrical connection.The effect of articulamentum 30 is to avoid stress to focus on
Soldered ball and the corner parts of the junction of lower floor's encapsulating structure, be distributed to central part by stress, from
And prevent the warpage of soldered ball.But, the heat radiation of upper strata encapsulation is a bottleneck, and upper strata encapsulation chip produces
Raw most of heat supports ball, lower floor's packaging body through upper strata packaging body, BGA, then conducts to base
Plate, finally shed external environment, and heat is not easy to shed, and affects packaging body junction temperature and raises, limits heap
Folded chip power and stacking quantity.The packaging body quantity of general stacking is less than two.
Summary of the invention
(1) to solve the technical problem that
In view of this, present invention is primarily targeted at a kind of heat radiation knot for PoP encapsulation of raising
Structure, to solve the heat dissipation problem of upper strata packaging body.
(2) technical scheme
For reaching above-mentioned purpose, the invention provides a kind of radiator structure for PoP encapsulation, including:
Upper strata packaging body, including upper layer package substrate 100 and the upper strata encapsulation being attached to or being welded in upper strata packaging body
Multiple upper stratas on multiple thermal holes (thermal via) 101 encapsulation heat conduction chip or device in substrate 100
Part 201；Lower floor's packaging body, including lower layer package substrate 300 be attached to or be welded in lower layer package substrate
Multiple lower floors encapsulation heat conduction chip on 300 surfaces or device 202；BGA supports ball 400, is formed at
Between upper strata packaging body and lower floor's packaging body, it is achieved the electricity interconnection of two-layer packaging body up and down, and support
Layer packaging body；BGA ball 500, is formed at the back side of the lower layer package substrate 300 of lower floor's packaging body,
To support upper and lower two-layer packaging body；Heat dissipating housing 700, is covered on the packaging body of upper strata, on realizing
The upper strata encapsulation heat conduction chip of layer packaging body or device 201 dispel the heat and shield；And thermal interfacial material
600, be formed at the upper strata encapsulation heat conduction chip of upper strata packaging body or device 201 and heat dissipating housing 700 it
Between, to reduce the thermal contact resistance between upper strata packaging body and heat dissipating housing.
In such scheme, described upper layer package substrate 100 includes: multilamellar large area Copper Foil 102；Many
Layer dielectric layer 103, is formed between multilamellar large area Copper Foil 102；Multiple thermal via101, point
Cloth, at multiple upper stratas encapsulation heat conduction chip or the lower surface of device 201, runs through multilamellar large area Copper Foil
102 and multilayer dielectricity layer 103, and in thermal via101, fill full copper；And multiple half via
104, it is distributed in layer package substrate surface perimeter part, runs through multilamellar large area Copper Foil 102 with many
Layer dielectric layer 103, and in half via 104, fill full copper.
In such scheme, described large area Copper Foil 102 uses thick copper, and thickness range is 12～36 μm,
And large area Copper Foil 102 interconnects with half via 104, half via 104 is filled full copper, half via 104
It is connected with heat dissipating housing 700.
In such scheme, described heat dissipating housing 700, as radome, uses frivolous material, such as aluminum,
Allumen etc..
In such scheme, a part of heat warp that described upper strata encapsulation heat conduction chip or device 201 produce
Thermal via101 conducts to any layer large area Copper Foil 102, is then conducted to the full copper of filling
Half via 104, after shed through heat dissipating housing 700；A part of heat is through the hot boundary of high heat conductance
Face material 600 is transmitted on heat dissipating housing 700, then is transmitted in external environment condition；Some heat
Ball 400, lower floor's packaging body and conduction is supported to lower floor's packaging body successively through upper strata packaging body, BGA
Under pcb board, finally shed to external environment.
In such scheme, under the heat that described lower floor encapsulation heat conduction chip or device 202 produce warp successively
Pcb board under layer packaging body, BGA ball and lower floor's packaging body is transmitted in external environment condition.
(3) beneficial effect
The radiator structure for PoP encapsulation that the present invention provides, upper strata packaging body uses thermal via+
The radiator structure of large area Copper Foil+half via+high thermal conductivity thermal interfacial material, upper strata encapsulation heat conduction chip
Or a part of heat that device 201 produces conducts to any layer large area Copper Foil through thermal via101
On 102, be then conducted to half via 104 filling full copper, after shed through heat dissipating housing 700；
A part of heat is transmitted on heat dissipating housing 700 through the thermal interfacial material 600 of high heat conductance, then is transmitted to
In external environment condition；Some heat supports ball 400, lower floor through upper strata packaging body, BGA successively
Packaging body and the pcb board conducted to lower floor's packaging body, finally shed to external environment, effectively
Solve the heat dissipation problem of upper strata packaging body.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of PoP encapsulating structure in prior art；
Fig. 2 is the schematic diagram of the radiator structure for PoP encapsulation according to the embodiment of the present invention；
Fig. 3 to Fig. 9 is the work making the radiator structure encapsulated for PoP according to the embodiment of the present invention
Process flow figure；Wherein:
Fig. 3 be according to the embodiment of the present invention containing large area Copper Foil, thermal via and half mistake
The structural representation of the upper layer package substrate in hole；
Fig. 4 be according to the embodiment of the present invention containing large area Copper Foil, thermal via and half mistake
The top view of the upper layer package substrate in hole；
Fig. 5 is to encapsulate according to the upper strata that formed after upper layer package substrate paster of the embodiment of the present invention
The structural representation of body；
Fig. 6 is to encapsulate according to the lower floor that formed after lower layer package substrate paster of the embodiment of the present invention
The structural representation of body；
Fig. 7 be according to the embodiment of the present invention after BGA ball is planted at the upper layer package substrate back side
Structural representation；
After Fig. 8 is the upper strata packaging body according to the embodiment of the present invention and lower floor's packaging body realization interconnection
Structural representation；
Fig. 9 be according to the embodiment of the present invention after lower floor's packaging body substrate back plants BGA ball
Structural representation.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with concrete real
Execute example, and referring to the drawings, the present invention is described in more detail.
As in figure 2 it is shown, Fig. 2 is the radiator structure for PoP encapsulation according to the embodiment of the present invention
Schematic diagram, this be used for PoP encapsulation radiator structure, including:
Upper strata packaging body, including upper layer package substrate 100 and the upper strata being attached to or being welded in upper strata packaging body
Multiple upper stratas on multiple thermal via101 encapsulation heat conduction chip or device in base plate for packaging 100
201；
Lower floor's packaging body, including lower layer package substrate 300 be attached to or be welded in lower layer package substrate 300
Multiple lower floors encapsulation heat conduction chip on surface or device 202；
BGA supports ball 400, is formed between upper strata packaging body and lower floor's packaging body, it is achieved upper and lower two
The electricity interconnection of layer packaging body, and support upper strata packaging body；
BGA ball 500, is formed at the back side of the lower layer package substrate 300 of lower floor's packaging body, to support
Two-layer packaging body up and down；
Heat dissipating housing 700, is covered on the packaging body of upper strata, to realize the upper strata encapsulation of upper strata packaging body
Heat conduction chip or device 201 dispel the heat and shield；And
Thermal interfacial material 600, is formed at upper strata encapsulation heat conduction chip or the device 201 of upper strata packaging body
And between heat dissipating housing 700, to reduce the thermal contact resistance between upper strata packaging body and heat dissipating housing.
Wherein, upper layer package substrate 100 includes: multilamellar large area Copper Foil 102；Multilayer dielectricity layer 103,
It is formed between multilamellar large area Copper Foil 102；Multiple thermal via101, are distributed in multiple upper strata
Encapsulation heat conduction chip or the lower surface of device 201, run through multilamellar large area Copper Foil 102 and multilayer dielectricity
Layer 103, and in thermal via101, fill full copper；And multiple half via 104, it is distributed in
Layer package substrate surface perimeter part, runs through multilamellar large area Copper Foil 102 and multilayer dielectricity layer 103,
And in half via 104, fill full copper.
Large area Copper Foil 102 uses thick copper, and thickness range is 12～36 μm and large area Copper Foil 102
Interconnecting with half via 104, fill full copper in half via 104, half via 104 is with heat dissipating housing 700 even
Connect.Heat dissipating housing 700, as radome, uses frivolous material, such as aluminum, allumen etc..
A part of heat that upper strata encapsulation heat conduction chip or device 201 produce passes through thermal via101
It is directed on any layer large area Copper Foil 102, is then conducted to half via 104 filling full copper,
Shed by heat dissipating housing 700；A part of heat is transmitted to through the thermal interfacial material 600 of high heat conductance
On heat dissipating housing 700, then it is transmitted in external environment condition；Some heat successively through upper strata packaging body,
BGA supports ball 400, lower floor's packaging body and the pcb board conducted to lower floor's packaging body, finally
Shed to external environment.
The heat that lower floor's encapsulation heat conduction chip or device 202 produce is successively through lower floor's packaging body, BGA
Pcb board under ball and lower floor's packaging body is transmitted in external environment condition.
Based on the radiator structure for PoP encapsulation shown in Fig. 2, Fig. 3 to Fig. 9 shows according to this
The process chart making the radiator structure encapsulated for PoP of inventive embodiments, specifically includes following
Step:
Step 1: layer package substrate 100 in making；Its manufacture method is first by large area Copper Foil 102
Forming substrate with dielectric layer 103 successively crossing stack, then the mid portion at this substrate surface punches
And fill copper and form multiple thermal via101, and beat half bore in the surrounding of this substrate surface and fill
Copper forms multiple half via 104；As shown in Figure 3 and Figure 4.
Step 2: multiple upper stratas encapsulation heat conduction chip or device 201 are attached to or are welded in upper strata encapsulation
In substrate 100 on multiple thermal via101, form upper strata packaging body；As shown in Figure 5.
Step 3: make upper strata packaging body；Multiple lower floors encapsulation heat conduction chip or device 202 are attached to
Or it is welded on lower layer package substrate 300, forms lower floor's packaging body；As shown in Figure 6.
Step 4: brush tin cream on upper layer package substrate 100 backside pads, steel mesh plants BGA ball also
Backflow, forms BGA and supports ball 400, and wherein BGA supports ball 400 1 aspect and realizes upper and lower two-layer
The electricity interconnection of packaging body, on the other hand plays the effect supporting upper strata packaging body；As shown in Figure 7.
Step 5: brush solder(ing) paste on lower floor's packaging body 300 upper surface of base plate pad, lower floor's encapsulation weldering
After dish aligns with upper strata packaging body BGA support ball 400, backflow realizes upper strata packaging body and seals with lower floor
Dress body interconnection, thus reach the purpose of three-dimension packaging；As shown in Figure 8.
Step 6: brush tin cream on lower floor's packaging body 300 substrate back pad, BGA ball planted by steel mesh
500, backflow realizes lower floor's packaging body and plants ball；As shown in Figure 9.
Step 7: in order to realize upper strata encapsulation heat conduction chip or device 201 purpose dispelling the heat and shield,
Packaging body top, upper strata arranges a heat dissipating housing 700, in order to reduce upper strata packaging body and heat dissipating housing
The thermal contact resistance of 700, is coated with one between upper strata encapsulation heat conduction chip or device 201 and heat dissipating housing 700
Floor height thermal conductivity thermal interfacial material 600.The radiator structure such as Fig. 2 for PoP encapsulation ultimately formed
Shown in.
Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect
Further describe, be it should be understood that the foregoing is only the present invention specific embodiment and
, be not limited to the present invention, all within the spirit and principles in the present invention, that is done any repaiies
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (3)
1. the radiator structure for PoP encapsulation, it is characterised in that including:
Upper strata packaging body, including upper layer package substrate (100) be attached to or be welded in upper strata packaging body
In upper layer package substrate (100) the multiple upper stratas on multiple thermal holes (101) encapsulation heat conduction chip or
Device (201)；
Lower floor's packaging body, including lower layer package substrate (300) be attached to or be welded in lower layer package substrate
(300) multiple lower floors on surface encapsulate heat conduction chip or device (202)；
BGA supports ball (400), is formed between upper strata packaging body and lower floor's packaging body, it is achieved on
The electricity interconnection of lower two-layer packaging body, and support upper strata packaging body；
BGA ball (500), is formed at the back side of the lower layer package substrate (300) of lower floor's packaging body,
To support upper and lower two-layer packaging body；
Heat dissipating housing (700), is covered on the packaging body of upper strata, to realize the upper strata envelope of upper strata packaging body
Dress heat conduction chip or device (201) dispel the heat and shield；And
Thermal interfacial material (600), is formed at upper strata encapsulation heat conduction chip or the device of upper strata packaging body
(201) and between heat dissipating housing (700), heat is contacted to reduce between upper strata packaging body and heat dissipating housing
Resistance；
Wherein, described upper layer package substrate (100) including:
Multilamellar large area Copper Foil (102)；
Multilayer dielectricity layer (103), is formed between multilamellar large area Copper Foil (102)；
Multiple thermal holes (101), are distributed in multiple upper strata encapsulation heat conduction chip or device (201)
Lower surface, run through multilamellar large area Copper Foil (102) and multilayer dielectricity layer (103), and in heat conduction
Hole (101) is filled full copper；And
Multiple half vias (104), are distributed in layer package substrate surface perimeter part, run through many
Layer large area Copper Foil (102) and multilayer dielectricity layer (103), and fill full in half via (104)
Copper.
Radiator structure for PoP encapsulation the most according to claim 1, it is characterised in that
Described large area Copper Foil (102) uses thick copper, and thickness range is 12～36 μm, and large area Copper Foil
(102) interconnect with half via (104), half via (104) is filled full copper, half via (104)
It is connected with heat dissipating housing (700).
Radiator structure for PoP encapsulation the most according to claim 1, it is characterised in that
Described heat dissipating housing (700) is as radome, and the material of employing is aluminum or allumen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310530690.7A CN103560117B (en) | 2013-10-31 | 2013-10-31 | Heat dissipation structure for PoP packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310530690.7A CN103560117B (en) | 2013-10-31 | 2013-10-31 | Heat dissipation structure for PoP packaging |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103560117A CN103560117A (en) | 2014-02-05 |
| CN103560117B true CN103560117B (en) | 2016-09-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310530690.7A Active CN103560117B (en) | 2013-10-31 | 2013-10-31 | Heat dissipation structure for PoP packaging |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106409774B (en) * | 2015-07-31 | 2019-04-26 | 鹏鼎控股(深圳)股份有限公司 | Shielding case, encapsulating structure and encapsulating structure production method |
| CN117276218A (en) * | 2023-11-23 | 2023-12-22 | 天通瑞宏科技有限公司 | Semiconductor packaging structure |
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| CN101937907A (en) * | 2009-06-29 | 2011-01-05 | 财团法人工业技术研究院 | Chip stacking package structure and manufacture method thereof |
| CN102573279A (en) * | 2010-11-17 | 2012-07-11 | 三星电子株式会社 | Semiconductor package and method of forming the same |
| CN103050455A (en) * | 2011-10-17 | 2013-04-17 | 联发科技股份有限公司 | Package on package structure |
| CN203659838U (en) * | 2013-10-31 | 2014-06-18 | 中国科学院微电子研究所 | Heat dissipation structure for PoP packaging |
-
2013
- 2013-10-31 CN CN201310530690.7A patent/CN103560117B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937907A (en) * | 2009-06-29 | 2011-01-05 | 财团法人工业技术研究院 | Chip stacking package structure and manufacture method thereof |
| CN102573279A (en) * | 2010-11-17 | 2012-07-11 | 三星电子株式会社 | Semiconductor package and method of forming the same |
| CN103050455A (en) * | 2011-10-17 | 2013-04-17 | 联发科技股份有限公司 | Package on package structure |
| CN203659838U (en) * | 2013-10-31 | 2014-06-18 | 中国科学院微电子研究所 | Heat dissipation structure for PoP packaging |
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| CN103560117A (en) | 2014-02-05 |
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