CN102487031A - Method for forming trench isolation - Google Patents
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- CN102487031A CN102487031A CN2010105697606A CN201010569760A CN102487031A CN 102487031 A CN102487031 A CN 102487031A CN 2010105697606 A CN2010105697606 A CN 2010105697606A CN 201010569760 A CN201010569760 A CN 201010569760A CN 102487031 A CN102487031 A CN 102487031A
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Abstract
The invention discloses a method for forming trench isolation. The method comprises the following steps of: forming a first silicon oxide layer on the surface of a semiconductor chip by adopting a low-pressure chemical vapor deposition process; etching in the first silicon oxide layer to form a trench pattern; by using the etched first silicon oxide layer as a mask, etching in the semiconductor chip to form a trench; removing the first silicon oxide layer; carrying out trench oxidation, and forming a silicon oxide insulating region on the surface of the trench; adopting the low-pressure chemical vapor deposition process to deposit polycrystalline silicon for filling the trench; and carrying out flattened back etching of polycrystalline silicon. According to the technical scheme provided by the invention, the low-pressure chemical vapor deposition process is adopted to fill the trench, a flattened back etching process is adopted to flatten the surface of the chip, and high-density plasma gas chemical vapor deposition equipment and chemical-mechanical flattening equipment with higher cost are not needed. The method can be compatible with the existing process platform and is convenient for large-scale application in practical production.
Description
Technical field:
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of trench isolations formation method of semiconductor device.
Background technology:
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster.Bigger memory data output and more function; Semiconductor wafer develops towards higher component density, high integration direction; Distance in the chip between two adjacent semiconductor device is also more and more approaching; Therefore need between two adjacent semiconductor device, isolated area be set, to isolate unwanted leakage current.
Trench isolations is a kind of common concrete way of realization of isolated area; Can greatly dwindle the isolation area; Thereby reduce whole chip cost; Its manufacturing approach is divided into three key steps usually: etching groove, insulation material are filled and the planarization of insulation material, through filling the insulation material in the groove that between two adjacent semiconductor device, is provided with, realize the electrical isolation between the adjacent semiconductor device.At present; Field of semiconductor manufacture; Usually adopt HDPCVD (high-density plasma chemical vapordeposition; The vapor deposition of high-density plasma aerochemistry) mode is implemented in fill oxide insulation material in the groove, and carries out the planarization of oxide through the mode of CMP (chemical mechanical planarization, chemical-mechanical planarization).
Yet, in the above-mentioned prior art, needing to use special-purpose high-density plasma aerochemistry vapor deposition device and chemical-mechanical planarization equipment, the cost of this kind equipment is higher, and is difficult to the existing processes platform compatible.
Summary of the invention
For solving the problems of the technologies described above; The object of the present invention is to provide a kind of trench isolations formation method that can be compatible with the existing processes platform; Make in the trench isolations manufacturing process, need not higher high-density plasma aerochemistry vapor deposition device of use cost and chemical-mechanical planarization equipment.
For realizing above-mentioned purpose, the invention provides following technical scheme:
A kind of trench isolations formation method comprises:
Adopt low-pressure chemical vapor phase deposition technology on semiconductor wafer surface, to form first silicon oxide layer;
Etching forms groove figure in first silicon oxide layer;
With first silicon oxide layer after the etching is that mask etching in semiconductor wafer forms groove;
Remove first silicon oxide layer;
Carry out the groove oxidation, on flute surfaces, form insulation regions of silicon oxide;
Adopt low-pressure chemical vapor phase deposition technology deposit polysilicon filling groove;
Carrying out the polysilicon planarization eat-backs.
Preferably,
The thickness of said first silicon oxide layer is not more than 4000 dusts.
Preferably,
Adopt dry etch process etching in first silicon oxide layer to form groove figure.
Preferably, after forming groove figure, also comprise:
Adopt wet-etching technology to remove photoresist layer.
Preferably,
Adopt wet-etching technology to remove first silicon oxide layer, the ratio of hydrofluoric acid and ammonium fluoride is 1: 20 in the etching solution, and etch period is for being not more than 2 minutes.
Preferably,
Temperature when carrying out the groove oxidation is not less than 1150 degrees centigrade.
Preferably,
Adopt thermal oxide growth technology to carry out the groove oxidation.
Preferably,
Carry out also comprising after the polysilicon planarization eat-backs:
Adopt the deposit on semiconductor wafer surface of low-pressure vapor phase depositing technics to form second silicon oxide layer;
Etching forms the groove protection zone in second silicon oxide layer.
Preferably,
Adopt wet-etching technology etching in second silicon oxide layer to form the groove protection zone.
Preferably,
The thickness of said second silicon oxide layer is not more than 4000 dusts.
Use the technical scheme that the embodiment of the invention provided; Mainly adopted low-pressure chemical vapor phase deposition technology and planarization etch-back technics to make trench isolations; Need not higher high-density plasma aerochemistry vapor deposition device of use cost and chemical-mechanical planarization equipment; And can be compatible mutually with the existing processes platform, be convenient to be applied in the actual production on a large scale.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the schematic flow sheet of the trench isolations formation method that provides in the embodiment of the invention one;
Fig. 2 is the structural representation of soi semiconductor wafer provided by the invention after forming first silicon oxide layer;
Fig. 3 is for comprising the structural representation of the semiconductor wafer of groove figure in first silicon oxide layer provided by the invention;
Fig. 4 is the structural representation behind the etching formation groove in the semiconductor wafer provided by the invention;
Fig. 5 is the partial structurtes sketch map of the semiconductor wafer of big BOX loss provided by the invention;
Fig. 6 is the partial structurtes sketch map of the semiconductor wafer that provides in the embodiment of the invention one;
Fig. 7 is the semiconductor chip structure sketch map behind the deposit polysilicon provided by the invention;
Fig. 8 is the semiconductor chip structure sketch map that forms in the embodiment of the invention one;
Fig. 9 is the semiconductor chip structure sketch map behind the formation photoresist pattern in the embodiment of the invention two;
Figure 10 is the semiconductor chip structure sketch map that forms in the embodiment of the invention two.
Embodiment
In the prior art; In the semiconductor device production process; Form trench isolations and need use special-purpose high-density plasma aerochemistry vapor deposition device and chemical-mechanical planarization equipment, the cost of this kind equipment is higher, and is difficult to the existing processes platform compatible.
Therefore; The object of the present invention is to provide can be compatible with the existing processes platform trench isolations formation method; Make in the trench isolations manufacturing process, need not higher high-density plasma aerochemistry vapor deposition device of use cost and chemical-mechanical planarization equipment.
The trench isolations formation method that the embodiment of the invention provides comprises:
Adopt low-pressure chemical vapor phase deposition technology on semiconductor wafer surface, to form first silicon oxide layer; Etching forms groove figure in first silicon oxide layer; With first silicon oxide layer after the etching is that mask etching in semiconductor wafer forms groove; Remove first silicon oxide layer; Carry out the groove oxidation, on flute surfaces, form insulation regions of silicon oxide; Adopt low-pressure chemical vapor phase deposition technology deposit polysilicon filling groove; Carrying out the polysilicon planarization eat-backs.
Use the technical scheme that the embodiment of the invention provided; Mainly adopted low-pressure chemical vapor phase deposition technology and planarization etch-back technics to make trench isolations; Need not higher high-density plasma aerochemistry vapor deposition device of use cost and chemical-mechanical planarization equipment; And can be compatible mutually with the existing processes platform, be convenient to be applied in the actual production on a large scale.
It more than is core concept of the present invention; To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention carried out clear, intactly description, obviously; Described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one:
As shown in Figure 1, a kind of schematic flow sheet of the trench isolations formation method that provides for present embodiment, this method may further comprise the steps:
Step S101 adopts the deposit of low-pressure chemical vapor phase deposition technology to form first silicon oxide layer on semiconductor wafer surface.
In conjunction with shown in Figure 2; It is for adopting SOI (Silicon-On-Insulator; Silicon-on-insulator) structural representation of the semiconductor wafer of technology after forming first silicon oxide layer; 201 for substrate (handle), 202 for bury oxide layer (buried oxide, BOX), 203 be that silicon layer, 204 is first silicon oxide layer.
As a kind of execution mode, can adopt LPTEOS technology deposit silicon dioxide on semiconductor wafer surface, form first silicon oxide layer.As optional implementation, sedimentary condition can for: under low pressure, medium vacuum degree (about 0.1～5 holder), when temperature is 650～750 degrees centigrade, thermal decomposition TEOS (tetraethyl orthosilicate, tetraethoxysilane).Utilize LPTEOS technology can produce the silicon oxide layer of excellent in uniformity.
Step S102, etching forms groove figure in first silicon oxide layer.
As optional execution mode; This step can be realized by following mode; At first on the first silicon oxide layer surface, be coated with photoresist, form photoresist layer, and in photoresist layer, form the photoresist pattern of groove figure through photoetching process; With the photoresist pattern is mask etching in first silicon oxide layer, forms groove figure.In conjunction with shown in Figure 3, it is the structural representation that comprises the semiconductor wafer of groove figure in first silicon oxide layer.Wherein, 201 is that substrate, 202 is that silicon layer, 204 is that first silicon oxide layer, 2041 is that groove figure zone, 205 is photoresist layer for burying oxide layer, 203.
As optional execution mode; In this step, can adopt dry etch process etching first silicon oxide layer, in the dry etching system; Corrasion is through chemical action or physical action; Or chemistry realizes with the acting in conjunction of physics, through dry etch process, can realize less groove dimensions control and the groove dimensions uniformity between the interior or wafer of semiconductor wafer preferably.
In addition, after forming groove figure, the photoresist layer of semiconductor wafer surface is die on, and need it be removed fully, therefore, after forming groove figure, can also comprise: adopt wet-etching technology to remove the photoresist layer on first silicon oxide layer surface.Particularly, can photoresist layer be placed the chemical solution that removes photoresist, the photoresist dissolving is peeled off.
Step S103 is that mask etching in semiconductor wafer obtains groove with first silicon oxide layer.
Illustration ground in this step, adopts first silicon oxide layer that does not reflux as mask, selects for use higher silicon/oxidative silicon to select the corrosive liquid of ratio to carry out etching, to reduce the loss of BOX in the etching groove.In conjunction with shown in Figure 4, it is the structural representation behind the etching formation groove in the semiconductor wafer.Wherein, 201 is that substrate, 202 is that silicon layer, 204 is that first silicon oxide layer, 2041 is that groove figure zone, 2031 is the groove in the semiconductor wafer for burying oxide layer, 203.
Step S104 removes first silicon oxide layer.
The thickness of BOX layer is less, and for example, in the step S101 of this execution mode, first thickness of oxide layer of formation preferably is: be not more than 4000 dusts.In the etching process of removing first silicon oxide layer,, can adopt first silicon oxide layer shown in the wet-etching technology removal for avoiding bigger BOX loss.For example, can adopt BOE (buffer oxide etch, buffer oxide layer etching) technology etching to remove first silicon oxide layer, the ratio of hydrofluoric acid and ammonium fluoride can be 1: 20 in the etching solution, and etch period is not more than 2 minutes.
In conjunction with shown in Figure 5, it is the partial structurtes sketch map that the semiconductor wafer of big BOX loss is arranged, and wherein, 202 are the thickness sketch map of BOX loss for burying oxide layer, 203 for silicon layer, 2021.Referring to shown in Figure 6, the partial structurtes sketch map of the semiconductor wafer that its optional technology that provides for application is above-mentioned forms can know and use the technology that provides in this step that the BOX loss 2021 that forms in the etching is less.Through test, the BOX lossy data that obtains is less than 1000 dusts in actual production.
Step S105 carries out the groove oxidation, on flute surfaces, forms insulation regions of silicon oxide.
Can adopt thermal oxide growth technology to carry out the groove oxidation in this step, form the region of silicon oxide of insulation in flute surfaces.If the temperature during oxidation is low excessively, then possibly have tangible wedge angle in the corner of groove, as shown in Figure 5, this wedge angle zone 2031 can obviously influence the Electric Field Distribution of the semiconductor device that obtains in the successive process.Alternatively, in this step, can adopt 1150 degrees centigrade temperature to carry out thermal oxidation.The groove structure sketch map that obtains when adopting 1150 degrees centigrade shown in Figure 6 can be known that by Fig. 6 corner's wedge angle of groove obviously disappears, and becomes slick and sly round zone 2032, can improve the Electric Field Distribution of follow-up semiconductor device, improves the highest withstand voltage of device.
Step S106 adopts low-pressure chemical vapor phase deposition technology deposit polysilicon filling groove.
This step can be under 575 degrees centigrade to 650 degrees centigrade environment, thermal decomposition of silane, and through LPCVD deposit polysilicon (LPPOLY).As a kind of attainable mode, under low pressure application of pure silane or content are that the mist of 20%～30% silane and nitrogen feeds reaction system, are deposit polysilicon under the condition of 0.2 to 1.0 holder at pressure.
Shown in Figure 7ly be the semiconductor chip structure sketch map behind the deposit polysilicon, wherein, 206 silica in step S105, forming, 207 is the polysilicon of deposit in this step, other icon is identical with above-mentioned other accompanying drawing, repeats no more.
With respect to available technology adopting HDPCVD or SACVD (sub atmospheric chemicalvapor deposition; The meteorological deposit of sub-atmospheric pressure chemistry) mode, the scheme of fill oxide insulation material in groove, the low-pressure chemical vapor phase deposition technology (LPPOLY) that available cost is lower in this step, production capacity is higher; Between the insulation regions of silicon oxide of flute surfaces, fill polysilicon; The scheme that this step provides can make full use of original equipment in the production line, need not to increase special-purpose HDPCVD equipment or SACVD equipment, can be compatible with the existing processes platform; Its development cost is lower, is convenient to large-scale promotion and application.
In addition, in the present embodiment, the polysilicon that silicon oxide region that the filling medium of groove is formed by thermal oxidation and LPPOLY form is formed, and makes trench fill not have the cavity, obtains filling effect preferably.
Step S107 carries out the polysilicon planarization and eat-backs.
In the prior art, after trench fill is accomplished, also need realize the planarization of semiconductor wafer surface, therefore, also need use special-purpose CMP equipment, improve production cost, be unfavorable for large-scale application through chemical-mechanical planarization technology.Adopt the planarization etch-back technics to realize the planarization of semiconductor wafer surface in the present embodiment, and remove the POLY layer that semiconductor wafer surface forms in step S106.
As shown in Figure 8, the structural representation of the semiconductor wafer that finally obtains for present embodiment, its icon is identical with above-mentioned other accompanying drawing, repeats no more.
Use the technical scheme that the embodiment of the invention provided; Mainly adopted low pressure vapor deposition process and planarization etch-back technics to make trench isolations; Need not higher high-density plasma aerochemistry vapor deposition device of use cost and chemical-mechanical planarization equipment; And can be compatible mutually with the existing processes platform, be convenient to be applied in the actual production on a large scale.
Embodiment two:
In order to prevent that follow-up rinsing process from causing damage to the oxide layer of trench isolations opening part, can also protect the trench isolations opening part, present embodiment provides a kind of scheme of protecting trench isolations on the basis of embodiment one:
The difference of this scheme and embodiment one is, after the planarization of step S107 polysilicon is eat-back.Also comprise:
Step S108 adopts the deposit on semiconductor wafer surface of low-pressure vapor phase depositing technics to form second silicon oxide layer.
In this step, also can adopt LPTEOS technology silicon oxide deposition on semiconductor wafer surface, form second silicon oxide layer.Wherein, the thickness of second silicon oxide layer shown in specifically can for: be not more than 4000 dusts.
Step S109, etching forms the groove protection zone in second silicon oxide layer.
In this step; At first on the second silicon oxide layer surface, be coated with photoresist, form photoresist layer, and in photoresist layer, form the photoresist pattern of groove protection zone through photoetching process; With the photoresist pattern is mask etching in second silicon oxide layer, forms groove protection zone figure.As shown in Figure 9, be the semiconductor chip structure sketch map behind the formation photoresist pattern, wherein, 208 is second silicon oxide layer, 209 is photoresist layer.Shown in figure 10, be the final semiconductor chip structure sketch map that forms, its icon is identical with above-mentioned other accompanying drawing, repeats no more.
Concrete, in this step, can adopt wet-etching technology etching second silicon oxide layer.In addition, after forming the groove protection zone, can also comprise, remove the photoresist layer of groove protection zone patterned surface.
The scheme that present embodiment provides is the improvement of on the basis of the scheme that embodiment one provides, carrying out, and therefore, but its part cross-references roughly the same repeats no more at this.The scheme that present embodiment provides; Through the groove protection zone that is provided with, can in follow-up rinsing process, protect the trench isolations opening part, reduce or avoid the loss of the oxide layer of opening part; Improve the insulation effect of trench isolations, the ratio of defects of the semiconductor device that the reduction successive process obtains.
The technical scheme that the embodiment of the invention provides; Adopted low-pressure chemical vapor phase deposition technology and planarization etch-back technics to make trench isolations; Need not higher high-density plasma aerochemistry vapor deposition device of use cost and chemical-mechanical planarization equipment; And can be compatible mutually with the existing processes platform, be convenient to be applied in the actual production on a large scale.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (10)
1. a trench isolations formation method is characterized in that, comprising:
Adopt low-pressure chemical vapor phase deposition technology on semiconductor wafer surface, to form first silicon oxide layer;
Etching forms groove figure in first silicon oxide layer;
With first silicon oxide layer after the etching is that mask etching in semiconductor wafer forms groove;
Remove first silicon oxide layer;
Carry out the groove oxidation, on flute surfaces, form insulation regions of silicon oxide;
Adopt low-pressure chemical vapor phase deposition technology deposit polysilicon filling groove;
Carrying out the polysilicon planarization eat-backs.
2. method according to claim 1 is characterized in that:
The thickness of said first silicon oxide layer is not more than 4000 dusts.
3. method according to claim 1 is characterized in that:
Adopt dry etch process etching in first silicon oxide layer to form groove figure.
4. method according to claim 1 is characterized in that, after forming groove figure, also comprises:
Adopt wet-etching technology to remove photoresist layer.
5. method according to claim 1 is characterized in that:
Adopt wet-etching technology to remove first silicon oxide layer, the ratio of hydrofluoric acid and ammonium fluoride is 1: 20 in the etching solution, and etch period is for being not more than 2 minutes.
6. method according to claim 1 is characterized in that:
Temperature when carrying out the groove oxidation is not less than 1150 degrees centigrade.
7. method according to claim 1 is characterized in that:
Adopt thermal oxide growth technology to carry out the groove oxidation.
8. method according to claim 1 is characterized in that, carries out also comprising after the polysilicon planarization eat-backs:
Adopt the deposit on semiconductor wafer surface of low-pressure vapor phase depositing technics to form second silicon oxide layer;
Etching forms the groove protection zone in second silicon oxide layer.
9. method according to claim 8 is characterized in that,
Adopt wet-etching technology etching in second silicon oxide layer to form the groove protection zone.
10. method according to claim 8 is characterized in that,
The thickness of said second silicon oxide layer is not more than 4000 dusts.
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| CN101567300A (en) * | 2008-04-24 | 2009-10-28 | 中芯国际集成电路制造(上海)有限公司 | Method for removing residue |
| CN101769848A (en) * | 2008-12-30 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting etching fluid filter |
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| US5914523A (en) * | 1998-02-17 | 1999-06-22 | National Semiconductor Corp. | Semiconductor device trench isolation structure with polysilicon bias voltage contact |
| CN1481013A (en) * | 2002-09-04 | 2004-03-10 | 南亚科技股份有限公司 | Method for forming groove isolation structure |
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Application publication date: 20120606 |