CN114361175A

CN114361175A - Three-dimensional memory device and manufacturing method thereof

Info

Publication number: CN114361175A
Application number: CN202210009183.8A
Authority: CN
Inventors: 张坤; 韩玉辉; 夏志良; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-01-05
Filing date: 2022-01-05
Publication date: 2022-04-15

Abstract

The application provides a manufacturing method of a three-dimensional memory device, which comprises the following steps: sequentially forming a stop layer and a first semiconductor layer on a first substrate; forming a stack layer on the first semiconductor layer; forming a channel hole penetrating through the stacked layer, the first semiconductor layer and the stop layer and extending into a part of the first substrate; forming a channel structure in the channel hole, wherein the channel structure comprises a functional layer, a channel layer, a filling part, a first plug and a second plug which are sequentially stacked, the first plug and the second plug are respectively positioned at two opposite ends of the filling part, and the second plug extends through the surface, far away from the first substrate, of the stop layer; the first substrate and the stop layer are removed to expose the second plugs, and each source contact is opposite to one second plug. The present application further provides a three-dimensional memory device. According to the three-dimensional memory device and the manufacturing method thereof, the second plug which completely fills the channel hole and is positioned at one end in the first substrate is formed, so that the channel structure cannot be damaged in the process of removing the first substrate and the stop layer.

Description

Three-dimensional memory device and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a three-dimensional memory device and a method for manufacturing the same.

Background

As the feature size of the planar memory approaches the lower limit, the manufacturing process of the planar memory has been very difficult and the manufacturing cost is very high, and in order to further increase the storage capacity and reduce the storage cost per bit, a three-dimensional memory has been proposed.

At present, in the manufacturing process of the three-dimensional memory, the bottom of a channel hole in a substrate cannot be completely filled, so that a formed channel structure has a gap, and when the substrate of the three-dimensional memory is thinned, a reagent used in the thinning process easily enters the channel structure from the gap to damage the channel structure, so that the performance of the channel structure is influenced, and the performance of the three-dimensional memory is further influenced.

Disclosure of Invention

In order to solve the above technical problem, the present application provides a three-dimensional memory device and a method for manufacturing the same, wherein a trench structure formed in a trench hole includes a second plug, and the second plug completely fills an end of the trench hole located in a first substrate, so that the trench structure is not damaged in a process of removing the first substrate, and thus, performance of the formed three-dimensional memory device is not affected.

An aspect of the present application provides a method of manufacturing a three-dimensional memory device, the method including: providing a first substrate, and sequentially laminating a stop layer and a first semiconductor layer on the first substrate; forming a stacked layer on one side of the first semiconductor layer far away from the stop layer, wherein the stacked layer comprises insulating layers and sacrificial layers which are alternately stacked; forming a plurality of channel holes, wherein each channel hole penetrates through the stacked layer, the first semiconductor layer and the stop layer and extends into a part of the first substrate; forming a channel structure in the channel hole, wherein the channel structure comprises a functional layer, a channel layer, a filling part, and a first plug and a second plug respectively located at two opposite ends of the filling part along a first direction, the second plug is closer to the first semiconductor layer than the first plug, the second plug extends across a surface of the stop layer away from the first substrate, and the first direction is a stacking direction of the insulating layer and the sacrificial layer; and removing the first substrate and the stop layer to expose the second plug.

Another aspect of the present application also provides a three-dimensional memory device, including: the semiconductor device includes a first semiconductor layer, at least one stack structure, a plurality of channel structures, a second semiconductor layer, and a plurality of source contacts. The at least one stacked structure is located on the first semiconductor layer, and the stacked structure includes insulating layers and conductive layers that are alternately stacked. Each channel structure penetrates through the stacked structure and the first semiconductor layer, wherein each channel structure comprises a functional layer, a channel layer, a filling part, and a first plug and a second plug which are located at two opposite ends of the filling part along a first direction in a stacked mode, the second plug is close to the first semiconductor layer compared with the first plug, and the first direction is the stacking direction of the insulating layer and the conducting layer.

According to the three-dimensional memory device and the manufacturing method thereof, the channel structure formed in the channel hole comprises the second plug, and the second plug completely fills one end, located in the first substrate, of the channel hole, so that the channel structure cannot be damaged in the process of removing the first substrate and the stop layer, and therefore the performance of the formed three-dimensional memory device is not affected.

Drawings

In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and obviously, the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a flowchart of a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional structure diagram of the three-dimensional memory device after step S101 in fig. 1 is completed.

Fig. 3 is a schematic cross-sectional structure diagram of the three-dimensional memory device after step S102 in fig. 1 is completed.

Fig. 4 is a schematic cross-sectional structure of a three-dimensional memory device after forming a stacked structure.

Fig. 5 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S103 in fig. 1 is completed.

Fig. 6 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S104 in fig. 1 is completed.

Fig. 7 is a sub-flowchart of step S104 in fig. 1.

Fig. 8 to 10 are schematic cross-sectional structures of a three-dimensional memory device corresponding to the steps of fig. 7.

Fig. 11 is a schematic cross-sectional structure diagram of a three-dimensional memory device after gate line trenches are formed.

Fig. 12 is a schematic cross-sectional structure of a three-dimensional memory device after forming a recess.

Fig. 13 is a schematic cross-sectional structure of a three-dimensional memory device after forming a conductive layer.

Fig. 14 is a schematic cross-sectional structure of a three-dimensional memory device after a gate line gap structure is formed.

Figure 15 is a cross-sectional structure diagram of a three-dimensional memory device after forming peripheral contacts, word line local contacts, and channel local contacts.

Fig. 16 is a cross-sectional structural diagram of a three-dimensional memory device after bonding peripheral contacts, word line local contacts, and channel local contacts to a peripheral circuit layer.

Fig. 17 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S105 in fig. 1 is completed.

Fig. 18 is a schematic cross-sectional structure of the three-dimensional memory device after forming the second semiconductor layer.

Fig. 19 is a schematic cross-sectional structure of a three-dimensional memory device after forming a source contact.

Fig. 20 is a schematic cross-sectional structure of a three-dimensional memory device after formation of source contact openings.

Fig. 21 is a schematic cross-sectional structure of a three-dimensional memory device after forming an interconnect layer.

Fig. 22 is a schematic cross-sectional structure diagram of a three-dimensional memory device according to an embodiment of the present application.

Description of reference numerals: 10-a first substrate; 20-a stop layer; 30-a first semiconductor layer; 40-stacked layers; 401-an insulating layer; 402-a sacrificial layer; 41-stacked structure; 411-end; 35-a first oxide layer; 36-a second oxide layer; 37-a third oxide layer; 403-grooves; 404-a conductive layer; 4041-a gate dielectric layer; 4042-an adhesive layer; 4043-gate; 50-channel holes; 60-channel structure; 61-a functional layer; 611-a barrier layer; 612-a charge storage layer; 613-tunneling layer; 62-a channel layer; 63-a filling section; 64-a first plug; 65-a second plug; 70-a second semiconductor layer; 80-a source contact; 81-source contact opening; 90-grid wire grooves; 91-gate line gap structure; 911-a silicon dioxide layer; 912-a polysilicon portion; 100-peripheral contacts; 110-word line local contacts; 120-channel local contacts; 130-peripheral circuit layer; 140-a second substrate; 150-a first bonding layer; 1501-a first bonding contact; 160-a second bonding layer; 1601 — a second bonding contact; 170-ILD layer; 180-through silicon contacts; 1801 — through silicon contact opening; 190-a spacer layer; 200-an interconnect layer; 2001-redistribution layer; 2002-a passivation layer; 210-contact pads; 300-three dimensional memory device.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.

In the description of the present application, the terms "first", "second", "third", etc. are used for distinguishing different objects, not for describing a particular order, and further, the terms "upper", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present application.

It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for fabricating a three-dimensional memory device according to an embodiment of the present disclosure. As shown in fig. 1, the method of manufacturing the three-dimensional memory device includes the steps of:

s101: a first substrate is provided, and a stop layer and a first semiconductor layer are sequentially stacked on the first substrate.

S102: and forming a stacked layer on one side of the first semiconductor layer far away from the stop layer, wherein the stacked layer comprises insulating layers and sacrificial layers which are alternately stacked.

S103: and forming a plurality of channel holes, wherein each channel hole penetrates through the stacked layer, the first semiconductor layer and the stop layer and extends into part of the first substrate.

S104: and forming a channel structure in the channel hole, wherein the channel structure comprises a functional layer, a channel layer, a filling part, and a first plug and a second plug which are respectively located at two opposite ends of the filling part along a first direction, the first plug and the second plug are sequentially stacked, the second plug is closer to the first semiconductor layer than the first plug, the second plug extends through the surface of the stop layer far away from the first substrate, and the first direction is a stacking direction of the insulating layer and the sacrificial layer.

S105: and removing the first substrate and the stop layer to expose the second plug.

According to the manufacturing method of the three-dimensional memory device, the channel structure formed in the channel hole comprises the second plug, and the second plug completely fills one end, located in the first substrate, of the channel hole, so that the channel structure cannot be damaged in the process of removing the first substrate and the stop layer, and therefore the performance of the formed three-dimensional memory device is not affected.

In the present application, the three-dimensional memory device may be a semiconductor device having a memory cell transistor string, for example, a three-dimensional NAND memory, a three-dimensional ferroelectric memory, a DRAM, or the like.

The method for manufacturing the three-dimensional memory device is further specifically described below with reference to schematic cross-sectional structure diagrams of the three-dimensional memory device during the manufacturing process.

Referring to fig. 2, fig. 2 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S101 in fig. 1 is completed. As shown in fig. 2, a first substrate 10 is provided, and a stop layer 20 and a first semiconductor layer 30 are sequentially stacked and formed on the first substrate 10.

The first substrate 10 serves as a carrier for supporting other film layers, such as the stop layer 20 and the first semiconductor layer 30.

In some embodiments, the stop layer 20 is used as a polish stop layer or an etch stop layer when the first substrate 10 is subsequently removed.

In some embodiments, the material of the first substrate 10 may be a semiconductor material, such as single crystal silicon, silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and the like.

In some embodiments, the material of the stop layer 20 may be an insulating material, such as silicon nitride or silicon oxide.

In some embodiments, the material of the first semiconductor layer 30 may be polysilicon.

In some embodiments, the insulating material may be sequentially deposited on the first substrate 10 by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. to form the stop layer 20 and to deposit polysilicon to form the first semiconductor layer 30.

In some embodiments, the first substrate 10 includes a third semiconductor layer, a dielectric layer and a fourth semiconductor layer (not shown) which are stacked, and the stop layer 20 is formed on a side of the third semiconductor layer away from the fourth semiconductor layer. In some embodiments, the material of the third semiconductor layer may be polysilicon, the material of the fourth semiconductor layer may be single crystal silicon, silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), etc., and the material of the dielectric layer may be an insulating material, such as silicon oxide, silicon oxynitride, etc.

Referring to fig. 3, fig. 3 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S102 in fig. 1 is completed. As shown in fig. 3, a stacked layer 40 is formed on a side of the first semiconductor layer 30 away from the stop layer 20, and the stacked layer 40 includes an insulating layer 401 and a sacrificial layer 402 which are alternately stacked.

In some embodiments, as shown in fig. 3, the stacked layer 40 includes at least one insulating layer 401 and at least one sacrificial layer 402, and the insulating layer 401 and the sacrificial layer 402 are alternately stacked and formed on the surface of the first semiconductor layer 30 away from the stop layer 20.

In some embodiments, forming the stacked layer 40 on a side of the first semiconductor layer 30 away from the stop layer 20 includes: forming the insulating layer 401 on a side of the first semiconductor layer 30 away from the stop layer 20; forming the sacrificial layer 402 on the side of the insulating layer 401 away from the first semiconductor layer 30; the insulating layer 401 and the sacrificial layer 402 are repeatedly and alternately formed to form the at least one insulating layer 401 and the at least one sacrificial layer 402 on the side of the first semiconductor layer 30 away from the stop layer 20.

In some embodiments, the material of the insulating layer 401 may be silicon oxide, silicon oxynitride, silicon oxycarbide, or the like.

In some embodiments, the material of the sacrificial layer 402 may be silicon nitride, amorphous carbon, polysilicon, etc.

In some embodiments, silicon oxide and silicon nitride may be alternately deposited on the surface of the first semiconductor layer 30 away from the stop layer 20 by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. to form the at least one insulating layer 401 and the at least one sacrificial layer 402.

In some embodiments, before the forming of the plurality of channel holes 50, the method of manufacturing the three-dimensional memory device further includes: and etching the stacked layer 40 to form at least one stacked structure 41 at intervals along a second direction, wherein an end 411 of the stacked structure 41 along the second direction is stepped, the second direction is perpendicular to the first direction, a schematic structure is shown in fig. 4, and fig. 4 is a schematic cross-sectional structure diagram of a three-dimensional memory device after the stacked structure 41 is formed.

In some embodiments, the stacked structure 41 may be formed by alternately etching and trimming the stacked layer 40 a plurality of times through an etch-trim process such that an end 411 of the stacked structure 41 in the second direction is stepped.

In some embodiments, after forming the stack structure 41, the method of manufacturing the three-dimensional memory device further includes: forming a first oxide layer 35 covering the first semiconductor layer 30 and the stack structure 41; forming a second oxide layer 36 filling the step region, the second oxide layer 36 being flush with a surface of the stack structure 41 away from the first semiconductor layer 30; and forming a third oxide layer 37, wherein the third oxide layer 37 covers the second oxide layer 36 and the stacked structure 41, and the schematic structure is as shown in fig. 4.

In some embodiments, the materials of the first oxide layer 35, the second oxide layer 36, and the third oxide layer 37 can all be silicon dioxide.

Referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S103 in fig. 1 is completed. As shown in fig. 5, a plurality of channel holes 50 are formed, each channel hole 50 penetrates through the stacked layer 40, the first semiconductor layer 30 and the stop layer 20 and extends into a portion of the first substrate 10, i.e., each channel hole 50 penetrates through the stacked structure 41, the first semiconductor layer 30 and the stop layer 20 and extends into a portion of the first substrate 10. Wherein each channel hole 50 penetrates the stacked structure 41 along the first direction.

In some embodiments, as shown in fig. 5, the aperture of the channel hole 50 increases in a direction from the stop layer 20 to the first semiconductor layer 30, i.e., the aperture of the channel hole 50 increases gradually in a direction from the stop layer 20 to the first semiconductor layer 30.

In some embodiments, the channel hole 50 may be cylindrical, and obviously, other cylindrical structures are also possible.

In some embodiments, the stack layer 40, the first semiconductor layer 30, the stop layer 20, and the first substrate 10 may be sequentially etched by a dry etching process (e.g., deep ion reactive etching) and/or a wet etching process to form the channel hole 50. Specifically, the three-dimensional memory device is placed in a reaction chamber of an ICP (inductively coupled plasma) device, an etching gas is introduced into the reaction chamber, and the etching rate of the stack layer 40 by the etching gas is increased in the direction from the stop layer 20 to the first semiconductor layer 30 by controlling the dry etching process, so that the aperture of the formed channel hole 50 can be increased in the direction from the stop layer 20 to the first semiconductor layer 30 in the same etching time.

Also, it can be understood that, when etching the stack layer 40, etching gas enters the stack layer 40 along the etched pores, and the density of the etching gas gradually increases in a direction from the first substrate 10 to the stack layer 40, so that a portion of the stack layer 40 far from the first substrate 10 is etched faster than a portion near the first substrate 10, and thus, the aperture of the channel hole 50 formed gradually increases in a direction far from the first substrate 10, that is, in a direction from the stop layer 20 to the first semiconductor layer 30.

Referring to fig. 6, fig. 6 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S104 in fig. 1 is completed. As shown in fig. 6, a channel structure 60 is formed in the channel hole 50, and a storage region is formed, the storage region including the channel structure 60, wherein the channel structure 60 includes a functional layer 61, a channel layer 62, a filling portion 63, and a first plug 64 and a second plug 65 respectively located at opposite ends of the filling portion 63 in the first direction, and the second plug 65 is closer to the first semiconductor layer 30 than the first plug 64. Wherein the cross-sectional structure of the step region is shown as A in FIG. 6, and the cross-sectional structure of the storage region is shown as B in FIG. 6. Where a is a cross-sectional view obtained by cutting the step region of the three-dimensional memory device along the first direction (e.g., a Z-axis direction in fig. 6) and the second direction (e.g., an X-axis direction in fig. 6), and B is a cross-sectional view obtained by cutting the memory region of the three-dimensional memory device along the first direction and a third direction (e.g., a Y-axis direction in fig. 6), the third direction being perpendicular to the first direction and the second direction, respectively.

In some embodiments, as shown in fig. 6, a surface of the first plug 64 away from the first semiconductor layer 30, a surface of the functional layer 61 away from the first semiconductor layer 30, and a surface of the channel layer 62 away from the first semiconductor layer 30 are flush.

In some embodiments, as shown in fig. 6, the functional layer 61 includes a blocking layer 611, a charge storage layer 612 and a tunneling layer 613 sequentially stacked on the inner wall of the channel hole 50. In some embodiments, the blocking layer 611 may be silicon dioxide, silicon oxynitride, etc., the charge storage layer 612 may be silicon nitride, silicon oxynitride, etc., and the tunneling layer 613 may be silicon dioxide, silicon oxynitride, etc.

In some embodiments, the channel layer 62 may be a polysilicon layer.

In some embodiments, the material of the filling portion 63 is an insulating material, for example, silicon dioxide. In some embodiments, the filling part 63 has an air gap inside. In other embodiments, the filler 63 may also be a solid structure, i.e., no air gap is present inside the filler 63.

In some embodiments, the material of the first plug 64 is a semiconductor material, such as polysilicon.

In some embodiments, the first plug 64 is used as a drain of the three-dimensional memory device.

In some embodiments, the material of the second plug 65 is a semiconductor material, such as polysilicon.

In some embodiments, the second plug 65 is used as a source of the three-dimensional memory device.

Referring to fig. 7 to 10 and fig. 6 together, fig. 7 is a flowchart illustrating a method of forming the channel structure 60, and fig. 8 to 10 and fig. 6 are schematic cross-sectional structures of the three-dimensional memory device corresponding to the steps in fig. 7. As shown in fig. 7, in some embodiments, the forming of the channel structure 60 in the channel hole 50 includes the following steps:

s1041: the functional layer 61 is formed on the side wall and the bottom wall of the channel hole 50, and the bottom wall of the channel hole 50 is an inner wall of one end of the channel hole 50 close to the first substrate 10, and the schematic structure is as shown in fig. 8.

S1042: depositing a semiconductor material in the channel hole 50 to form the channel layer 62 and the second plug 65, wherein the channel layer 62 covers a portion of the functional layer 61 located on the sidewall of the channel hole 50, and the second plug 65 covers a portion of the functional layer 61 located on the bottom wall of the channel hole 50, which is schematically shown in fig. 9.

S1043: the channel hole 50 is filled to form the filling portion 63, and the schematic structure is shown in fig. 10.

S1044: the first plug 64 is formed at one end of the filling part 63 far away from the second plug 65, and the schematic structure is shown in fig. 6.

In some embodiments, as shown in fig. 8, the functional layer 61 includes a blocking layer 611, a charge storage layer 612 and a tunneling layer 613 sequentially stacked on the inner wall of the channel hole 50. The functional layer 61 may be formed by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, for example, silicon dioxide may be deposited on the inner wall of the channel hole 50 by an atomic layer deposition process to form the blocking layer 611, silicon nitride may be deposited on the blocking layer 611 to form the charge storage layer 612, and silicon dioxide may be deposited on the charge storage layer 612 to form the tunneling layer 613. Wherein the inner wall of the channel hole 50 includes a sidewall and a bottom wall of the channel hole 50.

In some embodiments, a semiconductor material may be deposited within the channel hole 50 by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the channel layer 62 and the second plug 65. For example, polysilicon may be deposited on the functional layer 61 from the channel hole 50 by an atomic layer deposition process, specifically, the polysilicon deposition covers a portion of the functional layer 61 located on the sidewall of the channel hole 50 to form the channel layer 62, and the polysilicon deposition covers a portion of the functional layer 61 located on the bottom wall of the channel hole 50 to form the second plug 65.

In some embodiments, the aperture of the channel hole 50 increases in a direction from the stop layer 20 to the first semiconductor layer 30, that is, the aperture of a portion of the channel hole 50 closer to the first substrate 10 is smaller, that is, the bottom of the channel hole 50 is smaller than the aperture of other portions of the channel hole 50, when the semiconductor material is deposited in the channel hole 50, the thickness of the semiconductor material deposited on the bottom wall of the channel hole 50 is the same as the thickness of the semiconductor material deposited on the sidewall of the channel hole 50 due to the same deposition rate of the semiconductor material in the first direction and the second direction, and the bottom of the channel hole 50 is filled with the semiconductor material due to the smaller aperture of the bottom of the channel hole 50 compared to the aperture of other portions of the channel hole 50, that is, the bottom of the channel hole 50 is seamlessly filled with the semiconductor material to form the second plug 65, and the second plug 65 is formed by seamlessly filling the semiconductor material at the bottom of the channel hole 50, so that there is no void at the bottom of the channel structure 60, and therefore, during the subsequent process of removing the first substrate 10 and the stop layer 20, the channel structure 60 is not damaged, for example, when the first substrate 10 and the stop layer 20 are removed by using a chemical mechanical polishing process and/or an etching process, an abrasive and/or an etchant cannot enter the inside of the channel structure 60, and therefore, the channel structure 60 is not damaged, and the performance of the channel structure 60 is not affected. In addition, since the bottom of the channel hole 50 has a smaller hole diameter than the other portions of the channel hole 50, when the bottom of the channel hole 50 is filled with the semiconductor material to form the second plug 65, there is still a gap in the other portions of the channel hole 50, so that, while the second plug 65 is formed, a space is reserved for the subsequent formation of the filling portion 63 and the first plug 64.

In some embodiments, the filling portion 63 on the second plug 65 may be formed by filling silicon dioxide in the channel hole 50 through a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

In some embodiments, polysilicon may be deposited on an end of the filling portion 63 away from the second plug 65 by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the first plug 64.

In some embodiments, before the filling the channel hole 50 to form the filling part 63, the method for manufacturing a three-dimensional memory device further includes: the channel layer 62 is etched to thin the channel layer 62.

In some embodiments, the channel layer 62 is etched by a dry etching process, specifically, the three-dimensional memory device is placed in a reaction chamber of an ICP (inductively coupled plasma) apparatus, and an etching gas is introduced into the reaction chamber, and the etching gas selectively etches the channel layer 62 to thin the channel layer 62.

In this embodiment, the channel layer 62 is thinned by etching, so that it is avoided that the source and the drain of the three-dimensional memory device are not easily conducted through the channel layer 62 due to the excessive thickness of the channel layer 62. Wherein the thickness of the channel layer 62 is a dimension of the channel layer 62 in the second direction.

In some embodiments, before the removing the first substrate 10 and the stop layer 20, the method for manufacturing a three-dimensional memory device further includes: a plurality of gate line trenches 90 are formed, each gate line trench 90 penetrates through the stacked layer 40, the first semiconductor layer 30 and the stop layer 20, and extends into a portion of the first substrate 10, that is, each gate line trench 90 penetrates through the stacked structure 41, the first semiconductor layer 30 and the stop layer 20, and extends into a portion of the first substrate 10, wherein the gate line trenches 90 and the channel structures 60 are arranged at intervals, and a schematic structure is shown in fig. 11.

Wherein each gate line trench 90 penetrates through the stacked structure 41 along the first direction; the length direction of each gate wire slot 90 is parallel to the second direction; the plurality of gate line grooves 90 are arranged at intervals along the third direction.

In some embodiments, the stacked layer 40, the first semiconductor layer 30, the stop layer 20, and the first substrate 10 may be sequentially etched by a dry etching process (e.g., deep ion reactive etching) and/or a wet etching process to form the gate line trench 90.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes the steps of: the sacrificial layer 402 is removed from the gate line trenches 90 to form recesses 403, schematically illustrated in fig. 12.

In some embodiments, the sacrificial layer 402 may be removed by a wet etching process, specifically, the three-dimensional memory device is immersed in an etching groove, a hot phosphoric acid solution is contained in the etching groove, and the hot phosphoric acid solution selectively etches and removes the sacrificial layer 402 to form the groove 403, in this embodiment, the sacrificial layer 402 is made of silicon nitride.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes the steps of: the grooves 403 are filled to form a conductive layer 404, schematically shown in fig. 13.

In some embodiments, the conductive layer 404 includes a gate dielectric layer 4041, an adhesive layer 4042, and a gate 4043, which are sequentially stacked on the inner wall of the groove 403. In some embodiments, the material of the gate dielectric layer 4041 is an insulating material, such as silicon dioxide, silicon nitride, silicon oxynitride, or the like; the material of the adhesive layer 4042 is a conductive material, for example, titanium nitride or the like; the material of the gate 4043 may be a conductive material, such as tungsten, copper, cobalt, or the like. In some embodiments, the gate 4043 extends as a word line in the second direction and terminates at the stacked structure 41.

In some embodiments, the conductive layer 404 can be formed by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, for example, silicon nitride can be deposited from the gate line trench 90 on the inner wall of the recess 403 by an atomic layer deposition process to form the gate dielectric layer 4041, titanium nitride can be deposited on the gate dielectric layer 4041 to form the adhesion layer 4042, and tungsten can be deposited on the adhesion layer 4042 to form the gate 4043. In some embodiments, the gate dielectric layer 4041 is also formed along the sidewalls and bottom wall of the gate runner 90.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes the steps of: the gate line trenches 90 are filled to form a gate line gap structure 91.

In some embodiments, as shown in fig. 14, the gate line gap structure 91 includes a silicon dioxide layer 911 and a polysilicon portion 912, the silicon dioxide layer 911 covers the sidewall and the bottom wall of the gate line trench 90, and the polysilicon portion 912 is filled in the gate line trench 90. In this embodiment, the polysilicon portion is formed by filling polysilicon in the gate line groove 90, so that the mechanical performance of the gate line gap structure 91 can be adjusted, for example, the internal stress of the gate line gap structure 91 is reduced and the hardness of the gate line gap structure 91 is increased. In some embodiments, the gate line gap structure 91 may be formed by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

In other embodiments, the gate line trench 90 is filled with silicon dioxide to form the gate line gap structure 91.

In the three-dimensional memory device formed by using the method for manufacturing the three-dimensional memory device provided by the present application, no contact exists on the gate line gap structure 91, so that parasitic capacitance and leakage current are not introduced between the contact and the gate 4043.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes the steps of: a plurality of peripheral contacts 100, a plurality of word line local contacts 110, and a plurality of channel local contacts 120 are formed, wherein the plurality of peripheral contacts 100 are formed on a side of the first semiconductor layer 30 close to the stacked structure 41, the plurality of word line local contacts 110 are formed on a side of the end portion 411 of the stacked structure 41 far from the first semiconductor layer 30, and each channel local contact 120 is formed on a side of a first plug 64 far from the filling portion 63, as shown in fig. 15.

In some embodiments, forming the peripheral contact 100 includes: etching the third oxide layer 37, the second oxide layer 36, the first oxide layer 35, and the first semiconductor layer 30 to form a first contact hole, wherein the first contact hole penetrates through the second oxide layer 36 and the first oxide layer 35 and extends into a portion of the first semiconductor layer 30; and filling the first contact holes to form the peripheral contacts 100.

In some embodiments, the third oxide layer 37, the second oxide layer 36, the first oxide layer 35, and the first semiconductor layer 30 may be etched by a dry etching process and/or a wet etching process, for example, the three-dimensional memory device is placed in a reaction chamber of an ICP (inductively coupled plasma) apparatus, and different etching gases are sequentially introduced into the reaction chamber to selectively etch the third oxide layer 37, the second oxide layer 36, the first oxide layer 35, and the first semiconductor layer 30, respectively, so as to form the first contact hole.

In some embodiments, said filling said first contact hole to form said peripheral contact 100 comprises: forming a first titanium nitride layer covering the inner wall of the first contact hole; and filling the first contact hole to form a first conductive part. The material of the first conductive portion may be a metal material, such as tungsten, copper, cobalt, and the like.

In some embodiments, the first titanium nitride layer may be formed by depositing titanium nitride on the inner wall of the first contact hole through a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and depositing a metal material on the first titanium nitride layer to form the peripheral contact 100.

In some embodiments, forming the word line local contact 110 includes: etching the third oxide layer 37, the second oxide layer 36, the first oxide layer 35, the insulating layer 401, and the conductive layer 404 to form a second contact hole, wherein the second contact hole penetrates through the third oxide layer 37, the second oxide layer 36, the first oxide layer 35, and the insulating layer 401, and extends into a part of the conductive layer 404; and filling the second contact hole to form the word line local contact 110.

In some embodiments, said filling said second contact hole forms said word line local contact 110, comprising: forming a second titanium nitride layer covering the inner wall of the second contact hole; and filling the second contact hole to form a second conductive part. The material of the second conductive portion may be a metal material, such as tungsten, copper, cobalt, and the like.

In some embodiments, each word line local contact 110 is in contact with the gate 4043 of one of the conductive layers 404 for word line fan-out.

In some embodiments, forming the channel local contact 120 includes: etching the third oxide layer 37 to form a third contact hole exposing at least a portion of the first plug 64; and filling the third contact hole to form the word line local contact 110.

In some embodiments, said filling said third contact hole forms said word line local contact 110, comprising: forming a third titanium nitride layer, wherein the third titanium nitride layer covers the inner wall of the third contact hole; and filling the third contact hole to form a third conductive part. The material of the third conductive portion may be a metal material, such as tungsten, copper, cobalt, and the like.

In some embodiments, the channel local contact 120 may be electrically connected with a bit line contact of the three-dimensional memory device.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes: a first bonding layer 150 is formed on the side of the plurality of peripheral contacts 100, the plurality of word line local contacts 110, and the plurality of channel local contacts 120 away from the first semiconductor layer 30, and the first bonding layer 150 covers the plurality of peripheral contacts 100, the plurality of word line local contacts 110, and the plurality of channel local contacts 120, and the schematic structure is as shown in fig. 15.

In some embodiments, as shown in fig. 15, the first bonding layer 150 includes a plurality of first bonding contacts 1501 and a first isolation layer electrically isolating the plurality of first bonding contacts 1501, each first bonding contact 1501 making contact with a peripheral contact 100 or a wordline local contact 110 or a channel local contact 120.

In some embodiments, the material of the first bond contact 1501 can be a conductive material, such as tungsten, copper, aluminum, nickel silicide, and the like. The material of the first isolation layer may be an insulating material, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes the steps of: providing a peripheral circuit layer 130, and bonding one end of each of the plurality of peripheral contacts 100, the plurality of word line local contacts 110, and the plurality of channel local contacts 120, which is far away from the first semiconductor layer 30, to the peripheral circuit layer 130, respectively, which is schematically shown in fig. 16.

In some embodiments, as shown in fig. 16, the plurality of peripheral contacts 100, the plurality of wordline local contacts 110, and the plurality of channel local contacts 120 are bonded to the peripheral circuitry layer 130 through the first bonding layer 150, and the peripheral contacts 100, the channel local contacts 120, and the wordline local contacts 110 may be electrically connected to the peripheral circuitry layer 130 through the first bonding layer 150.

In some embodiments, the peripheral circuit layer 130 includes a second bonding layer 160, the second bonding layer 160 includes a plurality of second bonding contacts 1601 and a second isolation layer that electrically isolates the plurality of second bonding contacts 1601, the plurality of second bonding contacts 1601 being bonded to at least a portion of the plurality of first bonding contacts 1501.

In some embodiments, the second bonding contact 1601 and the first bonding contact 1501 are subjected to a plasma treatment, a wet treatment, and/or a thermal treatment prior to bonding the second bonding contact 1601 to the first bonding contact 1501, and the second bonding contact 1601 is aligned to bond with the first bonding contact 1501 in a face-to-face alignment to improve the bonding success rate.

In some embodiments, the peripheral circuit layer 130 may be digital, analog, and/or mixed signal control and sensing circuitry, such as page buffers, decoders, sense amplifiers, drivers, charge pumps, and the like.

In some embodiments, the peripheral circuit layer 130 is formed on a second substrate 140, as shown in fig. 16, the second substrate 140 is used to provide support for the peripheral circuit layer 130.

In the present application, by bonding the peripheral contact 100, the word line local contact 110, and the channel local contact 120 with the peripheral circuit layer 130, the semiconductor structure including the stack structure 41, the channel structure 60, the gate line gap structure 91, the peripheral contact 100, the word line local contact 110, and the channel local contact 120 can transmit electrical signals with the peripheral circuit layer 130.

Referring to fig. 17, fig. 17 is a schematic cross-sectional structure diagram of the three-dimensional memory device obtained after step S105 in fig. 1 is completed. As shown in fig. 17, the first substrate 10 and the stop layer 20 are removed to expose the second plug 65.

In some embodiments, the removing the first substrate 10 includes: the first substrate 10 is removed using a wet etching process and/or a dry etching process to expose the stop layer 20 and the channel structure 60.

In some embodiments, the removing the stop layer 20 includes: the stop layer 20 is removed by polishing using a first chemical mechanical polishing process to expose the second plug 65 and the first semiconductor layer 30.

In the present application, when the stop layer 20 is removed by polishing using the first chemical mechanical polishing process, the stop layer 20, the portion of the blocking layer 611 protruding from the first semiconductor layer 30, the portion of the charge storage layer 612 protruding from the first semiconductor layer 30, the portion of the tunneling layer 613 protruding from the first semiconductor layer 30, and the portion of the second plug 65 protruding from the first semiconductor layer 30 can be removed at the same time, and it is not necessary to sequentially remove the portion of the blocking layer 611 protruding from the first semiconductor layer 30, the portion of the charge storage layer 612 protruding from the first semiconductor layer 30, the portion of the tunneling layer 613 protruding from the first semiconductor layer 30, and the portion of the second plug 65 protruding from the first semiconductor layer 30 through other process steps, so that the process flow is simplified, the manufacturing cost is saved, and the production efficiency of the three-dimensional memory device can be improved.

In the present application, the stop layer 20 is removed by the first chemical mechanical polishing process, so as to expose the second plug 65, and the second plug 65 with a flat surface can be obtained, so that the second semiconductor layer formed subsequently can be in good contact with the second plug 65, and the second plug 65 can be electrically connected with the source contact formed subsequently more stably through the second semiconductor layer.

In some embodiments, removing the first substrate 10 using an etching process may include removing the first substrate 10 using a wet etching process and/or a dry etching process, for example, removing the first substrate 10 using a wet etching process, soaking the three-dimensional memory device in a tetramethylammonium hydroxide solution, and selectively etching only the first substrate 10 using tetramethylammonium hydroxide; or, placing the three-dimensional memory device in a reaction chamber of an ICP (inductively coupled plasma) device, introducing a fluorine-containing gas into the reaction chamber, and etching the first substrate 10 by the fluorine-containing gas to remove the first substrate 10.

In some embodiments, the stop layer 20 is removed by a first chemical mechanical polishing process, specifically, a polishing table is used for polishing, the three-dimensional storage device is fixed on the polishing head, the polishing table is in contact with the stop layer 20, the liquid supply device is used for supplying a first polishing liquid to the polishing table, and the polishing table is used for polishing the stop layer 20 by controlling the relative motion of the polishing table and the polishing head so that the polishing table and the three-dimensional storage device move relatively. The first polishing slurry selectively etches only the stop layer 20, and the polishing process is stopped at the first semiconductor layer 30.

In some embodiments, the first abrasive liquid may include silica, an organic or inorganic acid, and water, wherein the organic acid may include at least one of acetic acid, propionic acid, butyric acid, citric acid, tartaric acid, oxalic acid, maleic acid, and phthalic acid, and the inorganic acid includes at least one of hydrochloric acid, nitric acid, and phosphoric acid; or the first polishing liquid may include cerium oxide, a water-soluble organic polymer, and water, wherein the water-soluble organic polymer has a carboxylic acid group or a carboxylate group.

In other embodiments, the stop layer 20 may also be removed using a dry etch process. For example, the three-dimensional memory device is placed in a reaction chamber of an ICP (inductively coupled plasma) apparatus, and a fluorine-containing gas is introduced into the reaction chamber, and the fluorine-containing gas selectively etches the stop layer 20, so that the stop layer 20 is removed.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes: the second plug 65 is ion-doped. In an alternative embodiment, the second plug 65 is doped with N-type ions. For example, the second plug 65 is doped with an N-type dopant containing phosphorus (P) or arsenic (As). In some embodiments, the second plug 65 and the first semiconductor layer 30 are ion-doped at the same time.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes: forming a second semiconductor layer on a side of the first semiconductor layer 30 away from the stacked structure, the second semiconductor layer covering the second plug 65; and forming a plurality of source contacts on a side of the second semiconductor layer away from the first semiconductor layer 30, each source contact being opposite a second plug 65.

The following is more specifically described with reference to fig. 18 and 19.

Referring to fig. 18, fig. 18 is a schematic cross-sectional structure diagram of a three-dimensional memory device obtained after forming the second semiconductor layer 70. As shown in fig. 18, a second semiconductor layer 70 is formed on a side of the first semiconductor layer 30 away from the stacked structure 41, and the second semiconductor layer 70 covers the second plug 65.

In some embodiments, the material of the second semiconductor layer 70 may be polysilicon or ion-doped polysilicon.

In some embodiments, a semiconductor material may be deposited on a side of the first semiconductor layer 30 away from the stacked structure 41 by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the second semiconductor layer 70.

In some embodiments, after forming the second semiconductor layer 70, the method of manufacturing the three-dimensional memory device further includes: the second semiconductor layer 70 is ion doped, and in an alternative embodiment, the second semiconductor layer 70 is N-type ion doped. For example, an N-type dopant containing phosphorus (P) or arsenic (As) is doped to the second semiconductor layer 70.

In some embodiments, the ion doping the second semiconductor layer 70 includes: the second semiconductor layer 70 is ion-doped using an ion implantation process.

In some embodiments, after ion doping the second semiconductor layer 70, the method of manufacturing the three-dimensional memory device further includes: the second semiconductor layer 70 is annealed using a Rapid Thermal Annealing (RTA) process to remove lattice damage caused by the ion implantation process and electrically activate the doped ions. Illustratively, the three-dimensional memory device is placed in a chamber of an RTA apparatus, and an annealing temperature and an annealing time are set, wherein the annealing temperature may have a value of 700 to 1000 ℃ and the annealing time may have a value of 5 seconds to 5 hours.

In some embodiments, the material of the first semiconductor layer 30 and the material of the second semiconductor layer 70 are the same material (e.g., polysilicon), and the second semiconductor layer 70 is formed on the first semiconductor layer 30, so that the bonding strength between the second semiconductor layer 70 and the first semiconductor layer 30 is high, and thus, the performance of the three-dimensional memory device can be ensured.

In the embodiment of the present application, by forming the stacked structure 41 on the first semiconductor layer 30 and then forming the second semiconductor layer 70 on the side of the first semiconductor layer 30 away from the stacked structure 41, the second semiconductor layer 70 can be prevented from directly contacting the insulating layer 401 of the stacked structure 41, and thus the second semiconductor layer 70 can be prevented from being separated from the insulating layer 401 when the annealing process is performed on the second semiconductor layer 70 due to the low bonding degree of the second semiconductor layer 70 and the insulating layer 401. Since the insulating layer 401 of the stacked structure 41 is formed on the first semiconductor layer 30, since the manufacturing processes of the film layer structure (the channel structure 60, the gate line gap structure 90, the peripheral contact 100, the word line local contact 110, the channel local contact 120, etc.) are performed on the three-dimensional memory device multiple times before the second semiconductor layer 70 is formed, in these manufacturing processes, the degree of bonding between the first semiconductor layer 30 and the insulating layer 401 is continuously increased along with the progress of different manufacturing processes, so that the bonding between the first semiconductor layer 30 and the insulating layer 401 is tight, and when the second semiconductor layer 70 is annealed, the first semiconductor layer 30 and the insulating layer 401 are not separated, thereby ensuring the performance and quality of the formed three-dimensional memory device.

Referring to fig. 19, fig. 19 is a schematic cross-sectional structure diagram of a three-dimensional memory device obtained after forming the source contact 80. As shown in fig. 19, a plurality of source contacts 80 are formed on a side of the second semiconductor layer 70 away from the first semiconductor layer 30, and each source contact 80 is opposite to a second plug 65.

In the method for manufacturing the three-dimensional memory device provided in the present application, the gate line gap structure 91 and the source contact 80 are formed on two opposite sides of the second semiconductor layer 70, respectively, so that the source contact 80 is far away from the gate line gap structure 91, and thus, the three-dimensional memory device is formed without introducing parasitic capacitance and leakage current between the source contact 80 and the gate 4043.

In some embodiments, forming the source contact 80 includes: forming an ILD layer (inter-metal dielectric) 170 on a side of the second semiconductor layer 70 away from the first semiconductor layer 30; etching away a portion of the ILD layer (intermetal dielectric layer) 170 facing the second plug 65 to form a source contact opening 81, the source contact opening 81 exposing a portion of the second semiconductor layer 70 facing the second plug 65; the source contact opening 81 is filled to form the source contact 80, schematically shown in fig. 20.

In some embodiments, the source contact opening 81 may be formed by a photolithography patterning process and an etching process, specifically, a photoresist is coated on a side of the ILD layer 170 away from the second semiconductor layer 70 to form a protective layer, a portion of the protective layer facing the second plug 65 is removed by mask exposure and development, a portion of the ILD layer 170 facing the second plug 65 is removed by a dry etching process or a wet etching process, the source contact opening 81 is formed in the ILD layer 170, and the protective layer is removed by a concentrated sulfuric acid wet etching process.

In some embodiments, the material of the ILD layer 170 may be an insulating material, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like.

In some embodiments, the filling the source contact opening 81 to form the source contact 80 includes: forming a source contact adhesion layer covering an inner wall of the source contact opening 81; and filling the source contact opening 81 to form a source contact conductive portion. The material of the source contact adhesion layer may be titanium nitride, and the material of the source contact conductive portion may be a metal material, such as tungsten, copper, cobalt, or the like.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes: a plurality of through silicon contacts 180 (TSCs) are formed, the through silicon contacts 180 extending through the second semiconductor layer 70 and contacting an end of the peripheral contact 100 remote from the first bonding contact 1501, as schematically illustrated in fig. 19.

In some embodiments, forming the through-silicon contact 180 includes: etching away a portion of the ILD layer 170 facing the peripheral contact 100 to form a through silicon contact opening 1801, the through silicon contact opening 1801 exposing the peripheral contact 100, as shown in fig. 20; the through silicon contact opening 1801 is filled to form the through silicon contact 180, and the schematic structure is shown in fig. 19.

In some embodiments, said filling said through-silicon contact openings 1801 to form said through-silicon contacts 180 comprises: forming a spacer layer 190, said spacer layer 190 covering the inner walls of said through silicon contact opening 1801 and exposing said peripheral contact 100; forming a through silicon contact adhesion layer on the spacer layer 190; and filling the through-silicon contact opening 1801 to form a through-silicon contact conductive portion, the schematic structure is as shown in fig. 19. The material of the spacer layer 190 is an insulating material, such as silicon dioxide, silicon oxynitride, etc., the material of the through-silicon contact adhesion layer may be titanium nitride, and the material of the through-silicon contact conductive portion may be a metal material, such as tungsten, copper, cobalt, etc.

In some embodiments, the ILD layer 170 is flush with a surface away from the second semiconductor layer 70, a surface of the through silicon contact 180 away from the peripheral contact 100, and a surface of the source contact 80 away from the second semiconductor layer 70.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes: an interconnect layer 200 is formed on a side of the ILD layer 170 away from the second semiconductor layer 70, the interconnect layer 200 covers the source contact 80 and the through silicon contact 180, the interconnect layer 200 includes a redistribution layer 2001 and a passivation layer 2002 sequentially stacked on the ILD layer 170, and the schematic structure is as shown in fig. 21.

In some embodiments, the material of the redistribution layer 2001 may be a conductive material, such as tungsten, copper, cobalt, aluminum, etc., and the material of the passivation layer 2002 may be an insulating material, such as silicon dioxide, silicon nitride, silicon oxynitride, etc. The passivation layer 2002 serves to passivate and protect the three-dimensional memory device.

In some embodiments, the interconnect layer 200 is used for pad extraction to enable transmission of electrical signals between the three-dimensional memory device and external circuitry.

In some embodiments, the method of manufacturing a three-dimensional memory device further includes: portions of the passivation layer 2002 facing at least one of the through-silicon contacts 180 are etched away, exposing portions of the redistribution layer 2001 in contact with the through-silicon contacts 180 to form contact pads 210. The peripheral contact 100, the through silicon contact 180, and the first bonding layer 150 electrically connect the contact pad 210 for pad extraction to the peripheral circuit layer 130.

Referring to fig. 22, fig. 22 is a schematic cross-sectional structure diagram of a three-dimensional memory device 300 according to an embodiment of the present disclosure. As shown in fig. 22, the three-dimensional memory device 300 includes a first semiconductor layer 30, at least one stack structure 41, a plurality of channel structures 60, a second semiconductor layer 70, and a plurality of source contacts 80. The plurality of stacked structures 41 are located on the first semiconductor layer 30, and the stacked structures 41 include insulating layers 401 and conductive layers 404 that are alternately stacked. Each channel structure 60 penetrates through the stacked structure 41 and the first semiconductor layer 30, wherein the channel structure 60 includes a functional layer 61, a channel layer 62, a filling portion 63, and a first plug 64 and a second plug 65 respectively located at two opposite ends of the filling portion 63 along a first direction, the second plug 65 is closer to the first semiconductor layer 30 than the first plug 64, and the first direction is a stacking direction (e.g., a Z-axis direction in fig. 22) of the insulating layer 401 and the conductive layer 404.

In some embodiments, as shown in fig. 22, an end 411 of the stacked structure 41 in a second direction, which is perpendicular to the first direction, is stepped. Wherein the three-dimensional memory device 300 includes a memory region including the plurality of channel structures 60, and a cross-sectional structure of the memory region is shown as B in fig. 22. The three-dimensional memory device 300 includes a stepped region including an end 411 of the stack structure 41 in the second direction, and a cross-sectional structure of the stepped region is shown as a in fig. 22. Where a is a cross-sectional view obtained by cutting the step region of the three-dimensional memory device along the first direction (e.g., a Z-axis direction in fig. 6) and the second direction (e.g., an X-axis direction in fig. 6), and B is a cross-sectional view obtained by cutting the memory region of the three-dimensional memory device along the first direction and a third direction (e.g., a Y-axis direction in fig. 6), the third direction being perpendicular to the first direction and the second direction, respectively.

The three-dimensional memory device 300 further includes a plurality of gate line gap structures 91, a plurality of peripheral contacts 100, a plurality of word line local contacts 110, a plurality of channel local contacts 120 and a peripheral circuit layer 130, wherein the plurality of gate line gap structures 91 penetrate the stack structure 41 and the first semiconductor layer 30, and the gate line gap structure 91 is spaced apart from the channel structure 60, the plurality of peripheral contacts 100 are formed on a side of the first semiconductor layer 30 adjacent to the stacked structure 41, the plurality of word line local contacts 110 are formed on a side of the end 411 of the stacked structure 41 away from the first semiconductor layer 30, each channel local contact 120 is formed on a side of a first plug 64 away from the fill 63, the ends of the plurality of peripheral contacts 100, the plurality of word line local contacts 110, and the plurality of channel local contacts 120, which are away from the first semiconductor layer 30, are respectively bonded to the peripheral circuit layer 130.

Wherein each gate line gap structure 91 penetrates through the stacked structure 41 along the first direction; the length direction of each gate line gap structure 91 is parallel to the second direction; the plurality of gate line gap structures 91 are arranged at intervals along the third direction.

In some embodiments, as shown in fig. 22, the gate line gap structure 91 includes a silicon dioxide layer 911 and a polysilicon portion 912, and the silicon dioxide layer 911 surrounds the polysilicon portion 912.

In other embodiments, the gate line gap structure 91 includes only a silicon dioxide portion.

In some embodiments, as shown in fig. 22, the three-dimensional memory device 300 further includes a first bonding layer 150 and a second bonding layer 160, the first bonding layer 150 is located on a side of the plurality of peripheral contacts 100, the plurality of word line local contacts 110, and the plurality of channel local contacts 120 away from the first semiconductor layer 30, the first bonding layer 150 is in bonding connection with the second bonding layer 160, and the plurality of peripheral contacts 100, the plurality of word line local contacts 110, and the plurality of channel local contacts 120 are electrically connected with the peripheral circuit layer 130 through the first bonding layer 150 and the second bonding layer 160.

In some embodiments, as shown in fig. 22, the first bonding layer 150 includes a plurality of first bonding contacts 1501, the second bonding layer 160 includes a plurality of second bonding contacts 1601, and the plurality of second bonding contacts 1601 are bonded to at least some of the plurality of first bonding contacts 1501.

In some embodiments, as shown in fig. 22, the three-dimensional memory device 300 further includes a first oxide layer 35, a second oxide layer 36, and a third oxide layer 37, wherein the first oxide layer 35 covers the first semiconductor layer 30 and the stack structures 41, the second oxide layer 36 fills a space region between two adjacent stack structures 41, and the third oxide layer 37 covers the second oxide layer 36.

In some embodiments, as shown in fig. 22, the three-dimensional memory device 300 further includes the second semiconductor layer 70 and a plurality of source contacts 80. The second semiconductor layer 70 is located on a side of the first semiconductor layer 30 away from the stacked structure 41, and the second semiconductor layer 70 covers the second plug 65. The source contacts 80 are located on a side of the second semiconductor layer 70 away from the first semiconductor layer 30, and each source contact 80 is directly opposite to a second plug 65.

In some embodiments, as shown in fig. 21, the three-dimensional memory device 300 further includes a second substrate 140 for supporting the peripheral circuit layer 130, a through silicon contact 180, a spacer layer 190, a contact pad 210, an ILD layer 170, and an interconnect layer 200. The interconnect layer 200 includes a redistribution layer 2001 and a passivation layer 2002.

In the three-dimensional memory device 300 provided by the present application, the channel structure 60 formed in the channel hole 50 includes the second plug 65, and the second plug 65 completely fills the end of the channel hole 50 located in the first substrate 10, so that the channel structure 60 is not damaged during the process of removing the first substrate 10 and the stop layer 20, and thus, the performance of the three-dimensional memory device 300 is not affected. In addition, in the three-dimensional memory device 300 disclosed in the present application, the gate line gap structure 91 and the source contact 80 are respectively located at two opposite sides of the second semiconductor layer 70, so that the source contact 80 is far away from the gate line gap structure 91, and thus, parasitic capacitance and leakage current are not introduced between the source contact 80 and the gate electrode 4043.

The three-dimensional memory device 300 provided by the above-mentioned embodiments corresponds to the manufacturing method of the three-dimensional memory device described above, and the relevant points can be referred to each other.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The foregoing is an implementation of the embodiments of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiments of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.

Claims

1. A method for manufacturing a three-dimensional memory device, the method comprising:

providing a first substrate, and sequentially laminating a stop layer and a first semiconductor layer on the first substrate;

forming a stacked layer on one side of the first semiconductor layer far away from the stop layer, wherein the stacked layer comprises insulating layers and sacrificial layers which are alternately stacked;

forming a plurality of channel holes, wherein each channel hole penetrates through the stacked layer, the first semiconductor layer and the stop layer and extends into a part of the first substrate;

forming a channel structure in the channel hole, wherein the channel structure comprises a functional layer, a channel layer, a filling part, and a first plug and a second plug respectively located at two opposite ends of the filling part along a first direction, the second plug is closer to the first semiconductor layer than the first plug, the second plug extends across a surface of the stop layer away from the first substrate, and the first direction is a stacking direction of the insulating layer and the sacrificial layer; and

and removing the first substrate and the stop layer to expose the second plug.

2. The method of claim 1, wherein forming a channel structure in the channel hole comprises:

forming the functional layer on the side wall and the bottom wall of the channel hole, wherein the bottom wall of the channel hole is the inner wall of one end, close to the first substrate, of the channel hole;

depositing a semiconductor material in the channel hole to form the channel layer covering a portion of the functional layer on the sidewall of the channel hole and the second plug covering a portion of the functional layer on the bottom wall of the channel hole;

filling the channel hole to form the filling part; and

and forming the first plug at one end of the filling part far away from the second plug.

3. The method of claim 1, wherein an aperture of the channel hole increases in a direction from the stop layer to the first semiconductor layer.

4. The method of claim 1, wherein the material of the second plug is polysilicon.

5. The method of claim 1, wherein the stop layer is made of an insulating material.

6. The method of manufacturing a three-dimensional memory device according to claim 1, wherein before forming the second semiconductor layer, the method further comprises:

and carrying out ion doping on the second plug.

7. The method of claim 1, wherein the removing the stop layer comprises:

and removing the stop layer by grinding by using a first chemical mechanical grinding process.

8. The method of fabricating a three-dimensional memory device according to claim 1, wherein prior to said forming the plurality of channel holes, the method further comprises:

and etching the stacked layers to form at least one stacked structure at intervals along a second direction, wherein the end part of the stacked structure along the second direction is stepped, and the second direction is perpendicular to the first direction.

9. The method of fabricating a three-dimensional memory device of claim 8, wherein prior to said removing the first substrate and the stop layer, the method further comprises:

forming a plurality of gate wire grooves, wherein each gate wire groove penetrates through the stacking layer, the first semiconductor layer and the stop layer and extends into part of the first substrate, and the gate wire grooves and the channel structures are arranged at intervals;

removing the sacrificial layer from the gate line groove to form a groove;

filling the groove to form a conductive layer;

filling the grid line grooves to form a grid line gap structure;

forming a plurality of peripheral contacts, a plurality of word line local contacts and a plurality of channel local contacts, wherein the peripheral contacts are formed on one side of the first semiconductor layer close to the stacked structure, the word line local contacts are formed on one side of the end part of the stacked structure far away from the first semiconductor layer, and each channel local contact is formed on one side of a first plug far away from the filling part;

providing a peripheral circuit layer; and

and bonding one ends of the plurality of peripheral contacts, the plurality of word line local contacts and the plurality of channel local contacts, which are far away from the first semiconductor layer, with the peripheral circuit layer respectively.

10. The method of fabricating a three-dimensional memory device of claim 9, wherein after said removing the first substrate and the stop layer, the method further comprises:

forming a second semiconductor layer on one side of the first semiconductor layer far away from the stacked layer, wherein the second semiconductor layer covers the second plug; and

and forming a plurality of source contacts on one side of the second semiconductor layer far away from the first semiconductor layer, wherein each source contact is opposite to a second plug.

11. A three-dimensional memory device, comprising:

a first semiconductor layer;

at least one stacked structure on the first semiconductor layer, the stacked structure including insulating layers and conductive layers alternately stacked; and

each channel structure penetrates through the stacked structure and the first semiconductor layer, wherein each channel structure comprises a functional layer, a channel layer, a filling part, and a first plug and a second plug which are respectively located at two opposite ends of the filling part along a first direction, the functional layer, the channel layer, the filling part and the first plug are stacked in sequence, the second plug is close to the first semiconductor layer compared with the first plug, and the first direction is the stacking direction of the insulating layer and the conducting layer.

12. The three-dimensional memory device of claim 10, wherein an end of the stacked structure along a second direction is stepped, the second direction is perpendicular to the first direction, the three-dimensional memory device further comprises a plurality of gate line gap structures, a plurality of peripheral contacts, a plurality of word line local contacts, a plurality of channel local contacts, a peripheral circuit layer, a second semiconductor layer, and a plurality of source contacts, wherein the plurality of gate line gap structures penetrate through the stacked structure and the first semiconductor layer and are spaced apart from the channel structures, the plurality of peripheral contacts are formed on a side of the first semiconductor layer close to the stacked structure, the plurality of word line local contacts are formed on a side of the end of the stacked structure far from the first semiconductor layer, and each channel local contact is formed on a side of a first plug far from the filling portion, the peripheral contacts, the word line local contacts and the channel local contacts are respectively bonded with the peripheral circuit layer at one end far away from the first semiconductor layer, the second semiconductor layer is positioned at one side of the first semiconductor layer far away from the stacked structure, the second semiconductor layer covers the second plug, the source contacts are positioned at one side of the second semiconductor layer far away from the first semiconductor layer, and each source contact is opposite to one second plug.