CN101763887B - Reading device of storage unit and reading method thereof - Google Patents
Reading device of storage unit and reading method thereof Download PDFInfo
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- CN101763887B CN101763887B CN 200910198986 CN200910198986A CN101763887B CN 101763887 B CN101763887 B CN 101763887B CN 200910198986 CN200910198986 CN 200910198986 CN 200910198986 A CN200910198986 A CN 200910198986A CN 101763887 B CN101763887 B CN 101763887B
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Abstract
The invention relates to a reading device of a storage unit and a reading method thereof, which are used for reading the data stored in a selected storage unit in a storage. The storage unit outputs unit current as the input of the reading device of the storage unit according to the storage unit; the unit current finally appears as output current of a reading and amplifying circuit by a constant current source circuit under the feedback of a comparator; and compared with a reference current, the data stored in the storage unit can be judged and output. The unit current serves as the input/output comparison object of the reading device, thereby improving the reading speed and being more applicable for the storages such as a high-speed flash memory; meanwhile, the drain voltage of a transistor in the constant current source circuit can be clamped down to be a reference voltage by the comparator, so that the reading device can work in a normal state in a linear zone, thereby widening the voltage range of a working power supply of the reading device of the storage unit and greatly improving the data reading accuracy in the actual data reading process.
Description
Technical field
The invention belongs to the semiconductor memory field, relate to reading of semiconductor memory cell data, be specifically related to a kind of reading device and read method of memory cell.
Background technology
Semiconductor memory generally includes many word line (Word-line, WL), bit line (Bit-line, BL) and the storage unit (Memory-cell that is positioned at each intersection point configuration of word line and bit line, MC), each storage unit is in order to recording the data of a byte, realizes output to data that storer is stored by reading data on selected storage unit.Because memory array is classified the virtual earth array structure as, do not have real common source in this array, therefore, read in process in storage unit, usually will be positioned at the bit line ground connection that the storage unit on side, selected unit connects, be considered as ground wire.
US Patent No. 6529412B1 provides a kind of source read method, and Fig. 1 is the source voltage terminal memory cell data read method circuit diagram that this patent provides.As shown in Figure 1, sensing circuit 100 is the voltage sensing circuit, the electric current I that flows through on selected storage unit
Cell110 are converted to memory cell voltages V via current-voltage converter 130
CellAfter 150, be input to sensor amplifier (Sense Amplifier, S.A.) 170 end of oppisite phase, and after reference current Iref 120 is converted to reference voltage Vref 160 via current-voltage converter 140, be input to the in-phase end of sensor amplifier 170, the output of sensor amplifier 170 is the sense data 180 of this storage unit, and wherein, current-voltage converter 130,140 is integrated in pre-amplification circuit 705.Yet, adopt the voltage reading access method will bring larger time-delay, make the memory data reading speed slower, be not suitable for the high speed storeies such as NOR flash memory system.
Be compared to the voltage reading access method, the method that directly reads selected memory cell current has higher speed, greatly reduces the time of reading.
Fig. 2 is drain terminal electric current read method circuit diagram commonly used in prior art.As shown in Figure 2, memory array comprises many word line WL, bit line BL and is positioned at word line WL and the storage unit of bit line BL crossover location, wherein, the control gate that the word line will be positioned at the storage unit MOS transistor of delegation links together, and the source electrode that bit line will be positioned at the storage unit MOS transistor of same row links together.As shown in Figure 2, when selecting the data of reading cells A, gating control signal YA, YB are high level, gate transistor MC1, MC2 are in conducting state, storage unit A is selected, at this moment, word line WL＜m that storage unit A is expert at〉be placed in noble potential, and other word lines WL is placed in electronegative potential, and storage unit A is in conducting state.When initial, all bit line BL all are placed in reference voltage Vref, and this reference voltage Vref value is about 1.2V, subsequently, bit line BL＜k that the source S of storage unit A connects〉ground connection, bit line BL＜k+1 that its drain D connects〉connection reading device 200, other bit lines BL is all unsettled.At this moment, bit line BL＜k+1〉on electric current be the electric current I of storage unit A
A, under the retroactive effect of comparer I1, transistor Mi drain terminal D voltage is clamped down on is reference voltage Vref, cell current I
AAs the input current of reading amplifying circuit 201, be input in the constant-current source circuit that is formed by transistor M3, M4 via transistor Mi, and produce the equal image current I of current value with it on transistor M4
4, this electric current 210 compares with reference current Iref, during greater than reference current Iref, reads " 1 ", if current value less than reference current Iref, is read " 0 " when current value.
Higher than the voltage reading access method, then, in the method, data reading circuit connects the bit line of selected storage unit drain terminal from the data reading speed of drain terminal electric current read method, reading circuit and read the required reference voltage Vref of amplifying circuit and pre-charge voltage V
DDMagnitude of voltage is very approaching, but this makes the operating voltage range of reading transistor M3, M4 in amplifying circuit 201 very little, easily causes the inaccurate of reading numerical values.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of memory cell reading device, quickening memory cell data reading speed, but and increase working power voltage scope.
For solving the problems of the technologies described above, memory cell reading device provided by the invention is in order to the data of selected cell stores in read memory, this storage unit is according to the data output unit electric current of storing, and the output current of this storage unit source is as the input of memory cell reading device of the present invention, under the retroactive effect of the first comparer and the second comparer, show as the 3rd transistorized electric current, and compare with reference current, judge according to this and export the data that storage unit is stored.
Concretely, memory cell reading device provided by the invention comprises:
Reference unit is in order to provide reference voltage and reference current;
Read amplifying circuit, comprise the first constant-current source circuit and the first transistor, wherein: the first constant-current source circuit comprises transistor seconds and the 3rd transistor, and the source of the first transistor is connected with the source of transistor seconds;
The second constant-current source circuit comprises the 4th transistor and the 5th transistor;
The first comparer in order to receiving reference voltage, and is all clamped down on the first transistor and the 5th transistorized drain voltage and is reference voltage;
The second comparer in order to receiving reference voltage, and is clamped down on the 4th transistorized drain voltage and is reference voltage.
In memory cell reading device provided by the invention, the first transistor, the 4th transistor, the 5th transistor are nmos pass transistor, transistor seconds, the 3rd transistor are the PMOS transistor, and four, the 5th equal ground connection of transistorized source and second, third transistorized drain terminal all connect supply voltage, in addition, in this memory cell reading device, the first comparer can be read amplifying circuit by multichannel and share.
The present invention also provides a kind of memory cell read method, the above-mentioned memory cell reading device that provides is provided the method, in order to the data of a certain storage unit in read memory, this storage unit is according to data output one cell current of storing, and the method comprises:
Receive this cell current;
Receive reference current;
This cell current is read amplifying circuit through the constant-current source circuit input;
This cell current shows as the output of sensor amplifier, and compares with reference current, the data that this storage unit of judgement output is according to this stored.
In memory cell read method provided by the invention, reference current is provided by a reference unit, this reference unit is also exported a reference voltage simultaneously, this reference voltage range is 0.10V ~ 0.80V, and the interconnective two transistor drain voltage of grid of composition constant-current source circuit is all clamped down under the retroactive effect of comparer is this reference voltage.
Technique effect of the present invention is that the output unit electric current of employing storage unit has greatly reduced data and read the time as input and the output comparison other of reading device, improves reading speed, is more suitable for the application of the memory devices such as high speed flash memory.Meanwhile, in memory cell reading device provided by the invention and read method, adopt comparer that the 4th transistor and the 5th transistorized drain voltage are clamped down on and be reference voltage, make it can enter normal operating conditions at linear zone, but increased the working power voltage scope of memory cell reading device, read in process in real data, greatly improved the accuracy that data read.
Description of drawings
Fig. 1 is source voltage terminal memory cell data read method circuit diagram;
Fig. 2 is drain terminal current storage device method for reading data circuit diagram;
Fig. 3 a is source current memory cell data reading device working circuit diagram provided by the invention;
Fig. 3 b is memory cell reading device amplification circuit diagram provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 3 a is the storage reading apparatus working circuit diagram according to source current memory cell data reading device provided by the invention one better embodiment.
Memory cell reading device 300 is in order to the data of selected cell stores in read memory.In this embodiment, selected storage unit A is according to the data output unit electric current I of storing
A, and the output current I of this storage unit A source S
AElectric current input as memory cell reading device 300 under the retroactive effect of the first comparer I1 and the second comparer I2, via the second constant current source electric current 320, shows as the electric current I of the 3rd transistor M3
3, and compare with reference current Iref, judge according to this and export the data DOUT that storage unit A is stored.
As shown in Fig. 3 a, memory construction comprises many word line WL and bit line BL, and is provided with storage unit at word line WL and bit line BL crossover location.Every word line WL connects the storage unit control gate that is positioned at same row, and bit line BL connects the storage unit source/drain terminal that is positioned at same row.
Memory cell reading device 300 amplification circuit diagrams that Fig. 3 b provides for this embodiment.
As shown in Fig. 3 b, the memory cell reading device 300 that this embodiment provides comprises: reference unit 301, read amplifying circuit 302, the second constant-current source circuit 320, the first comparer I1 and the second comparer I2.Wherein, reference unit 301 is in order to provide reference voltage Vref and reference current Iref; The second constant-current source circuit 320 comprises the 4th transistor M4 and the 5th transistor M5, in order to the electric current I with storage unit A
ABe converted to the image current I of the 5th transistor M5
5Read amplifying circuit 302 and comprise the first constant-current source circuit 310 and the first transistor Mi, wherein: the first constant-current source circuit 310 comprises transistor seconds M2 and the 3rd transistor M3, and the source S of the first transistor Mi is connected with the source S of transistor seconds M2; The first comparer I1 in-phase input end is in order to receive reference voltage Vref, inverting input is in order to connect the drain terminal D of the 5th transistor M5 and the first transistor Mi, the drain voltage of the 5th transistor M5 and the first transistor Mi is all clamped down on be reference voltage Vref, the control gate G of its output terminal connection the first transistor Mi; The second comparer I2 in-phase input end is in order to receiving reference voltage Vref, and inverting input is in order to connect the drain terminal D of the 4th transistor M4, the drain voltage of the 4th transistor M4 clamped down on be reference voltage Vref, and its output terminal connects the control gate G of the 4th transistor M4.
As most preferred embodiment, the first transistor Mi, the 4th transistor M4, the 5th transistor M5 are nmos pass transistor, transistor seconds M2, the 3rd transistor M3 are the PMOS transistor, and the drain terminal D of the equal ground connection GND of the source S of the 4th transistor M4, the 5th transistor M5 and transistor seconds M2, the 3rd transistor M3 all meets supply voltage V'dd.
As optional embodiment, the first comparer I1 of memory cell reading device 300 is read amplifying circuit 302 by multichannel and shares.
In the storage unit A data read process, word line WL＜m that storage unit A is expert at〉be placed in noble potential, other word lines WL is placed in electronegative potential, gating control signal YA, YB are noble potential, the gating circuit conducting that transistor MC1 and transistor MC2 form, at this moment, storage unit A is selected.Under original state, all bit line BL all are placed in reference voltage Vref, and reference voltage level Vref scope is 0.10V ~ 0.80V; In data read process, bit line BL＜k+1 that storage unit A drain terminal D connects〉be placed in pre-charge voltage V
DD, V
DDBe the normal working voltage of storage unit A, bit line BL＜k that storage unit A source S connects〉connection data reading device 300, BL is unsettled for other bit lines.At this moment, the source-drain current I of storage unit A
ADirect input current I as storage unit reading device 300 second constant-current source circuits 320
4Flow into the 4th transistor M4, and produce and storage unit A source-drain current I on the 5th transistor M5
AThe image current I that size is identical
5, the image current I of the 5th transistor M5
5Be input to as input current and read in amplifying circuit 302, and via the input current I of the first transistor Mi as the first constant-current source circuit 310
2Flow into transistor seconds M2, and show as the image current I of the 3rd transistor M3
3, as the output of reading amplifying circuit 302.Image current I on the 3rd transistor M3
3Iref compares with reference current, and the data DOUT that this storage unit A is stored is exported in judgement according to this.
As another embodiment, the constant-current source circuit 310/320 of memory cell reading device 300 also comprises the impedance device of connecting with transistor M2/M3/M4/M5, image current value and the cell current I of constant-current source circuit 310/320 output
AEqual or proportional, cell current I
AShow as finally that current value equates with it or proportional the 3rd transistor M3 on image current I
3, as the output of reading amplifying circuit 302.Image current I on the 3rd transistor M3
3Iref compares with reference current, and the data DOUT that this storage unit A is stored is exported in judgement according to this.
This embodiment also provides a memory cell read method, and the method is storage unit source electric current read method.
The source current storage method for reading data that this embodiment provides is in order to the data of a certain storage unit in read memory, with reference to the circuit diagram of memory cell reading device shown in Fig. 3 a/3b, storage unit A is according to the data output one cell current I that stores
A, this cell current I
AReading object and comparison other as method for reading data that this embodiment provides.
Concrete must saying, the memory cell read method that this embodiment provides comprises:
Receive this cell current I
A
Receive reference current Iref;
This cell current I
ARead amplifying circuit 302 through constant-current source circuit 320 inputs;
This cell current I
AShow as the output I that reads amplifying circuit 302
3, and compare the data that this storage unit A of judgement output is according to this stored with reference current Iref.
In this embodiment, reference current Iref is provided by reference unit 301, and this reference unit 301 is also exported a reference voltage Vref simultaneously, and this reference voltage Vref scope is 0.10V ~ 0.80V.
As most preferred embodiment, the second constant-current source circuit 320 comprises the 4th transistor M4 and the 5th transistor M5, four, the grid G of the 5th transistor M4, M5 is connected, under the retroactive effect of the second comparer I2 and the first comparer I1, the drain voltage of the 4th transistor M4 and the 5th transistor M5 is clamped down on respectively is reference voltage Vref.Cell current I
AProduce the equal image current I of current value with it on the 5th transistor M5 via the 4th transistor M4
5, image current I
5Be input to the first constant-current source circuit 310 via the first transistor Mi that reads in amplifying circuit 302, and produce image current I via transistor seconds M2 on the 3rd transistor M3
3, this image current I
3Current value still with cell current I
AIdentical, as the output of reading amplifying circuit 302, and compare with reference current Iref, export according to this data DOUT that this storage unit A is stored.
As optional embodiment, constant-current source circuit 310/320 also comprises the impedance device of connecting with transistor M2/M3/M4/M5, cell current I
AAfter constant-current source circuit 310/320, the outgoing mirror image current value that shows and cell current I
AEquate or proportional, finally show as the image current I of the 3rd transistor M3 in output amplifier 302
3, as the output of reading amplifying circuit 302, and compare with reference current Iref, export according to this data DOUT that this storage unit A is stored.
The related data of this memory cell read method read and the data comparison other is electric current, and its reading speed is better than with the voltage source of object/drain terminal voltage reading access method as a comparison.In addition, because the method adopts the source electric current as reading object, involved reference voltage Vref value is 0.10V ~ 0.80V in reading process, much smaller than transistorized operating voltage V
DDAnd in the method, the the 4th, the 5th transistor M4 in the second constant-current source circuit 320, M5 drain voltage are all clamped down on is reference voltage Vref, four, the 5th transistor M4, M5 can enter duty at linear zone, but increased significantly the working power voltage scope, made sense data more accurate.
In the situation that can also consist of without departing from the spirit and scope of the present invention many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in instructions.
Claims (4)
1. memory cell reading device comprises:
Reference unit is in order to provide reference voltage and reference current;
Read amplifying circuit, comprise the first constant-current source circuit and the first transistor, wherein, the first constant-current source circuit comprises transistor seconds and the 3rd transistor, and the source of the first transistor is connected with the source of transistor seconds;
It is characterized in that, also comprise:
The second constant-current source circuit comprises the 4th transistor and the 5th transistor;
The first comparer in order to receiving described reference voltage, and is clamped down on described the first transistor and the described the 5th transistorized drain voltage and is described reference voltage;
The second comparer in order to receiving described reference voltage, and is clamped down on the described the 4th transistorized drain voltage and is described reference voltage;
Wherein, described the first transistor, the 4th transistor, the 5th transistor are nmos pass transistor, and described transistor seconds, the 3rd transistor are the PMOS transistor; Described the 4th transistor and the described the 5th equal ground connection of transistorized source and described transistor seconds and the described the 3rd transistorized drain terminal all connect supply voltage; Described the 4th transistor is connected with the 5th transistorized grid, and described transistor seconds, the 3rd transistorized grid are connected;
The in-phase input end of described the first comparer is in order to receive reference voltage, and inverting input connects described the first transistor and the described the 5th transistorized drain terminal, and its output terminal connects the control gate of described the first transistor; The in-phase input end of described the second comparer is in order to receive reference voltage, and inverting input connects the described the 4th transistorized drain terminal, and its output terminal connects described the 4th transistor and the described the 5th transistorized control gate;
The described the 4th transistorized drain terminal receiving element electric current after the mirror image by described the second constant-current source circuit and the first constant-current source circuit, with cell current output, and compares with reference current, and the data that storage unit is stored are exported in judgement accordingly.
2. memory cell reading device according to claim 1, it is characterized in that, described device also comprises gating circuit, and described gating circuit comprises the transistor of one or more series connection, its input signal is the gating control signal, in order to the storage unit of the selected reading out data of wanting.
3. memory cell read method, data in order to a storage unit in read memory, described storage unit is according to data output one cell current of storing, the method adopts reading device claimed in claim 1 to complete reading of cell data, it is characterized in that, the method is from storage unit source reading unit electric current, and itself and reference current are compared, the data that this storage unit of judgement output is according to this stored.
4. memory cell read method according to claim 3, is characterized in that, the method comprises:
The receiving element electric current;
Receive reference current;
Described cell current is read amplifying circuit through the second constant-current source circuit input;
Described cell current shows as the output of reading amplifying circuit, and compares with described reference current, the data that this storage unit of judgement output is according to this stored.
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| CN 200910198986 CN101763887B (en) | 2009-11-18 | 2009-11-18 | Reading device of storage unit and reading method thereof |
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| CN 200910198986 CN101763887B (en) | 2009-11-18 | 2009-11-18 | Reading device of storage unit and reading method thereof |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103106916B (en) * | 2012-12-21 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Memorizer and reading circuit, a kind of comparison circuit |
| CN103177749B (en) * | 2013-02-01 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Read voltage generation circuit |
| CN103559904A (en) * | 2013-11-05 | 2014-02-05 | 苏州贝克微电子有限公司 | Real amplifier of single-end data sensing |
| CN104505123B (en) * | 2014-12-05 | 2018-04-20 | 深圳市国微电子有限公司 | A kind of reading application circuit of antifuse memory |
| CN106024063A (en) * | 2016-07-19 | 2016-10-12 | 北京兆易创新科技股份有限公司 | Data reading device and method of nonvolatile memory |
| CN106024062B (en) * | 2016-07-19 | 2023-12-05 | 兆易创新科技集团股份有限公司 | Data reading device and method of nonvolatile memory |
| CN111833941B (en) * | 2019-04-15 | 2022-09-02 | 中电海康集团有限公司 | Reading circuit of memory and memory |
| CN114978478A (en) * | 2021-02-19 | 2022-08-30 | 联华电子股份有限公司 | Physical unclonable function circuit, method of operating the same, and semiconductor chip |
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