CN101727167B - power switching circuit - Google Patents
power switching circuit Download PDFInfo
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- CN101727167B CN101727167B CN2008101734242A CN200810173424A CN101727167B CN 101727167 B CN101727167 B CN 101727167B CN 2008101734242 A CN2008101734242 A CN 2008101734242A CN 200810173424 A CN200810173424 A CN 200810173424A CN 101727167 B CN101727167 B CN 101727167B
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- 238000001514 detection method Methods 0.000 claims abstract description 6
- 230000005059 dormancy Effects 0.000 description 18
- 230000037007 arousal Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 230000006266 hibernation Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
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Abstract
The invention discloses a power switching circuit which is configured on a mainboard of a notebook computer. The power switching circuit is characterized by comprising a startup detection circuit and a power switching unit, wherein the startup detection circuit is used for detecting whether a power knob of the notebook computer in a holding state is pressed or not, and then outputting a startup state signal. The power switching unit is coupled to the startup detection circuit and used for determining whether to switch off all the power supply rails on the mainboard according to the startup state signal.
Description
Technical field
The invention relates to a kind of power-saving technology, and particularly be in the power supply switch circuit of institute's consumed power under the holding state relevant for a kind of mainboard that can reduce notebook.
Background technology
Along with energy crisis is approached gradually, environmental consciousness comes back gradually, and in recent years, U.S. government has proposed 80 Plus and Energy Star energy-conservation standards such as (Energy Star), with expectation to the power consumption of electronic product standard to some extent.Wherein, Energy Star 4.0 standards of latest edition have begun formally effective in July, 2007, and its requirement for the stand-by power consumption of notebook (Notebook) seems quite harsh.
The mainboard (motherboard) of the Energy Star 4.0 regulation notebooks of latest edition is at network enabled arousal function (Wake On Lan not, WOL) under the situation, when notebook is in dormancy (hibernation, S4) and the shutdown (power off, S5) etc. during the standby state, its stand-by power consumption will be lower than 0.7W.
Yet, inserting when the direct current jack (DC jack) of notebook under the situation of electric pressure converter (adaptor) and since the power management chip on the mainboard (for example being the TPS51120 power management chip) still can receive standby power (+VBATR) use to the chip on the mainboard with the power rail (power rail) that continues generations+3V and+5V.Thus, the stand-by power consumption that the power that those chips consumed will probably can cause notebook to be in dormancy (S4) and shutdown (S5) state is higher than the 0.7W of Energy Star 4.0 defineds.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of power supply switch circuit, it can be at the mainboard of notebook under the situation of network enabled arousal function (WOL), the stand-by power consumption that causes notebook to be in dormancy (S4) and shutdown (S5) state is close in 0W, uses the regulation that meets Energy Star 4.0.
The invention provides a kind of power supply switch circuit, it is disposed on the mainboard of notebook.Described power supply switch circuit is characterised in that it comprises start testing circuit and power switching unit.Wherein, whether the start testing circuit is pressed in order to the power knob that detection is in the notebook under the holding state, and exports the open state signal according to this.Power switching unit couples the start testing circuit, in order to determine whether to cut off all power rails on the described mainboard according to described open state signal.
In one embodiment of this invention, described start testing circuit comprises first resistance, second resistance, first nmos pass transistor, first electric capacity, and Zener diode.Wherein, an end of described first resistance and described second resistance couples standby power.The grid of described first nmos pass transistor couples the other end of described power knob and described first resistance, and the drain electrode of described first nmos pass transistor couples the other end of described second resistance, and the source electrode of described first nmos pass transistor then is coupled to earthing potential.
One end of described first electric capacity couples the drain electrode of described first nmos pass transistor, and the other end of described first electric capacity then is coupled to described earthing potential.The anode tap of described Zener diode couples described earthing potential, and the cathode terminal of described Zener diode then couples the drain electrode of described first nmos pass transistor, and exports described open state signal.
In one embodiment of this invention, described power switching unit comprises PMOS transistor, the 3rd resistance, the 4th resistance, second nmos pass transistor, the 5th resistance, second electric capacity, first diode, second diode, and the 3rd diode.Wherein, the transistorized source electrode of described PMOS couples described standby power, and described PMOS transistor drain is then exported described standby power when described PMOS transistor turns.One end of described the 3rd resistance couples the transistorized source electrode of described PMOS, and the other end of described the 3rd resistance then is coupled to the transistorized grid of described PMOS.
One end of described the 4th resistance couples the transistorized grid of described PMOS.The drain electrode of described second nmos pass transistor couples the other end of described the 4th resistance, and the source electrode of described second nmos pass transistor then is coupled to described earthing potential.One end of described the 5th resistance couples the grid of described second nmos pass transistor, and the other end of described second nmos pass transistor then is coupled to described earthing potential.One end of described second electric capacity couples the grid of described second nmos pass transistor, and the other end of described second electric capacity then is coupled to described earthing potential.
The anode tap of described first diode is in order to receive the WOL (Wake On LAN) signal, and the cathode terminal of described first diode then is coupled to the grid of described second nmos pass transistor.The anode tap of described second diode is kept signal in order to receive power supply, and the cathode terminal of described second diode then is coupled to the grid of described second nmos pass transistor.The anode tap of described the 3rd diode is in order to receive described open state signal, and the cathode terminal of described the 3rd diode then is coupled to the grid of described second nmos pass transistor.
In one embodiment of this invention, when the power knob of the notebook under being in described holding state was not pressed, described power supply keeps signal and described open state signal is all low voltage level.
In one embodiment of this invention, when the power knob of the notebook under being in described holding state was pressed, described power supply keeps signal and described open state signal is a high-voltage level.Thus, all power rails that recover on the described mainboard are used in described PMOS transistor meeting conducting.
In one embodiment of this invention, when described mainboard network enabled arousal function, described WOL (Wake On LAN) signal is a high-voltage level, otherwise is low voltage level.
In one embodiment of this invention, described WOL (Wake On LAN) signal is provided by the network control chip on the described mainboard, and described power supply is kept signal and provided by the keyboard control chip on the described mainboard.
In one embodiment of this invention, described holding state is dormancy (hibernation) state or shutdown (power off) state.
The present invention provides a kind of mainboard with power supply switch circuit that the invention described above proposes in addition.
The present invention provides a kind of notebook with mainboard that the invention described above proposes in addition.
The present invention directly disposes a power supply switch circuit on the mainboard of notebook.This power supply switch circuit can be at the mainboard of notebook under the situation of network enabled arousal function (WOL), and when notebook is in dormancy (S4) and shutdown (S5) state, cut off all power rails on the mainboard, use the stand-by power consumption that causes notebook to be in dormancy and off-mode and be close to, use the regulation that meets Energy Star 4.0 in 0W.
For above and other objects of the present invention, feature and advantage can be become apparent, the several embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates the synoptic diagram into the notebook of one embodiment of the invention.
Fig. 2 illustrates the circuit diagram into the start testing circuit of one embodiment of the invention.
Fig. 3 illustrates the circuit diagram into the power switching unit of one embodiment of the invention.
Embodiment
The technology effect that the present invention desired to reach mainly is in order to allow the mainboard of notebook under the situation of network enabled arousal function (WOL) not, and its stand-by power consumption that is in dormancy (S4) and shutdown (S5) state can meet the regulation of Energy Star 4.0.And following content will encyclopaedize at the technical characterictic of this case, uses to offer those skilled in the art and consider and examine.
Fig. 1 illustrates the synoptic diagram into the notebook 100 of one embodiment of the invention.Please refer to Fig. 1, notebook 100 comprises mainboard 101 and power knob (power button) PB.Certainly, should know that with the technician of this area notebook 100 also includes other parts, for example display screen, CD-ROM drive ... etc., do explanation but following content only can list parts related to the present invention.
In present embodiment, mainboard 101 includes the power supply switch circuit of being made up of start testing circuit 103 and power switching unit 105 (directly being configured on the mainboard 101), network control chip 107, keyboard control chip 109, and power management chip 111 (for example being the TPS51120 power management chip).Wherein, whether start testing circuit 103 is pressed in order to the power knob PB that detection is in the notebook 100 under the holding state (for example being in the state of dormancy (S4) or shutdown (S5)), and exports open state signal PWRSW according to this; And power switching unit 105 couples start testing circuit 103, determines whether to cut off all power rails (power rails) on the mainboard 101 in order to foundation open state signal PWRSW.
Clearer, Fig. 2 illustrates the circuit diagram into the start testing circuit 103 of one embodiment of the invention.Please merge with reference to Fig. 1 and Fig. 2, start testing circuit 103 comprises first resistance R 1, second resistance R 2, nmos pass transistor N1, first capacitor C 1, and Zener diode (Zener Diode) ZD (for example Zener diode about 3V).Wherein, one end of first resistance R 1 and second resistance R 2 couples standby power+VBATR (being approximately 18.5V), and this standby power+VBATR can just produce under the situation of insertion electric pressure converter (adaptor does not illustrate) at the direct current jack (DC jack does not illustrate) of notebook 100.
The grid of the first nmos pass transistor N1 (gate) couples the other end of the power knob PB and first resistance R 1, the drain electrode of the first nmos pass transistor N1 (drain) couples the other end of second resistance R 2, and the source electrode of the first nmos pass transistor N1 (source) then is coupled to earthing potential.One end of first capacitor C 1 couples the drain electrode of the first nmos pass transistor N1, and the other end of first capacitor C 1 then is coupled to earthing potential.The anode tap of Zener diode ZD (anode) couples earthing potential, and the cathode terminal of Zener diode ZD (cathode) then couples the drain electrode of the first nmos pass transistor N1, and output open state signal PWRSW.
In present embodiment, when the power knob PB of the notebook 100 under being in dormancy (S4) and shutdown (S5) state is not pressed, open state signal PWRSW is a low voltage level, but when the power knob PB of the notebook 100 under being in dormancy (S4) and shutdown (S5) state was pressed, open state signal PWRSW then was a high-voltage level.
In addition, Fig. 3 illustrates the circuit diagram into the power switching unit 105 of one embodiment of the invention.Please merge with reference to Fig. 1～Fig. 3, power switching unit 105 comprises PMOS transistor P1, the 3rd resistance R 3, the 4th resistance R 4, nmos pass transistor N2, the 5th resistance R 5, second capacitor C 2, the first diode D1, the second diode D2, and the 3rd diode D3.Wherein, the source electrode of PMOS transistor P1 couples standby power+VBATR, and the drain electrode of PMOS transistor P1 is then exported standby power+VBATR and given power management chip 111 when PMOS transistor P1 conducting.
One end of the 3rd resistance R 3 couples the source electrode of PMOS transistor P1, and the other end of the 3rd resistance R 3 then is coupled to the grid of PMOS transistor P1.One end of the 4th resistance R 4 couples the grid of PMOS transistor P1.The drain electrode of nmos pass transistor N2 couples the other end of the 4th resistance R 4, and the source electrode of nmos pass transistor N2 then is coupled to earthing potential.
One end of the 5th resistance R 5 couples the grid of nmos pass transistor N2, and the other end of nmos pass transistor N2 then is coupled to earthing potential.One end of second capacitor C 2 couples the grid of nmos pass transistor N2, and the other end of second capacitor C 2 then is coupled to earthing potential.The anode tap of the first diode D1 is in order to the WOL (Wake On LAN) signal NIC_GPIO that is provided by network control chip 107 to be provided, and the cathode terminal of the first diode D1 then is coupled to the grid of nmos pass transistor N2.
The anode tap of the second diode D2 is kept signal KBC_PWRKEEP in order to the power supply that is provided by keyboard controller 109 to be provided, and the cathode terminal of the second diode D2 then is coupled to the grid of nmos pass transistor N2.The anode tap of the 3rd diode D3 is in order to receive open state signal PWRSW, and the cathode terminal of the 3rd diode D3 then is coupled to the grid of nmos pass transistor N2.
In present embodiment, when the power knob PB of the notebook 100 under being in dormancy (S4) and shutdown (S5) state is not pressed, it is low voltage level that power supply is kept signal KBC_PWRKEEP, but when the power knob PB of the notebook 100 under being in dormancy (S4) and shutdown (S5) state was pressed, power supply was kept signal KBC_PWRKEEP and then is high-voltage level.In addition, when mainboard 101 network enabled were waken (WOL) function up, WOL (Wake On LAN) signal NIC_GPIO was a high-voltage level, otherwise was low voltage level.
Based on as can be known above-mentioned, when mainboard 101 when network enabled is not waken (WOL) function up, WOL (Wake On LAN) signal NIC_GPIO can be low voltage level.Thus, when the power knob PB of the notebook 100 under being in dormancy (S4) and shutdown (S5) state is not pressed, because open state signal PWRSW and power supply are kept signal KBC_PWRKEEP and are all low voltage level, so PMOS transistor P1 can be cut off.
With this understanding, because standby power+VBATR can not be provided to power management chip 111, so power management chip 111 just not can as continue as the Prior Art generations+3V and+power rail of 5V uses (that is all power rails on the cut-out mainboard 101) for the chip of mainboard 101, can level off to 0W to such an extent as to be in the standby consumed power of dormancy (S4) and the notebook 100 of shutdown under (S5) state, so can meet the regulation of Energy Star 4.0.
Yet, when the power knob PB of the notebook 100 under being in dormancy (S4) and shutdown (S5) state is pressed, because open state signal PWRSW can transfer high-voltage level to by low voltage level, so nmos pass transistor N2 can be switched on, to such an extent as to PMOS transistor P1 also can follow conducting.
With this understanding, because standby power+VBATR can be by regular supply to power management chip 111, thus power management chip 111 will as continue as the Prior Art generations+3V and+power rail of 5V uses (that is all power rails on the recovery mainboard 101) for the chip of mainboard 101.Thus, receive at keyboard control chip 109+during the power rail of 3V, it can be kept signal KBC_PWRKEEP with power supply and transfer high-voltage level to by low voltage level, so that power knob PB is when returning to the state that is not pressed, notebook 100 can allow nmos pass transistor N2 continue to be maintained at the state of conducting, so can be finished the action of follow-up start.
On the contrary, when mainboard 101 network enabled were waken (WOL) function up, WOL (Wake On LAN) signal NIC_GPIO can be high-voltage level.Thus, be not pressed even if be in the power knob PB of the notebook 100 under dormancy (S4) and shutdown (S5) state, nmos pass transistor N2 still can be switched on, to such an extent as to PMOS transistor P1 also can follow conducting.
With this understanding, because standby power+VBATR can be by regular supply to power management chip 111, thus power management chip 111 will as continue as the Prior Art generations+3V and+power rail of 5V uses (that is all power rails on the recovery mainboard 101) for the chip of mainboard 101.Thus, mainboard 101 can network enabled wake (WOL) function up.
In sum, the present invention directly disposes a power supply switch circuit on the mainboard of notebook.This power supply switch circuit can be at the mainboard of notebook under the situation of network enabled arousal function (WOL), and when notebook is in dormancy (S4) and shutdown (S5) state, cut off all power rails on the mainboard, using the stand-by power consumption that causes notebook to be in dormancy and off-mode is close in 0W, use the regulation that meets Energy Star 4.0, can prolong the battery powered time of notebook simultaneously again.
Though the present invention discloses as above with a plurality of embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (11)
1. a power supply switch circuit is disposed on the mainboard of a notebook, it is characterized in that this power supply switch circuit comprises:
One start testing circuit, whether a power knob that is in this notebook under the holding state in order to detection is pressed, and exports an open state signal according to this; And
One power switching unit couples this start testing circuit, determines whether to cut off all power rails on this mainboard according to this open state signal,
Wherein this start testing circuit comprises:
One first resistance, the one end couples a standby power; One second resistance, the one end couples this standby power;
One first nmos pass transistor, its grid couples the other end of this power knob and this first resistance, and its drain electrode couples the other end of this second resistance, and its source electrode then is coupled to an earthing potential;
One first electric capacity, the one end couples the drain electrode of this first nmos pass transistor, and its other end then is coupled to this earthing potential; And
One Zener diode, its anode tap couples this earthing potential, and its cathode terminal then couples the drain electrode of this first nmos pass transistor, and exports this open state signal.
2. power supply switch circuit as claimed in claim 1 is characterized in that, this power switching unit comprises:
One PMOS transistor, its source electrode couples this standby power, and this standby power is then exported in its drain electrode when this PMOS transistor turns;
One the 3rd resistance, one end couple the transistorized source electrode of this PMOS, and its other end then is coupled to the transistorized grid of this PMOS;
One the 4th resistance, one end couple the transistorized grid of this PMOS;
One second nmos pass transistor, its drain electrode couples the other end of the 4th resistance, and its source electrode then is coupled to this earthing potential;
One the 5th resistance, the one end couples the grid of this second nmos pass transistor, and its other end then is coupled to this earthing potential;
One second electric capacity, the one end couples the grid of this second nmos pass transistor, and its other end then is coupled to this earthing potential;
One first diode, its anode tap is in order to receive a WOL (Wake On LAN) signal, and its cathode terminal then is coupled to the grid of this second nmos pass transistor;
One second diode, its anode tap is kept signal in order to receive a power supply, and its cathode terminal then is coupled to the grid of this second nmos pass transistor; And
One the 3rd diode, its anode tap is in order to receive this open state signal, and its cathode terminal then is coupled to the grid of this second nmos pass transistor.
3. power supply switch circuit as claimed in claim 2 is characterized in that, when this power knob of this notebook under being in this holding state was not pressed, this power supply keeps signal and this open state signal is all a low voltage level.
4. power supply switch circuit as claimed in claim 3 is characterized in that, when this power knob of this notebook under being in this holding state was pressed, this power supply keeps signal and this open state signal is a high-voltage level.
5. power supply switch circuit as claimed in claim 4 is characterized in that, when this power supply was kept signal and this open state signal and is all this high-voltage level, this PMOS transistor can conducting, uses all power rails that recover on this mainboard.
6. power supply switch circuit as claimed in claim 2 is characterized in that, when this mainboard was supported a calling function of network, this WOL (Wake On LAN) signal was a high-voltage level, otherwise was a low voltage level.
7. power supply switch circuit as claimed in claim 2 is characterized in that, this WOL (Wake On LAN) signal is provided by the network control chip on this mainboard.
8. power supply switch circuit as claimed in claim 2 is characterized in that, this power supply is kept signal and provided by the keyboard control chip on this mainboard.
9. power supply switch circuit as claimed in claim 1 is characterized in that, this holding state is a dormant state or an off-mode.
10. mainboard with power supply switch circuit as claimed in claim 1.
11. notebook with mainboard as claimed in claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101734242A CN101727167B (en) | 2008-10-21 | 2008-10-21 | power switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101734242A CN101727167B (en) | 2008-10-21 | 2008-10-21 | power switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101727167A CN101727167A (en) | 2010-06-09 |
| CN101727167B true CN101727167B (en) | 2011-12-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101734242A Expired - Fee Related CN101727167B (en) | 2008-10-21 | 2008-10-21 | power switching circuit |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103186441B (en) * | 2011-12-30 | 2016-06-29 | 国网山东省电力公司单县供电公司 | Switching circuit |
| CN105159431A (en) * | 2015-07-29 | 2015-12-16 | 山东超越数控电子有限公司 | Low-static-power design method for complete machine at low temperature |
| CN106100071B (en) * | 2016-08-17 | 2019-02-19 | 北京拓盛智联技术有限公司 | A kind of battery protecting circuit |
| CN113559350A (en) * | 2021-08-02 | 2021-10-29 | 北京哈特凯尔医疗科技有限公司 | Control circuit of hydration treatment liquid inlet and outlet balance system |
| TWI824464B (en) * | 2022-03-31 | 2023-12-01 | 仁寶電腦工業股份有限公司 | Electronic device and a startup method for the electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6724588B1 (en) * | 1999-09-22 | 2004-04-20 | Dell Usa L.P. | Power supply selector |
| CN1622005A (en) * | 2003-11-24 | 2005-06-01 | 顺德市顺达电脑厂有限公司 | Power supply status automatic test method for computer apparatus |
| CN200972626Y (en) * | 2005-05-20 | 2007-11-07 | 金德奎 | Computer switch power supply and micro-wait power control device of its system |
-
2008
- 2008-10-21 CN CN2008101734242A patent/CN101727167B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6724588B1 (en) * | 1999-09-22 | 2004-04-20 | Dell Usa L.P. | Power supply selector |
| CN1622005A (en) * | 2003-11-24 | 2005-06-01 | 顺德市顺达电脑厂有限公司 | Power supply status automatic test method for computer apparatus |
| CN200972626Y (en) * | 2005-05-20 | 2007-11-07 | 金德奎 | Computer switch power supply and micro-wait power control device of its system |
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| CN101727167A (en) | 2010-06-09 |
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Owner name: STATE GRID CORPORATION OF CHINA Free format text: FORMER OWNER: YINGYEDA CO., LTD., TAIWAN Effective date: 20141218 Owner name: STATE GRID ZHEJIANG ELECTRIC POWER COMPANY SHAOXIN Effective date: 20141218 |
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Inventor after: Xu Yue Inventor after: Zheng Ye Inventor after: Yu Gang Inventor after: Guo Jinsong Inventor after: Yu Jianjun Inventor after: Yu Miaojie Inventor after: He Haixia Inventor before: Dong Buqiang Inventor before: Liu Shihao |
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Free format text: CORRECT: ADDRESS; FROM: TAIWAN, CHINA TO: 100031 XICHENG, BEIJING Free format text: CORRECT: INVENTOR; FROM: DONG BUQIANG LIU SHIHAO TO: XU YUE ZHENG YE YU GANG GUO JINSONG YU JIANJUN YU MIAOJIE HE HAIXIA |
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Effective date of registration: 20141218 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: State Grid Zhejiang Electric Power Company Patentee after: Shaoxing Power Supply Company of State Grid Zhejiang Electric Power Company Patentee after: State Grid Zhejiang Zhuji Power Supply Co., Ltd. Patentee after: Zhuji Dongbai Electric Power Equipment Manufacturing Co., Ltd. Address before: Taipei City, Taiwan Chinese Shilin District Hougang Street No. 66 Patentee before: Inventec Corporation |
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