CN101685774A - Heteroepitaxial growth process based on interface nano-structure - Google Patents
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Abstract
The invention discloses a heteroepitaxial growth process based on interface nano-structure, wherein lattice mismatch exists between a substrate material and an epitaxial layer material, and the formation of the epitaxial layer comprises four stages: firstly, forming metal nano granules on the substrate; secondly, growing a nano-line; thirdly, depositing a mask layer and enabling the upper part ofthe nano-line to expose outside; and finally, taking the exposed part of the nano-line as a window transversely grown epitaxial layer. In the invention, the nano-line with high crystal quality is usedas the window for transversely growing, and the mask layer separates the transversely grown epitaxial layer and the substrate so as to eliminate the limitation of lattice match between the epitaxiallayer material and the substrate material. The invention can successfully solve the problem of heteroepitaxial growth among crystal materials with the lattice mismatch and provides a new idea for therealization of photoelectron integration.
Description
Technical field:
The present invention relates to a kind of heteroepitaxial growth process in the optoelectronic areas, particularly the heteroepitaxial growth method of the semiconductor crystal storeroom of lattice mismatch (being that lattice does not match).
Background technology:
World today's opto-electronic device of deducing turns to integrated great turnover by discrete.Owing to be subjected to all restrictions and the constraint of aspects such as material, structure and technology, obtain considerable progress, photoelectron is integrated must to solve a series of important basic science problems.
Growth various material system (being the material compatibility) on a kind of material substrate, the excellent properties that collects various materials is an one, is to realize the integrated desirable approach of photoelectron.For example: silicon (Si) crystal is the most frequently used, the most cheap microelectronic material; But, can't be used as photoelectron material, especially for luminescent material because Si is an indirect bandgap material.And the III-V group iii v compound semiconductor material as GaAs (GaAs), indium phosphide (InP), gallium nitride (GaN) etc., is the most frequently used photoelectron material.If can realize the integrated of silicon materials and III-V family material, the two is combined; On a block semiconductor chip, both made microelectronic integrated circuit, make opto-electronic device again; Be expected to advance the photoelectron development of integration technology.
Existing heteroepitaxy stratiform growth method mainly is faced with the problem (D.Colombo of lattice mismatch issue and thermal mismatching, E.Grilli, M.Guzzi, S.Marchionna, M.Bonfanti, " Analysis of strainrelaxation by microcracks in epitaxial GaAs grown on Ge/Si substrates ", Journalof Applied Physics, vol.101, pp.103519,2007.).The heteroepitaxial growth of GaAs/Si for example, because the lattice mismatch of the two is up to 4.1%, this has caused in the epitaxial loayer defect concentration up to 10
8/ cm
2In order to address this problem, the technology that adopts has at present: resilient coating technology (N.Gopalakrishnan, K.Baskar, H.Kawanami, et al., Effects of the lowtemperature buffer layer thickness on the growth of GaAs on Si by MBE, J.Cryst.Growth, vol.250, pp.29-33,2003), flexible substrate technology (C.L.Chua, W.Y.Hsu, C.H.Lin, et al., Overcoming the pseudomorphic critical thickness limit usingcompliant substrates, Appl.Phys.Lett., vol.64, pp.3640-3642,1994) and horizontal extension technology (J.D.Schaub, R.Li, C.L.Schow, et al., Resonant-Cavity-EnhancedHigh-Speed Si Photodiode Grown by Epitaxial Lateral Overgrowth, IEEEPHOTONICS TECHNOLOGY LETTERS, vol.12, pp.1647,1999).Wherein:
Resilient coating (buffer) technology: be to realize that by introducing resilient coating the lattice constant with substrate (such as Si) carries out the transition to the lattice constant of epitaxial loayer (such as GaAs).Come the relaxation lattice constant by introducing misfit dislocation (misfitdislocation), stop or suppress, thereby improve the crystal mass of epitaxial loayer because the threading dislocation (threading dislocation) that lattice mismatch caused extends through in the epitaxial loayer.But for the relaxation lattice constant, the growth temperature of resilient coating is usually far below normal growth temperature, therefore the defect concentration of resilient coating itself is higher, and this has reduced top upward crystal mass (J.A.Carlin, the S.A.Ringel of the epitaxial loayer of growth, et al., Impact of GaAs buffer thickness on electronicquality of GaAs grown on graded Ge/GeSi/Si substrates, Appl.Phys.Lett., vol.14, pp.1884,2000).Therefore the defect concentration of epitaxial loayer is difficult to accomplish to be lower than 10
6/ cm
2, can't be used to prepare the high-performance optical electronic device, especially for luminescent device;
Flexible substrate (Compliant Substrate) technology: be between substrate and epitaxial loayer, to introduce a flexible layer material, and absorb or discharge the strain that causes by lattice mismatch, thereby reduce the defective of epitaxial loayer by the elastic deformation of this flexible layer.The flexible layer that adopts has two kinds at present: the thin layer and the strontium titanates (SrTiO of distortion bonding
3) thin layer.For the thin layer of distortion bonding, realize large-area preparation because bonding technology is very complicated, very difficult, and residual stress and thin layer surface undulation big (F.E.Ejeckam, M.L.Seaford, Y.H.Lo, H.Q.Hou, et al., Appl.Phys.Lett., vol.71, pp.776,1997).For strontium titanates (SrTiO
3) thin layer, Motorola is (K.Eisenbeiser after 2001 reported first, J.Finder, R.Emrick, et al., RF devices implemented on GaAs on Si substratesusing a SrTiO3 buffer layer, in Proc.GaAs IC Symp., Baltimore, MD, 2001), because the repeated problem of test is not seen below continuous report.Therefore the flexible substrate technology also is in the exploratory stage, does not also thoroughly solve the problem of lattice mismatch;
Horizontal extension technology: be to grow the GaAs thin layer as Seed Layer at the Si substrate earlier, then cover one deck mask (as SiO
2), expose the GaAs Seed Layer thereby utilize photoetching technique on mask, to produce window, carry out transversal epitaxial growth GaAs at last.Because the cohesion forming core of GaAs on mask can be bigger, thus GaAs can't be on mask direct growth; Therefore, GaAs is only in the growth of window place, and lateral magnification gradually, forms the GaAs pantostrat that covers the mask layer top at last.But the GaAs of window area is grown directly upon on the Si substrate, still has higher defect concentration, and this has reduced the GaAs crystal mass of cross growth.Simultaneously, photoetching process is comparatively complicated, and can introduce contaminating impurity.
In sum, above method is solving on the lattice mismatch issue, and is all undesirable.In view of this, exploring new technology and new departure, solve the problem that lattice mismatch brought between epitaxial loayer and the substrate, improve the crystal mass of epitaxial loayer, is a problem that prior art is difficult to overcome.
The growth of semiconductor nanowires at present usually with metal nanoparticle as catalyst, utilize the semiconductor epitaxial growth technique, grow vertical in the position of metallic particles or favour the columnar nanometer line of substrate horizontal plane.Because the contact area very little (less than 1 square micron) of nano wire and substrate, lattice mismatch can not produce defective in so little zone.Therefore, the crystal mass of nano wire is not subjected to the influence of substrate, and there is not lattice mismatch issue in the heteroepitaxy of nano wire.At present, on the Si substrate, grown flawless high-quality GaAs nano wire (Thomas
C.Patrik T.Svensson, et al, Epitaxial III-V Nanowires on Silicon, Nano.Lett., vol.4, pp.1987-1990,2004).
But semiconductor device structure substantially all belongs to parallel layer structure at present, and corresponding technology also is at layer structure; And, on so very thin nano wire, make then unusual difficulty of device at nano thread structure vertical or that tilt, need complexity, expensive equipment such as electron beam lithography simultaneously.Therefore how utilizing the nano wire of high-crystal quality, and change it into plane layer structure, also is a technical barrier that needs to be resolved hurrily.
Summary of the invention:
The objective of the invention is to find out a kind of new extension scheme, realize the high-quality extension of two kinds of materials of big (lattice mismatch=((epitaxial material lattice constant-substrate lattice constant)/substrate lattice constant) * 100%) of lattice mismatch.Purpose of the present invention can realize in the following manner.
The invention provides a kind of heteroepitaxial growth process, wherein have lattice mismatch between backing material and the epitaxial film materials, and the formation of epitaxial loayer comprises following four-stage based on interface nano-structure:
At first on substrate, form metal nanoparticle;
Follow grow nanowire;
Precipitate mask layer then and make the top of nano wire expose;
At last with the nano wire part exposed as window cross growth epitaxial loayer.
Wherein formed metal nanoparticle diameter is 10～500nm the phase I.
Wherein lattice mismatch surpasses 0.1% between preferred substrate material and the epitaxial film materials.
Wherein in the second stage nanowire growth be with metal nanoparticle as catalyst, grow vertical in the position of metallic particles or favour the semiconductor column nano wire of substrate horizontal plane, wherein the diameter of the diameter of nano wire and metallic particles is close.
Wherein phase III deposition mask layer makes nano wire and substrate be buried in the mask layer, make the top of nano wire expose via methods such as etching, grinding or ultrasonic waves, and the bottom of nano wire and substrate surface is still coated by mask layer.
Wherein the part of exposing with nano wire in the quadravalence section is carried out the transversal epitaxial growth semi-conducting material and is formed one deck continuous semiconductor epitaxial loayer as window.
Described backing material is selected from following crystal: silicon, GaAs, indium phosphide or germanium.
Described epitaxial film materials is selected from III-V family semi-conducting material or IV family semi-conducting material, is preferably to be selected from GaAs, indium phosphide, gallium nitride, gallium phosphide, indium arsenide or germanium silicon.
The solution of the present invention combines the advantage of nanowire growth technology and transversal epitaxial growth technology.The nano wire of or inclination vertical with substrate by growth earlier, at this moment, owing to the contact area very little (nanoscale) of epitaxial film materials nano wire and substrate, and the atom in the nano wire can transversal stretching; Even therefore the lattice constant and the substrate of epitaxial loayer do not match, still can grow on substrate obtains fabricating low-defect-density, high-quality nano wire.
This programme is compared with the transversal epitaxial growth technology, adopts nano wire as the extension window, need not complicated photoetching process, and reduced the pollution that photoetching process is brought.Simultaneously, because nano wire has higher crystal mass, the crystal mass of follow-up horizontal extension layer is also higher.Therefore, it is simple that this programme has technology, the advantage that the epitaxial loayer crystal mass is higher.
Description of drawings:
Fig. 1 forms the nano-metal particle schematic diagram on the Si substrate;
Fig. 2 utilizes the semiconductor nanowires schematic diagram of metallic particles as the catalyst growth;
Fig. 3 (a) covers substrate and nano wire schematic diagram for the mask layer of growth;
Fig. 3 (b) is for to utilize methods such as etching, grinding or ultrasonic wave to make the top of nano wire expose schematic diagram;
Fig. 4 (a) is for being the starting stage schematic diagram that window carries out transversal epitaxial growth with the nano wire;
Fig. 4 (b) is for being the final effect schematic diagram that window carries out horizontal extension with the nano wire.
Embodiment:
The present invention is described in detail so that better understand essence of the present invention below in conjunction with accompanying drawing.
Example 1:
The GaAs/Si heteroepitaxial growth
1. at first, the thick metallic films such as gold of the plating about 0.5nm of one deck through high annealing, obtain the metal nanoparticle that radius is about 10nm, as shown in Figure 1 on the Si substrate;
Then with metal nanoparticle as catalyst, utilize the semiconductor epitaxial growth technique, in the position that metallic particles is arranged, grow GaAs columnar nanometer line perpendicular to the substrate horizontal plane.Wherein the diameter of the diameter of GaAs nano wire and metallic particles is close, and height is greater than 10nm, as shown in Figure 2;
3. then continue deposition layer of silicon dioxide (SiO
2) material is as mask layer, makes nano wire be buried in the mask layer, shown in Fig. 3 (a); Utilize lithographic method to make the top of nano wire expose then, and the bottom of nano wire and substrate surface are still coated by mask layer, shown in Fig. 3 (b);
4. utilize part that nano wire exposes as window at last, carry out transversal epitaxial growth GaAs semi-conducting material, shown in Fig. 4 (a), continued growth forms one deck continuous semiconductor epitaxial loayer at last, shown in Fig. 4 (b).
Example 2:
The InP/Ge heteroepitaxial growth
1. at first, the thick platinum film of the plating about 2nm of one deck through high annealing, obtains the metal nanoparticle that radius is about 100nm on the Ge substrate;
Then with metal nanoparticle as catalyst, utilize the semiconductor epitaxial growth technique, in the position that metallic particles is arranged, grow favour the substrate horizontal plane InP columnar nanometer line.Wherein the diameter of the diameter of InP nano wire and metallic particles is close, and height is greater than 10nm;
3. then continue deposition one deck silicon nitride (Si
3N
4) material is as mask layer, makes nano wire be buried in the mask layer, utilize Ginding process to make the top of nano wire expose then, and the bottom of nano wire and substrate surface still coated by mask layer;
4. utilize part that nano wire exposes as window at last, carry out transversal epitaxial growth InP semi-conducting material continued growth formation at last one deck continuous semiconductor epitaxial loayer.
Example 3
The GaN/Si heteroepitaxial growth
1. at first, the thick platinum/titanium metal thin film of the plating about 10nm of one deck through high annealing, obtains the metal nanoparticle that radius is about 500nm on the Si substrate;
Then with metal nanoparticle as catalyst, utilize the semiconductor epitaxial growth technique, in the position that metallic particles is arranged, grow GaN columnar nanometer line perpendicular to the substrate horizontal plane.Wherein the diameter of the diameter of GaN nano wire and metallic particles is close, and height is greater than 10nm, as shown in Figure 2.
3. then continue deposition one deck nitrogen-oxygen-silicon (SiON) material as mask layer, make nano wire be buried in the mask layer, utilize ultrasonic method to make the top of nano wire expose then, and the bottom of nano wire and substrate surface are still coated by mask layer;
4. utilize part that nano wire exposes as window at last, carry out transversal epitaxial growth GaN semi-conducting material, continued growth forms one deck continuous semiconductor epitaxial loayer at last.
Example 4
The SiGe/GaAs heteroepitaxial growth
1. at first, the thick golden metallic film of the plating about 8nm of one deck through high annealing, obtains the metal nanoparticle that radius is about 300nm on the GaAs substrate;
Then with metal nanoparticle as catalyst, utilize the semiconductor epitaxial growth technique, in the position that metallic particles is arranged, grow SiGe columnar nanometer line perpendicular to the substrate horizontal plane.Wherein the diameter of the diameter of nano wire and metallic particles is close, and height is greater than 10nm;
3. then continue deposition layer of silicon dioxide (SiO
2) material is as mask layer, makes nano wire be buried in the mask layer, utilize lithographic method to make the top of nano wire expose then, and the bottom of nano wire and substrate surface still coated by mask layer;
4. utilize part that nano wire exposes as window at last, carry out transversal epitaxial growth SiGe semi-conducting material, continued growth forms one deck continuous semiconductor epitaxial loayer at last.
Example 5
The InAs/Si heteroepitaxial growth
1. at first, the thick platinum film of the plating about 5nm of one deck through high annealing, obtains the metal nanoparticle that radius is about 400nm on the Si substrate;
Then with metal nanoparticle as catalyst, utilize the semiconductor epitaxial growth technique, in the position that metallic particles is arranged, grow the InAs columnar nanometer line that favours the substrate horizontal plane.Wherein the diameter of the diameter of nano wire and metallic particles is close, and height is greater than 10nm;
3. then continue deposition one deck silicon nitride (Si
3N
4) material is as mask layer, makes nano wire be buried in the mask layer, utilize Ginding process to make the top of nano wire expose then, and the bottom of nano wire and substrate surface still coated by mask layer;
4. utilize part that nano wire exposes as window at last, carry out transversal epitaxial growth InAs semi-conducting material, continued growth forms one deck continuous semiconductor epitaxial loayer at last.
The above is know-why and limiting examples that the present invention uses, the equivalent transformation of doing according to conception of the present invention, as long as when the scheme that it used does not exceed the scope that claims contain yet, and all should be within the scope of the invention.
Claims (9)
1, a kind of heteroepitaxial growth process based on interface nano-structure it is characterized in that having lattice mismatch between backing material and the epitaxial film materials, and the formation of epitaxial loayer comprises following four-stage:
At first on substrate, form metal nanoparticle;
Follow grow nanowire;
Precipitate mask layer then and make the top of nano wire expose;
At last with the nano wire part exposed as window cross growth epitaxial loayer.
2, heteroepitaxial growth process according to claim 1 is characterized in that: lattice mismatch surpasses 0.1% between backing material and the epitaxial film materials.
3, heteroepitaxial growth process according to claim 1 is characterized in that: the phase I, formed metal nanoparticle diameter was 10～500nm.
4, heteroepitaxial growth process according to claim 1, it is characterized in that: nanowire growth is as catalyst with metal nanoparticle in the second stage, grow vertically or favour the semiconductor column nano wire of substrate horizontal plane in the position of metallic particles, wherein the diameter of the diameter of nano wire and metallic particles is close.
5, heteroepitaxial growth process according to claim 1, it is characterized in that: phase III deposition mask layer makes nano wire and substrate be buried in the mask layer, make the top of nano wire expose via etching, grinding or ultrasonic method, and the bottom of nano wire and substrate surface are still coated by mask layer.
6, heteroepitaxial growth process according to claim 1 is characterized in that: the part of exposing with nano wire in the quadravalence section is carried out the transversal epitaxial growth semi-conducting material and is formed one deck continuous semiconductor epitaxial loayer as window.
7,, it is characterized in that described backing material is selected from following crystal: silicon, GaAs, indium phosphide or germanium according to arbitrary described heteroepitaxial growth process among the claim 1-6.
8, according to arbitrary described heteroepitaxial growth process among the claim 1-6, it is characterized in that: described epitaxial film materials is selected from III-V family semi-conducting material or IV family semi-conducting material.
9, heteroepitaxial growth process according to claim 8 is characterized in that: described epitaxial film materials is selected from GaAs, indium phosphide, gallium nitride, gallium phosphide, indium arsenide or germanium silicon.
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