CN101542726A - Semiconductor chip with through-silicon vias and side pads - Google Patents

Abstract

The invention disclosed herein relates to multi-chip semiconductor element packages that may be used in products such as flash memory. In one exemplary embodiment, the semiconductor chip may include through-silicon vias and side pads.

Description

Semiconductor chip with through-silicon vias and side pads

technical field

[0001] The invention disclosed herein relates to multi-chip semiconductor devices that may be used in, for example, flash memory devices.

Background of the invention

[0002] Integrated circuits have become basic components of many electronic devices. In some cases, it is useful to incorporate multiple integrated circuit wafers or "chips" within the same semiconductor device. For example, chips can be stacked on top of another chip, and in some cases chips can be electrically connected to each other by wire-bonding, and in other cases chips can be electrically connected to each other by through-silicon-via. connections, which can be electrically connected all the way through a silicon wafer. In this stacked die package structure, the bottom die may provide electrical connections to the substrate. The substrate redistributes signals and power to the stacked chips. The substrate may also be electrically connected to a printed circuit board, for example, via solder joints to allow the semiconductor device to interface with external devices and/or components. Multi-chip semiconductor devices can be used in a wide range of applications, including products such as flash memory.

Description of drawings

[0003] The inventive subject matter is particularly pointed out and distinctly described in the concluding portion of the specification. However, an understanding of its structure and/or method of operation, as well as its objects, features and/or advantages, may be understood by referring to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0004] FIG. 1a is a top view of an exemplary embodiment of a multi-chip semiconductor package;

[0005] FIG. 1b is a cross-sectional view of the exemplary semiconductor package of FIG. 1a;

[0006] FIG. 2a depicts an aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer;

[0007] FIG. 2b depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including bonding the wafer to a support;

[0008] FIG. 2c depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including thinning the wafer;

[0009] FIG. 2d depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including drilling holes;

[0010] FIG. 2e depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including forming an isolation layer;

[0011] FIG. 2f depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including forming an adhesion layer;

[0012] FIG. 2g depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including filling the vias;

[0013] FIG. 2h depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including forming a polymer layer;

[0014] FIG. 2i depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including forming solder bumps;

[0015] FIG. 2j depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer, including dicing the wafer;

[0016] FIG. 3 is a cross-sectional view of an exemplary embodiment of a semiconductor device including through-silicon vias and lateral interconnects;

[0017] FIG. 4 is a cross-sectional view of an exemplary embodiment of a stack of semiconductor chips; and

5 depicts a flow chart of an exemplary embodiment of a method of forming TSVs and side pads of a semiconductor chip;

[0019] FIG. 6 depicts a flowchart of an exemplary embodiment of a method of assembling an exemplary semiconductor device including through-silicon vias and side pad stacked chips.

[0020] Reference is made to the following detailed description of the accompanying drawings, which form a part hereof, wherein like numerals refer to like components throughout to indicate corresponding or analogous elements. For ease of description, it should be understood that elements depicted in the drawings are not necessarily drawn to actual size. For example, the size of some of the elements may be enlarged relative to other elements. Furthermore, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the present invention. It should also be noted that directions and numbers such as up, down, top, bottom, etc. may be used to facilitate discussion of the figures, but are not intended to limit the application of the invention. Therefore, the following detailed description and the scope of the present invention defined by the present invention and its equivalents are not limiting.

Detailed description of the invention

[0021] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. Accordingly, known methods, procedures, components and/or circuits will not be described in detail herein.

[0022] In the specification, "one embodiment" means that a particular feature, structure or characteristic described in this embodiment is included in at least one embodiment of the present invention. Thus, appearances of "in one embodiment" in various places in this specification do not necessarily refer to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any manner in one or more embodiments.

[0023] As mentioned above, in some electronic devices, many semiconductor chips can be arranged in a stacked manner so as to be able to increase operating capability while maintaining relatively low cost and small size. "Multi-chip" semiconductor devices can be widely used in the field of electronic equipment. For example, "stacked" arrangements of semiconductor chips are particularly useful within flash memory devices. Of course, other devices may take advantage of stacked semiconductor chip configurations as well as other multi-chip configurations.

[0024] One technique for stacking multiple chips includes wire bonding. Wire bonding may have some disadvantages, such as a relatively large form factor caused by a relatively large wire profile, and a high stack chip height when using wire bonding. Another disadvantage includes relatively poor electrical performance, such as signal delays caused by relatively long wire interconnects. TSV technology can at least partially avoid these potential disadvantages.

[0025] As described above, when implementing stacked semiconductor chips, the semiconductor chips may transmit signals from one chip to another chip using through-silicon vias (TSVs). As used herein, "through-silicon via" and its abbreviation TSV are meant to include any vertical electrical connection that passes completely through a silicon wafer, die, or chip. As used herein, "wafer" and "chip" are synonyms and may be used interchangeably. Generally, "wafer" refers to a rectangular segment of a semiconductor wafer.

[0026] While stacked semiconductor chips with TSVs may have some advantages, there are also some disadvantages. For example, TSVs are useful in providing common signals to individual semiconductor chips in a partial stack. Common signals may include, for example, address signals and/or data signals. As used herein, "common signal" refers to any signal that is to be shared among multiple stacked chips. In many embodiments, common signals may be shared among all stacked chips. Thus, TSVs pass common signals from chip to chip, and the signals will reach each intended chip. For example, if stacked chips form part of a flash memory device, address signals may need to be paired to individual semiconductor chips. TSVs can be quite efficient in providing these signals to the individual stack components. On the other hand, non-common signals, such as chip-selective signals, cannot be efficiently processed using TSVs. For non-shared signals, the use of TSVs may significantly increase the number of TSVs required, resulting in considerable die size and cost increases and failure rates.

[0027] Furthermore, it is advantageous to utilize existing semiconductor wafers, such as those designed for wire bonding implementations, such as TSV technology. However, if some TSV solutions are used without any changes to the wafer design, it may be difficult to accommodate enough TSV interconnects for shared and unshared signals due to space constraints. Of course, changing chip designs may require significant effort and sufficient resources. One or more embodiments described herein provide TSV interconnects without requiring changes to the die design and can accommodate shared and unshared signals.

[0028] In one embodiment, non-common signals can be routed from side pads on the semiconductor chip to a substrate, such as a substrate comprising bismaleimide triazine (BT), through a flexible side substrate . Furthermore, in the exemplary embodiment, one or more common signals may be routed to the substrate through one or more TSVs. As used herein, "uncommon signal" refers to a signal that is intended to go to fewer than all the chips in the stack. In various embodiments, unshared signals may only go to one chip, although the scope of the invention is not limited in this respect. In memory devices, examples of uncommon signals include, but are not limited to, chip select signals and power signals.

[0029] FIG. 1a is a top view of an exemplary embodiment of a multi-chip semiconductor package 100. As shown in FIG. The semiconductor package 100 in this example includes a semiconductor die stack 400 comprising a plurality of discrete semiconductor dies, each semiconductor die placed on top of another semiconductor die. In one embodiment, the chips may be bonded to each other at least in part by soldering over the plurality of TSV locations 130, and the physical bonding may be enhanced by a layer of polymer material between the chips. The semiconductor chip stack 400 of the present exemplary embodiment is electrically connected to the substrate 150 . In one exemplary embodiment, the substrate 150 may include bismaleimide triazine (BT), although the scope of the invention is not limited in this respect.

[0030] In one or more embodiments, semiconductor die stack 400 may be soldered to BT substrate 150 via TSV 130 and may utilize underfill of polymer material to enhance physical bonding, although the scope of the present invention is not limited by limited to these aspects.

[0031] Furthermore, in one embodiment, the semiconductor chip stack 400 may include one or more side substrates 140, which may also be referred to as side connectors herein. In one or more embodiments, the side substrate may comprise a flexible side substrate. For example, the side substrate may contain one or more metal signal lines on a flexible plastic standoff that may be glued to one or more side pads, although the scope of the invention is not limited in these respects.

FIG. 1 b is a cross-sectional view of a multi-chip semiconductor package 100 . This schematic diagram shows a semiconductor chip stack 400 with some TSVs 130 and side connectors 140 . The semiconductor chip stack 400 of this example is disposed on the BT substrate 150 and at least partially encapsulated by the material 170 . In one embodiment, the TSV 130 can electrically connect multiple common signals to the substrate 150 , while the side substrate 140 can electrically connect one or more non-common signals to the BT substrate 150 . In the embodiment depicted in FIGS. 1a and 1b, the multi-chip semiconductor package 100 may contain a NAND flash memory product, although the scope of the invention is not limited in this respect. In one or more embodiments, more than one chip type may be incorporated into a chip stack. Examples of such chip types that may be incorporated into a chip stack may include, but are not limited to, flash memory chips, dynamic random access memory (DRAM) chips, application specific integrated circuit (ASIC) chips, and the like.

[0033] In one embodiment, the side substrate 140 includes a pair of polymer layers that surround the copper layer. On the surface of the side substrate 400 facing the chip stack 400 , a plurality of bonding pads are formed, which can be connected to a plurality of side connectors on the chip of the chip stack 400 . In one embodiment, the bond pads may comprise copper with a nickel/gold finish. The bonding pads may be electrically connected to the middle metal layer of the side substrate 140 via via holes. Additionally, in one embodiment, the copper layer sandwiched between the two polymer layers may not be a continuous layer, but may contain a structure that redistributes signals from the chip stack 400 to the lower portion of the side substrate 400, In order to connect the signal to the BT substrate 150 . Of course, this is only an exemplary embodiment of a side substrate, and the scope of the present invention is not limited in this respect.

[0034] In one embodiment, semiconductor chip stack 400 may be protected by a molding material 170. In one exemplary embodiment, substrate 150 may also be at least partially protected, although in other embodiments, substrate 150 is not hermetically encapsulated by molding material 170 . In one exemplary embodiment, molding material 170 may include an epoxy polymer material, although the scope of the invention is not limited in this respect.

FIG. 2 a depicts one aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer 200 . Within the following illustrations, aspects of this exemplary technique will be described. Embodiments of the invention may include all, some or more of the various aspects described. Additionally, the order discussed is merely an exemplary order, so the scope of the invention is not limited in this respect. Embodiments of the invention are not limited to the exemplary techniques described herein. Also, any existing or future-developed technology for forming TSVs and side pads may be used. Furthermore, the specific materials described herein are used as examples only, so the scope of the present invention is not limited to the specific examples described herein.

公司或Samsung公司采购而来的。晶圆200可以包含多个集成电路210。为了清晰地进行描述，在此例子里描述两个集成电路210。当然，本发明的范围并不受限于此方面。在集成电路210内，可能有多个键合焊盘250，在一个示范实施例里，焊盘可能包含具有镍/金表面的铜。但是，这仅是一个键合焊盘的例子，所以本发明的范围并不受限于此方面。在键合焊盘和集成电路之间有一个重新分配层255来提供互联。[0036] In the example depicted in FIG. 2a, wafer 200 may comprise an input wafer, which may be obtained from a

purchased from the company or Samsung. Wafer 200 may contain a plurality of integrated circuits 210 . For clarity of description, two integrated circuits 210 are depicted in this example. Of course, the scope of the present invention is not limited in this respect. Within integrated circuit 210, there may be a plurality of bond pads 250, which in one exemplary embodiment may comprise copper with a nickel/gold surface. However, this is only an example of a bonding pad, so the scope of the present invention is not limited in this respect. There is a redistribution layer 255 between the bond pads and the integrated circuit to provide interconnection.

[0037] Generally, a wafer such as wafer 200 may be singulated into a plurality of individual chips, and in some cases, a plurality of chips may be stacked together. In practice, using wire bonding techniques to interconnect stacked chips, gold wires can be bonded to one bond pad and also bonded to the bond pad of another chip. TSV technology generally has several advantages over wire-bond-based chip stacks, including smaller size due to absence of wire loops, better electrical performance due to shorter interconnects, which can Reduce signal delay and power consumption. Other potential advantages may include ease of integration of various functional chip types, and lower overall manufacturing costs.

[0038] In one or more embodiments, in order to avoid redesigning the integrated circuit and/or die to provide sufficient space to accommodate TSV interconnects for uncommon signals, side connectors may be formed for uncommon signals. TSV interconnects can be used to share signals, which can take advantage of bond pads already fabricated on existing wafers. Wafer 200, originally designed for wire bonded die stacking applications, is in this example the starting point for the exemplary operations described in Figures 2b-2j.

[0039] In one embodiment, semiconductor wafer 200 includes a silicon layer 220. Furthermore, in one embodiment, integrated circuits 210 are supported within the silicon layer. Embodiments of the invention may include any type of integrated circuit, including but not limited to memory circuits. In addition, integrated circuit 210 may be formed using any known techniques or techniques developed in the future. As previously described, in one or more embodiments, wafer 200 may comprise a previously fabricated wafer including integrated circuits, redistribution layers, and bond pads.

FIG. 2 b depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer 200 . In one embodiment, a layer of polymer-based adhesive 240 is formed over the wafer, and wafer holder 230 may be bonded to wafer 200 . In one or more embodiments, bracket 230 may comprise glass. In another embodiment, bracket 230 may comprise silicon. However, these are merely exemplary materials that might be used for bracket 230, so the scope of the invention is not limited in this respect. Furthermore, in one embodiment, the polymer-based adhesive 240 can bond the wafer 200 to the holder 230 at a relatively low temperature, and the wafer can also be bonded by subjecting the adhesive 240 to a relatively high temperature. Unbond. In one embodiment, the glue 240 may comprise a thermoplastic polymer that provides a temporary bond at temperatures below about 150°C. Furthermore, in one embodiment, the wafer may be debonded from the holder 230 at a temperature in the range of approximately 180°C to 210°C. However, the scope of the present invention is not limited in these respects.

[0041] FIG. 2c depicts another aspect of an exemplary technique for forming TSVs and side pads of wafer 200. In one or more exemplary embodiments, silicon layer 220 may be thinned. That is, the thickness of the silicon layer 220 can be reduced. Although embodiments of the invention are not limited to any particular technique for reducing the thickness of the silicon layer, in one exemplary embodiment, the silicon layer is thinned by a mechanical grinding process. Other possible techniques for thinning the wafer 200 by reducing the thickness of the silicon layer 220 may include, but are not limited to, chemical mechanical polishing, wet etching, and dry chemical etching. In one or more embodiments, wafer 200 may have a thickness in the range of about 300-400 μm before thinning and may be in the range of about 50-100 μm after thinning, although not within the scope of the present invention. limited in this respect.

[0042] FIG. 2d depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer 200. In one or more embodiments, there are a plurality of vias 260 extending deep through silicon layer 220 to reach integrated circuit 210 . In this embodiment, the position of the through hole 260 is approximately the same as that of the previous through hole 255 . However, these are merely exemplary locations of vias, so the scope of the invention is not limited in this respect.

[0043] In one embodiment, a partially deep hole 265 is formed approximately halfway between the two integrated circuits. In one embodiment, the location of part of the deep hole 265 may be a location designed for die sawing. In one embodiment, the depth of the partial deep hole 265 is less than the depth of the through hole 260 . The scope of the present invention is not limited to any particular depth of the partially deep holes.

[0044] In one or more embodiments, via hole 260 and partial deep hole 265 may be formed using any known technique or a technique developed in the future. In an exemplary embodiment, the holes can be formed by a deep reactive ion etching (DRIE) process, including spin coating a layer of photoresist material (photoresist material) on the wafer surface, and exposing and developing the photoresist material to define The area that will be drilled. In another embodiment, a laser drilling method may be utilized. However, these are merely exemplary techniques for making the individual wells, so the scope of the invention is not limited in these respects.

FIG. 2 e depicts another aspect of an exemplary technique for forming TSVs and side pads of a semiconductor wafer 200 . In one or more embodiments, forming an isolation layer 225 under the wafer includes forming an isolation layer on the sidewalls of the vias 260 and on the bottom and sidewalls of some of the deep holes 265 . In one embodiment, isolation layer 225 may comprise silicon oxide (SiO ₂ ), although the scope of the invention is not limited in this respect, and other insulating materials are possible. As with other aspects described herein, the isolation layer 225 may be formed using any known technique or a technique developed in the future. In one embodiment, isolation layer 225 may comprise _SiO2 prepared by chemical vapor deposition (PECVD), and may be approximately 0.5 μm thick, although the scope of the invention is not limited in this respect.

[0046] FIG. 2f depicts another aspect of an exemplary technique for forming TSVs and side pads of wafer 200. In one embodiment, an adhesion layer 270 is formed on a portion of the bottom of the wafer 200 . As shown in FIG. 2 f , an adhesion layer 270 may be formed on the bottom surface of the wafer 200 in and around the through hole 260 and part of the deep hole 265 . The adhesion layer 270 may be adhered to the isolation layer 225 and the seed layer (not shown), which may be formed after the formation of the adhesion layer to provide an electrode for the electroplating process described below. The seed layer may comprise the same materials used in the filling operation described below, although the scope of the invention is not limited in this respect. In one embodiment, a sputtering technique may be used to form the adhesion layer 270 and seed layer, although the scope of the invention is not limited in this respect. In one embodiment, the adhesion layer 270 may also act as a spacer to avoid potential reactions between the copper conductor (not depicted in FIG. 2f ) and the exposed insulating material 225 or silicon layer 220 within the via. In one embodiment, the adhesion layer 270 may comprise titanium tungsten having a thickness of approximately 0.1 to 0.2 μm, although the scope of the invention is not limited in this respect.

[0047] FIG. 2g depicts another aspect of an exemplary technique for forming TSVs and side pads of wafer 200. In one embodiment, a conductive material is filled in the through hole 260 and part of the deep hole 265 . For example, copper can be filled inside the holes. In another exemplary embodiment, the holes may be filled with polysilicon. Other exemplary materials that may be used include, but are not limited to, gold, solder, tungsten, conductive glue, and the like. However, these are merely exemplary conductive materials, so the scope of the present invention is not limited in this respect. In one or more embodiments, exemplary techniques for depositing conductive material may include, but are not limited to, electroless plating, immersion plating, solder printing, conductive paste printing or placement, and electrolytic plating techniques. TSVs are formed by depositing a conductive material within via 260 with a conductive path extending completely through silicon layer 220 from bond pad 250 at the location of via 235 previously made to pad 290 at the location of via 260 .

[0048] FIG. 2h depicts another aspect of an exemplary technique for forming TSVs and side pads of wafer 200. In one or more embodiments, a layer 295 of polymer material is deposited on the underside of the wafer 200 . Polymer layer 295 may provide additional structural integrity and may provide a surface for bonding to another semiconductor chip, for example, if implemented using a laminate. Additionally, the polymer layer 295 can be positioned to make a pad on top of a filled via to ensure that the pad does not touch another solder joint and cause a short circuit. In an exemplary embodiment, polymer material 295 may comprise polyamine (PI) or benzocyclobutene (BCB), although the scope of the invention is not limited in this respect. Also, in one embodiment, polymer layer 295 may be formed by spin coating and curing techniques, although the scope of the invention is not limited in this respect.

[0049] FIG. 2i depicts another aspect of an exemplary technique for forming TSVs and side pads of wafer 200. In one embodiment, the deposition pad 290 is in an area approximately coincident with the location of the via 260 . In one or more embodiments, pad 290 may comprise tin, tin/lead composite, tin/copper composite, tin/silver/copper composite, tin/indium composite, tin/gold composite, etc., although The scope of the invention is not limited in this respect. Exemplary techniques for forming pads 290 may include, but are not limited to, electroplating and/or solder paste micro-printing. As otherwise described herein, embodiments of the invention are not limited to any particular technique for depositing pads.

[0050] FIG. 2j depicts another aspect of an exemplary technique for forming TSVs and side pads of wafer 200. In this exemplary embodiment, two integrated circuits are depicted in Figures 2a-2j. Of course, other embodiments may generally include a greater number of integrated circuit dies. However, in this example, two integrated circuits are intended to describe a technique for forming side pads 235 . In one embodiment, when the wafer 200 is diced, a portion of the deep hole 265 is segregated, as described in FIG. 2j , and the conductive material 280 forms a pair of side pads 235 . One of the pair of side pads is connected to an integrated circuit, and the other side pad is connected to another integrated circuit. In this embodiment, wafer dicing 299 separates wafer 200 into two distinct chips. Furthermore, in one or more embodiments, the wafer 200 can be debonded from the holder 240 by increasing the temperature above 180°C.

[0051] In the example depicted in FIG. 2j, the side pad 235 is electrically connected to the TSV. However, in other exemplary embodiments, there may be individual conductive paths connecting the side pads to the integrated circuit. For example, the polymer layer 295 may comprise the conductive material of the TSV, connect to the side pads, but not provide solder pads, so that there is an isolated conductive path between the side pads and the integrated circuit.

FIG. 3 depicts a cross-sectional view of an exemplary embodiment of a semiconductor chip 300 . In one or more embodiments, chip 300 may include a silicon layer 320 . Although not shown in FIG. 3 , semiconductor device 300 may include an integrated circuit formed on silicon layer 320 . A plurality of TSVs 340 extend through the silicon layer 320 and the polymer layer 310 . In this embodiment, there are a plurality of bonding pads 350 on the upper surface of the silicon layer. As previously mentioned, bond pads 350 would already be present if the wafer had been designed and fabricated for wire bonding. As shown in FIG. 4 , the bonding pad 350 is located on top of the TSV 340 and on top of the via connected to the side pad 330 . Of course, the vias may be formed according to the exemplary techniques described above. It should be noted that the vias connected to the side pads 330 do not extend completely through the polymer layer 310 to avoid contacting the bonding pads of a chip below the chip 300 in the stack. Furthermore, in one embodiment, a solder pad 390 may also be formed on the TSV 340. Note that for TSV 340, there is a pair of pads. Bond pads 350 are already present on the wafer, and solder pads 390 are formed according to exemplary techniques described herein.

[0053] TSV 340 may be connected to one or more common signals of the integrated circuit, while side pad 330 may be connected to one or more uncommon signals connected to the integrated circuit. As shown in FIG. 4 below, a plurality of semiconductor chips such as chip 300 may be stacked on top of each other, and TSVs provide common signal interconnections between the chips. Although the exemplary embodiments described herein refer to shared signals connected to TSVs and non-shared signals connected to side pads, the scope of the present invention is not so limited and other embodiments are possible, namely one or more One unshared signal can be connected to the TSV, and one or more shared signals can be connected to the side pad.

[0054] FIG. 4 depicts a cross-sectional view of an exemplary embodiment of a stack 400 of semiconductor chips. In the example depicted in FIG. 4, the semiconductor die stack 400 includes a NAND flash memory stack. In one embodiment, the chips of chip stack 400 may comprise similar chips. In one or more other embodiments, the chips of chip stack 400 may comprise different types of chips. In an exemplary embodiment, the chip stack may include one or more NAND flash chips, DRAM chips, and ASIC chips. Of course, these are merely examples of the types of chips that may make up a chip stack, and the scope of the invention is not limited in this respect. Again, in this example, four semiconductor chips are described, although the scope of the invention is not limited in this respect, and other embodiments may utilize any number of chips.

[0055] In one or more exemplary embodiments, the semiconductor chips of stack 400 may include elements similar to semiconductor chip 300 as described in FIG. 3, such as integrated circuits formed within a silicon layer. A plurality of through-silicon vias extend through the silicon and polymer layers of the plurality of chips. In one embodiment, a plurality of bond pads are formed on the upper surface of the silicon layer, and as previously described, the bond pads are located approximately on top of the TSVs and also on top of the vias connected to the side pads. . In this exemplary embodiment, the vias connected to the side pads do not extend completely through the polymer layer to avoid the vias from contacting the bond pads of a chip below the current chip in the stack. As with other embodiments described herein, the TSVs may be connected to one or more common signals of the integrated circuit, while the side pads may be connected to one or more uncommon signals connected to the integrated circuit. Furthermore, in one or more embodiments, the bonding pads of the first chip may be electrically connected to a second chip placed on top of the first chip by connection of the solder pads. Solder pads are described above in connection with FIG. 3 for an embodiment. In the example of FIG. 4 , there are a plurality of bond pad/solder pad connections 445 between the individual chips of the chip stack 400 .

[0056] In the present embodiment, the semiconductor chip stack is mounted on the connector 430. The receptacle 430 may contain signal lines for distributing signals to and receiving signals from the TSVs. For example, receptacle 430 may include common signal pads 440 which, in one exemplary embodiment, may be soldered to substrate 450, which may subsequently be soldered to a printed circuit board (not shown). In the example depicted in FIG. 4 , common signals from chip stack 400 are connected to the top of connector 430 . In this exemplary embodiment, the receptacle 430 can redistribute common signals, and the signals can also be connected to the bonding pads on the bottom of the receptacle, and then soldered to the substrate 450 . In one or more embodiments, interposer 430 may comprise silicon, although the scope of the invention is not limited in this respect. In one or more embodiments, substrate 450 may comprise bismaleimide triazine (BT), although the scope of the invention is not limited in this respect.

[0057] As described in FIG. 4, the side substrate 410 is connected to a plurality of side pads. As with other embodiments described herein, the side pads may be connected to one or more non-common signals. In the exemplary embodiment, where the semiconductor die stack 400 includes a NAND flash memory stack, one or more uncommon signals may include chip select signals. In one embodiment, the chip select signal may be electrically connected to the substrate 450 . The side substrate 410 of this example may include non-common signal pads 420 . Of course, the chip select signal is just one example of the type of signal that can be transmitted via the side pads and the side substrate. In one or more exemplary embodiments, side substrate 410 may include a flexible side substrate.

[0058] As previously mentioned, in one embodiment, the flexible side substrate may comprise a pair of polymer layers sandwiching a layer of copper. However, this is only an exemplary embodiment of a side substrate, so the scope of the present invention is not limited in this respect.

[0059] FIG. 5 is a flowchart of an exemplary embodiment of a method of forming TSVs and side pads of a semiconductor chip. Various aspects of the exemplary method are described in detail with reference to Figures 2a-2j. At block 510, the wafer with at least one integrated circuit is bonded to a support, and at block 520, the wafer is thinned. At block 530, vias are etched, and at block 540, an isolation layer is formed. At block 550, an adhesive layer is formed on at least a portion of the release layer. At block 560, the vias are filled, and at block 570, a polymer matrix is formed. At block 580, solder is plated on the filled vias, and at block 590, the wafer is diced. Embodiments of the invention may include all, some, or more of the modules 510-590. Furthermore, the order of blocks 510-590 is merely an exemplary order, and the scope of the invention is not limited in this respect.

[0060] FIG. 6 is a flowchart of an exemplary embodiment of a method of assembling a semiconductor device of stacked chips having TSVs and side pads. At block 610, a connector is fabricated with TSV interconnects that mate with the bottom chip of the final chip stack, and at block 620, the bottom chip is mounted on the connector. At block 630, if it is determined that there are other chips to be mounted on the stack, at block 640, the next chip is added to the stack. At block 630, if it is determined that there are no other chips, at block 650, a side substrate is bonded to the side pads of the stacked chip. At block 660, the side substrates are bonded to a bottom substrate, and at block 670, solder is reflowed to secure the solder joints of the connector to the bottom substrate. Of course, embodiments of the present invention may include all, some or more of the modules 610-670. Also, the order of blocks 610-670 is merely an exemplary order, so the scope of the invention is not limited in this respect.

Being called "and/or" herein may refer to "and", may refer to "or", may refer to "exclusive or", may refer to "one of them", may refer to " Some, but not all," may mean "neither," and/or may mean "both," although the scope of the invention is not limited in this respect.

[0062] In the foregoing description, various aspects of the invention have been described. For explanatory purposes, specific numbers, systems and/or configurations are set forth in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details to obtain the benefits of the present disclosure. For example, known features may be omitted and/or simplified in order to enable a clear understanding of the invention. While certain features of the invention have been described and/or illustrated herein, numerous improvements, substitutions, changes and/or equivalents will occur to those skilled in the art. Therefore, it is to be understood that the appended claims are intended to cover all modifications and/or changes that fall within the spirit and scope of the invention.

Claims (30)

1. A device comprising: a plurality of semiconductor chips arranged in a stack, the plurality of chips comprising one or more through-silicon vias and one or more side pads; and A side substrate, which is electrically connected to one or more side pads. 2. The apparatus of claim 1, one or more through-silicon vias electrically connecting one or more common signals from a plurality of semiconductor chips to a base substrate. 3. The apparatus of claim 1, one or more TSVs electrically connecting one or more common signals from a plurality of semiconductor chips to an interposer, the interposer being electrically connected to a bottom substrate. 4. The device of claim 3, wherein the side substrates are electrically connected to the bottom substrate. 5. The device of claim 4, one or more side pads electrically connecting one or more non-common signals from the plurality of semiconductor chips to the bottom substrate through the side substrate. 6. The device of claim 5, wherein the bottom substrate comprises bismaleimide triazine (BT). 7. The device of claim 1, wherein the side substrate comprises a flexible side substrate comprising two polymer layers sandwiching a conductive layer. 8. The apparatus of claim 3, wherein the one or more common signals comprise one or more address signals and/or data signals. 9. The apparatus of claim 5, wherein the one or more unshared signals comprise one or more chip select signals and/or power signals. 10. The apparatus of claim 1, wherein the plurality of semiconductor chips comprises one or more flash memory chips, dynamic random access memory chips, and/or application specific integrated circuit chips. 11. A multi-chip semiconductor package comprising: A plurality of semiconductor chips are arranged in a stacked manner, and the plurality of semiconductor chips include one or more through-silicon vias and one or more side pads; a side substrate electrically connected to one or more side pads; and A bottom substrate is electrically connected to the one or more side pads via the side substrate, and the bottom substrate is electrically connected to the one or more through-silicon vias. 12. The multi-chip semiconductor package of claim 11 , further comprising an interposer disposed between the plurality of semiconductor chips and the base substrate, the interposer routing one or more signals from one or more TSVs electrically connected to the bottom substrate. 13. The multi-chip semiconductor package of claim 11, wherein the plurality of semiconductor chips includes one or more flash memory chips, dynamic random access memory chips, and/or application specific integrated circuit chips. 14. The multi-chip semiconductor package of claim 11, one or more side pads electrically connecting one or more non-common signals from the bottom substrate to the one or more semiconductor chips through the side substrate. 15. The multi-chip semiconductor package of claim 11, one or more through silicon vias electrically connecting one or more common signals from the interposer to the plurality of semiconductor chips. 16. The multi-chip semiconductor package of claim 11, wherein the side substrate comprises a flexible side substrate comprising a conductive layer protected by two layers of polymer material. 17. A method comprising: Through-silicon vias and side pads are formed on one or more semiconductor chips of a wafer, the vias are electrically connected to the first signal of the first integrated circuit formed on the silicon layer, and the side pads are electrically connected to The second signal of the first integrated circuit. 18. The method of claim 17, the first signal comprising a shared signal and the second signal comprising a non-shared signal. 19. The method of claim 18, wherein the common signal comprises an address signal and the uncommon signal comprises a chip select signal. 20. The method according to claim 17, wherein said forming TSVs and side pads comprises: A wafer is provided, wherein the wafer includes a plurality of bond pads on a silicon layer, the plurality of bond pads includes one or more bond pads electrically connected to a first integrated circuit, and includes a One or more bond pads electrically connected to the second integrated circuit formed on it. 21. The method according to claim 20, wherein said forming TSVs and side pads further comprises: forming a polymer-based adhesive on the silicon layer, the polymer-based adhesive at least partially protecting the bond pads; and Adhere the wafer to a holder. 22. The method of claim 21, wherein said forming TSVs and side pads further comprises thinning the wafer. 23. The method according to claim 22, wherein said forming TSVs and side pads further comprises: forming a plurality of vias, wherein the positions of the plurality of vias approximately coincide with the positions of the plurality of bond pads; and A further hole is formed between the first and second integrated circuits at a location designed for wafer dicing, wherein said further hole extends less than the entire thickness of the silicon layer. 24. The method according to claim 23, wherein said forming through-silicon vias and side pads further comprises: at the bottom of the silicon layer, at the sidewalls of a plurality of through-holes, and at the sidewall and bottom of another hole form an isolation layer. 25. The method according to claim 24, wherein said forming TSVs and side pads further comprises: forming an adhesion layer and a seed layer in the plurality of TSVs and another hole. 26. The method according to claim 25, wherein said forming the TSV and the side pad further comprises: filling a conductive material into the TSV and the other hole. 27. The method according to claim 26, wherein said forming TSVs and side pads further comprises: forming a polymer layer at the bottom of the wafer, the polymer layer at least partially leaves exposed vias and another conductive material in the hole. 28. The method of claim 27, wherein said forming TSVs and side pads further comprises: forming solder on the conductive material at locations approximately coincident with at least some of the vias. 29. The method according to claim 28, wherein said forming TSVs and side pads further comprises: cutting the wafer at a position approximately coincident with the center of another hole, so that the sidewall of another hole is formed A pair of side pads, one of which is connected to the first integrated circuit and the other is connected to the second integrated circuit. 30. A method comprising: Fabricate an interposer that contains TSV interconnects that mate with the bottom chip of the chip stack; The bottom chip of the stack is on the socket; Stack one or more other chips on top of the bottom chip; electrically connecting a side substrate to one or more side pads of one or more stacked chips; electrically connecting the side substrates to a bottom substrate; and Electrically connect the header to the bottom substrate.

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