CN107994001A - A kind of chip package and terminal device - Google Patents
A kind of chip package and terminal device Download PDFInfo
- Publication number
- CN107994001A CN107994001A CN201711217201.7A CN201711217201A CN107994001A CN 107994001 A CN107994001 A CN 107994001A CN 201711217201 A CN201711217201 A CN 201711217201A CN 107994001 A CN107994001 A CN 107994001A
- Authority
- CN
- China
- Prior art keywords
- chip
- package substrate
- package
- pad
- side pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The embodiment of the invention discloses a kind of chip package, including chip, package substrate and weldable material, the side of package substrate is equipped with side pad, and the functional pin of chip is connected on the side pad of package substrate by semiconductor leads technique；Weldable material is arranged at the pad of side.As it can be seen that the weldable material in the embodiment of the present invention is arranged at the side pad of package substrate, and side pad is arranged at the side of package substrate, reduces the integral thickness of chip package, is more advantageous to the lightening of terminal device.An embodiment of the present invention provides a kind of terminal device for including said chip encapsulation, is more advantageous to lightening, lifting user experience.
Description
Technical field
The present embodiments relate to chip encapsulation technology field, more particularly to a kind of chip package.The embodiment of the present invention
Further relate to a kind of terminal device.
Background technology
With the development of science and technology, requirement of the user to electronic product is higher and higher, promote the trend that electronic product is lightening
More and more obvious, the height of surface mount elements has a certain impact the whole height tool of electronic product in electronic product, so
The lightening of chip package is conducive to the lightening of electronic product.In the prior art, the weldable material for encapsulating chip is arranged on
The bottom of package substrate, so as to add the thickness of chip package, is unfavorable for the lightening of electronic product.
In consideration of it, how to provide a kind of chip package for solving above-mentioned technical problem and terminal device becomes art technology
Personnel's urgent problem to be solved.
The content of the invention
The purpose of the embodiment of the present invention is to provide a kind of chip package, reduces the integral thickness of chip package, more favorably
In the lightening of terminal device.The another object of the embodiment of the present invention is to provide a kind of terminal including said chip encapsulation and sets
It is standby, it is more advantageous to lightening, lifting user experience.
In order to solve the above technical problems, an embodiment of the present invention provides a kind of chip package, including chip, package substrate and
Weldable material, the side of the package substrate are equipped with side pad, and the functional pin of the chip passes through semiconductor leads work
Skill is connected on the side pad of the package substrate；The weldable material is arranged at the side pad.
Optionally, the functional pin of the chip is connected to the package substrate by way of the lead of semiconductor side
On the pad of side.
Optionally, the functional pin of the chip is connected to the package substrate by way of semiconductor perforates lead
On the pad of side.
Optionally, the chip is COB bare chips.
Optionally, the weldable material is tin ball.
Optionally, the side pad is distributed on described two opposite sides of package substrate.
A kind of terminal device, including chip package as described above.
An embodiment of the present invention provides a kind of chip package, including chip, package substrate and weldable material, package substrate
Side be equipped with side pad, the functional pin of chip is connected to the side pad of package substrate by semiconductor leads technique
On；Weldable material is arranged at the pad of side.As it can be seen that the weldable material in the embodiment of the present invention is arranged at package substrate
At the pad of side, and side pad is arranged at the side of package substrate, reduces the integral thickness of chip package, is more advantageous to
Terminal device it is lightening.
An embodiment of the present invention provides a kind of terminal device for including said chip encapsulation, is more advantageous to lightening, lifting
User experience.
Brief description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of overlooking the structure diagram of chip package provided in an embodiment of the present invention；
Fig. 2 is a kind of overlooking the structure diagram of package substrate provided in an embodiment of the present invention；
Fig. 3 is a kind of diagrammatic cross-section of chip package provided in an embodiment of the present invention；
Fig. 4 is connected to side for a kind of functional pin of chip provided in an embodiment of the present invention by semiconductor side lead
The structure diagram of pad；
Fig. 5 is connected to side for a kind of functional pin of chip provided in an embodiment of the present invention by semiconductor perforation lead
The structure diagram of pad.
Embodiment
An embodiment of the present invention provides a kind of chip package, reduces the integral thickness of chip package, is more advantageous to terminal
Equipment it is lightening；The embodiment of the present invention additionally provides a kind of terminal device for including said chip encapsulation, is more advantageous to frivolous
Change, lift user experience.
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiments obtained without making creative work, belong to the scope of protection of the invention.
It refer to Fig. 1 first, Fig. 1 is a kind of structure diagram of chip package provided in an embodiment of the present invention.
The chip package, including chip 1, package substrate 2 and weldable material 3, the side of package substrate 2 are welded equipped with side
Disk 21, the functional pin of chip 1 are connected on the side pad 21 of package substrate 2 by semiconductor leads technique；Solderable material
Material 3 is arranged at side pad 21.
Specifically, the side pad 21 of package substrate 2 is set with specific reference to the functional pin distribution on chip 1, such as
Shown in Fig. 2, the side pad 21 of package substrate 2 can be semicircle, it is of course also possible to for it is square, non-hollow out, protrusion etc. other
The pad of shape, the application are not specifically limited this.
It should be noted that the Outside Dimensions of the chip 1 in the embodiment of the present invention are slightly less than the peripheral ruler of package substrate 2
It is very little, make the surface area of chip 1 close to the surface area of package substrate 2, and then reduce the volume of chip package.Chip 1 is arranged at
On package substrate 2, the functional pin of chip 1 is connected on side pad 21 by semiconductor leads technique, and weldable material 3 is set
The side of side pad 21 is placed in, side pad 21 can be specifically close to and (as shown in Figure 3) is set, easy to which chip package is answered
With when on corresponding substrate, chip package directly can be soldered to by corresponding terminal by laser burns weldable material 3 and set
On standby substrate, since weldable material 3 is arranged at the side of package substrate 2, so as to reduce the thickness of chip package,
There is no the fusing thing of weldable material between the bottom of welding process chips encapsulation and the substrate of corresponding terminal equipment, favorably yet
In the height for reducing whole terminal device.
Further, as Fig. 4, the functional pin of chip 1 can be connected to encapsulation by way of the lead of semiconductor side
On the side pad 21 of substrate 2, the functional pin of specific chip 1 is connected to encapsulation by the package lead in Fig. 4 from side
On the side pad 21 of substrate 2.Or the side of lead as shown in figure 5, the functional pin of chip 1 can also be perforated by semiconductor
Formula is connected on the side pad 21 of package substrate 2, is specifically punched at the functional pin of chip 1, and pass through the envelope in Fig. 5
Lead is filled from hole by the way that the functional pin of chip 1 is connected on the side pad 21 of package substrate 2.
Certainly, the functional pin of chip 1 is not limited only to be connected to the side pad of package substrate 2 using above two mode
On 21, other modes can also be used to be connected on side pad 21, do not limited specifically.
Specifically, chip 1 is COB bare chips.
It should be noted that the chip 1 in the embodiment of the present invention can be the COB bare chips suitable for camera module,
It can be the chip suitable for other-end equipment, such as other kinds of semiconductor or non-semiconductor chip, not limit specifically
It is fixed.
Further, weldable material 3 is tin ball.
Specifically, tin ball can be planted at the side pad 21 of package substrate 2.Certainly, the side pad of package substrate 2
Packing material at 21 is not limited only to plantation tin ball, or gold goal or other metal materials, it is specific unlimited.In addition,
Weldable material is set at side pad 21, can also be specifically the other forms such as affixed metal piece.
More specifically, side pad 21 is distributed on 2 two opposite sides of package substrate.
Specifically, the distribution situation of side pad 21 should be configured according to the functional pin situation of chip 1, for example, can
To be arranged on the two of package substrate 2 opposite sides, can also be arranged on two adjacent sides, it is, of course, also possible to
It is arranged in the surrounding of package substrate 2, or 3 sides, does not limit specifically.
An embodiment of the present invention provides a kind of chip package, including chip, package substrate and weldable material, package substrate
Side be equipped with side pad, the functional pin of chip is connected to the side pad of package substrate by semiconductor leads technique
On；Weldable material is arranged at the pad of side.As it can be seen that the weldable material in the embodiment of the present invention is arranged at package substrate
At the pad of side, and side pad is arranged at the side of package substrate, reduces the integral thickness of chip package, is more advantageous to
Terminal device it is lightening.
On the basis of above-described embodiment, an embodiment of the present invention provides a kind of terminal device, including chip envelope as above
Dress.
It should be noted that terminal device provided in an embodiment of the present invention, is more advantageous to lightening, lifting user experience.
In addition, refer to above-described embodiment for specific introduce of chip package involved in the embodiment of the present invention, the application exists
This is repeated no more.
It should also be noted that, in the present specification, such as term " comprising ", "comprising" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only include that
A little key elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged
Except also there are other identical element in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide scope caused.
Claims (7)
- A kind of 1. chip package, it is characterised in that including chip, package substrate and weldable material, the side of the package substrate Side is equipped with side pad, and the functional pin of the chip is connected to the side weldering of the package substrate by semiconductor leads technique On disk；The weldable material is arranged at the side pad.
- 2. chip package according to claim 1, it is characterised in that the functional pin of the chip passes through semiconductor side The mode of lead is connected on the side pad of the package substrate.
- 3. chip package according to claim 1, it is characterised in that the functional pin of the chip is perforated by semiconductor The mode of lead is connected on the side pad of the package substrate.
- 4. the chip package according to Claims 2 or 3, it is characterised in that the chip is COB bare chips.
- 5. according to the chip package described in claim 1-3 any one, it is characterised in that the weldable material is tin ball.
- 6. chip package according to claim 5, it is characterised in that the side pad is distributed in the package substrate two On a opposite side.
- 7. a kind of terminal device, it is characterised in that including the chip package as described in 1 and 6 any one of claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711217201.7A CN107994001A (en) | 2017-11-28 | 2017-11-28 | A kind of chip package and terminal device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711217201.7A CN107994001A (en) | 2017-11-28 | 2017-11-28 | A kind of chip package and terminal device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107994001A true CN107994001A (en) | 2018-05-04 |
Family
ID=62033976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711217201.7A Pending CN107994001A (en) | 2017-11-28 | 2017-11-28 | A kind of chip package and terminal device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107994001A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6118164A (en) * | 1984-07-04 | 1986-01-27 | Mitsubishi Electric Corp | Semiconductor device |
| JP2006066646A (en) * | 2004-08-26 | 2006-03-09 | Kyocera Corp | Piezo-electric element housing package and piezo-electric device |
| CN201403145Y (en) * | 2009-04-30 | 2010-02-10 | 广州大凌实业股份有限公司 | Lateral contact CMOS image sampling module group |
| KR20100020766A (en) * | 2008-08-13 | 2010-02-23 | 주식회사 하이닉스반도체 | Stack package |
| CN101542726B (en) * | 2008-11-19 | 2011-11-30 | 香港应用科技研究院有限公司 | Semiconductor chip with silicon through holes and side bonding pads |
| CN104124216A (en) * | 2014-07-03 | 2014-10-29 | 天水华天科技股份有限公司 | Substrate chip carrier CSP package and production method thereof |
-
2017
- 2017-11-28 CN CN201711217201.7A patent/CN107994001A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6118164A (en) * | 1984-07-04 | 1986-01-27 | Mitsubishi Electric Corp | Semiconductor device |
| JP2006066646A (en) * | 2004-08-26 | 2006-03-09 | Kyocera Corp | Piezo-electric element housing package and piezo-electric device |
| KR20100020766A (en) * | 2008-08-13 | 2010-02-23 | 주식회사 하이닉스반도체 | Stack package |
| CN101542726B (en) * | 2008-11-19 | 2011-11-30 | 香港应用科技研究院有限公司 | Semiconductor chip with silicon through holes and side bonding pads |
| CN201403145Y (en) * | 2009-04-30 | 2010-02-10 | 广州大凌实业股份有限公司 | Lateral contact CMOS image sampling module group |
| CN104124216A (en) * | 2014-07-03 | 2014-10-29 | 天水华天科技股份有限公司 | Substrate chip carrier CSP package and production method thereof |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180504 |